From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: "José Roberto de Souza" <jose.souza@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH v4 1/5] drm/i915/display: Replace drm_i915_private in voltage swing functions by intel_encoder
Date: Thu, 9 Jul 2020 17:10:55 +0300 [thread overview]
Message-ID: <20200709141055.GC6112@intel.com> (raw)
In-Reply-To: <20200708205512.21625-1-jose.souza@intel.com>
On Wed, Jul 08, 2020 at 01:55:08PM -0700, José Roberto de Souza wrote:
> intel_encoder will be needed inside of vswing functions in a future
> patch, so here doing this change in all vswing functions since HSW.
>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 164 +++++++++++++----------
> 1 file changed, 95 insertions(+), 69 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 5773ebefffc7..e80319aa7cf0 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -707,8 +707,10 @@ static const struct cnl_ddi_buf_trans tgl_combo_phy_ddi_translations_dp_hbr2[] =
> };
>
> static const struct ddi_buf_trans *
> -bdw_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
> +bdw_get_buf_trans_edp(struct intel_encoder *encoder, int *n_entries)
> {
> + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> +
> if (dev_priv->vbt.edp.low_vswing) {
> *n_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
> return bdw_ddi_translations_edp;
> @@ -719,8 +721,10 @@ bdw_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
> }
>
> static const struct ddi_buf_trans *
> -skl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
> +skl_get_buf_trans_dp(struct intel_encoder *encoder, int *n_entries)
> {
> + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> +
> if (IS_SKL_ULX(dev_priv)) {
> *n_entries = ARRAY_SIZE(skl_y_ddi_translations_dp);
> return skl_y_ddi_translations_dp;
> @@ -734,8 +738,10 @@ skl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
> }
>
> static const struct ddi_buf_trans *
> -kbl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
> +kbl_get_buf_trans_dp(struct intel_encoder *encoder, int *n_entries)
> {
> + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> +
> if (IS_KBL_ULX(dev_priv) ||
> IS_CFL_ULX(dev_priv) ||
> IS_CML_ULX(dev_priv)) {
> @@ -753,8 +759,10 @@ kbl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
> }
>
> static const struct ddi_buf_trans *
> -skl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
> +skl_get_buf_trans_edp(struct intel_encoder *encoder, int *n_entries)
> {
> + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> +
> if (dev_priv->vbt.edp.low_vswing) {
> if (IS_SKL_ULX(dev_priv) ||
> IS_KBL_ULX(dev_priv) ||
> @@ -777,9 +785,9 @@ skl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
> if (IS_KABYLAKE(dev_priv) ||
> IS_COFFEELAKE(dev_priv) ||
> IS_COMETLAKE(dev_priv))
> - return kbl_get_buf_trans_dp(dev_priv, n_entries);
> + return kbl_get_buf_trans_dp(encoder, n_entries);
> else
> - return skl_get_buf_trans_dp(dev_priv, n_entries);
> + return skl_get_buf_trans_dp(encoder, n_entries);
> }
>
> static const struct ddi_buf_trans *
> @@ -807,19 +815,21 @@ static int skl_buf_trans_num_entries(enum port port, int n_entries)
> }
>
> static const struct ddi_buf_trans *
> -intel_ddi_get_buf_trans_dp(struct drm_i915_private *dev_priv,
> +intel_ddi_get_buf_trans_dp(struct intel_encoder *encoder,
> enum port port, int *n_entries)
> {
> + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> +
> if (IS_KABYLAKE(dev_priv) ||
> IS_COFFEELAKE(dev_priv) ||
> IS_COMETLAKE(dev_priv)) {
> const struct ddi_buf_trans *ddi_translations =
> - kbl_get_buf_trans_dp(dev_priv, n_entries);
> + kbl_get_buf_trans_dp(encoder, n_entries);
> *n_entries = skl_buf_trans_num_entries(port, *n_entries);
> return ddi_translations;
> } else if (IS_SKYLAKE(dev_priv)) {
> const struct ddi_buf_trans *ddi_translations =
> - skl_get_buf_trans_dp(dev_priv, n_entries);
> + skl_get_buf_trans_dp(encoder, n_entries);
> *n_entries = skl_buf_trans_num_entries(port, *n_entries);
> return ddi_translations;
> } else if (IS_BROADWELL(dev_priv)) {
> @@ -835,16 +845,18 @@ intel_ddi_get_buf_trans_dp(struct drm_i915_private *dev_priv,
> }
>
> static const struct ddi_buf_trans *
> -intel_ddi_get_buf_trans_edp(struct drm_i915_private *dev_priv,
> +intel_ddi_get_buf_trans_edp(struct intel_encoder *encoder,
> enum port port, int *n_entries)
> {
> + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> +
> if (IS_GEN9_BC(dev_priv)) {
> const struct ddi_buf_trans *ddi_translations =
> - skl_get_buf_trans_edp(dev_priv, n_entries);
> + skl_get_buf_trans_edp(encoder, n_entries);
> *n_entries = skl_buf_trans_num_entries(port, *n_entries);
> return ddi_translations;
> } else if (IS_BROADWELL(dev_priv)) {
> - return bdw_get_buf_trans_edp(dev_priv, n_entries);
> + return bdw_get_buf_trans_edp(encoder, n_entries);
> } else if (IS_HASWELL(dev_priv)) {
> *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
> return hsw_ddi_translations_dp;
> @@ -871,9 +883,11 @@ intel_ddi_get_buf_trans_fdi(struct drm_i915_private *dev_priv,
> }
>
> static const struct ddi_buf_trans *
> -intel_ddi_get_buf_trans_hdmi(struct drm_i915_private *dev_priv,
> +intel_ddi_get_buf_trans_hdmi(struct intel_encoder *encoder,
> int *n_entries)
> {
> + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> +
> if (IS_GEN9_BC(dev_priv)) {
> return skl_get_buf_trans_hdmi(dev_priv, n_entries);
> } else if (IS_BROADWELL(dev_priv)) {
> @@ -889,33 +903,36 @@ intel_ddi_get_buf_trans_hdmi(struct drm_i915_private *dev_priv,
> }
>
> static const struct bxt_ddi_buf_trans *
> -bxt_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
> +bxt_get_buf_trans_dp(struct intel_encoder *encoder, int *n_entries)
> {
> *n_entries = ARRAY_SIZE(bxt_ddi_translations_dp);
> return bxt_ddi_translations_dp;
> }
>
> static const struct bxt_ddi_buf_trans *
> -bxt_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
> +bxt_get_buf_trans_edp(struct intel_encoder *encoder, int *n_entries)
> {
> + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> +
> if (dev_priv->vbt.edp.low_vswing) {
> *n_entries = ARRAY_SIZE(bxt_ddi_translations_edp);
> return bxt_ddi_translations_edp;
> }
>
> - return bxt_get_buf_trans_dp(dev_priv, n_entries);
> + return bxt_get_buf_trans_dp(encoder, n_entries);
> }
>
> static const struct bxt_ddi_buf_trans *
> -bxt_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
> +bxt_get_buf_trans_hdmi(struct intel_encoder *encoder, int *n_entries)
> {
> *n_entries = ARRAY_SIZE(bxt_ddi_translations_hdmi);
> return bxt_ddi_translations_hdmi;
> }
>
> static const struct cnl_ddi_buf_trans *
> -cnl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
> +cnl_get_buf_trans_hdmi(struct intel_encoder *encoder, int *n_entries)
> {
> + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> u32 voltage = intel_de_read(dev_priv, CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
>
> if (voltage == VOLTAGE_INFO_0_85V) {
> @@ -935,8 +952,9 @@ cnl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
> }
>
> static const struct cnl_ddi_buf_trans *
> -cnl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
> +cnl_get_buf_trans_dp(struct intel_encoder *encoder, int *n_entries)
> {
> + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> u32 voltage = intel_de_read(dev_priv, CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
>
> if (voltage == VOLTAGE_INFO_0_85V) {
> @@ -956,8 +974,9 @@ cnl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
> }
>
> static const struct cnl_ddi_buf_trans *
> -cnl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
> +cnl_get_buf_trans_edp(struct intel_encoder *encoder, int *n_entries)
> {
> + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> u32 voltage = intel_de_read(dev_priv, CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
>
> if (dev_priv->vbt.edp.low_vswing) {
> @@ -976,14 +995,16 @@ cnl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
> }
> return NULL;
> } else {
> - return cnl_get_buf_trans_dp(dev_priv, n_entries);
> + return cnl_get_buf_trans_dp(encoder, n_entries);
> }
> }
>
> static const struct cnl_ddi_buf_trans *
> -icl_get_combo_buf_trans(struct drm_i915_private *dev_priv, int type, int rate,
> +icl_get_combo_buf_trans(struct intel_encoder *encoder, int type, int rate,
> int *n_entries)
> {
> + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> +
> if (type == INTEL_OUTPUT_HDMI) {
> *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi);
> return icl_combo_phy_ddi_translations_hdmi;
> @@ -1000,7 +1021,7 @@ icl_get_combo_buf_trans(struct drm_i915_private *dev_priv, int type, int rate,
> }
>
> static const struct icl_mg_phy_ddi_buf_trans *
> -icl_get_mg_buf_trans(struct drm_i915_private *dev_priv, int type, int rate,
> +icl_get_mg_buf_trans(struct intel_encoder *encoder, int type, int rate,
> int *n_entries)
> {
> if (type == INTEL_OUTPUT_HDMI) {
> @@ -1016,7 +1037,7 @@ icl_get_mg_buf_trans(struct drm_i915_private *dev_priv, int type, int rate,
> }
>
> static const struct cnl_ddi_buf_trans *
> -ehl_get_combo_buf_trans(struct drm_i915_private *dev_priv, int type, int rate,
> +ehl_get_combo_buf_trans(struct intel_encoder *encoder, int type, int rate,
> int *n_entries)
> {
> if (type != INTEL_OUTPUT_HDMI && type != INTEL_OUTPUT_EDP) {
> @@ -1024,15 +1045,15 @@ ehl_get_combo_buf_trans(struct drm_i915_private *dev_priv, int type, int rate,
> return ehl_combo_phy_ddi_translations_dp;
> }
>
> - return icl_get_combo_buf_trans(dev_priv, type, rate, n_entries);
> + return icl_get_combo_buf_trans(encoder, type, rate, n_entries);
> }
>
> static const struct cnl_ddi_buf_trans *
> -tgl_get_combo_buf_trans(struct drm_i915_private *dev_priv, int type, int rate,
> +tgl_get_combo_buf_trans(struct intel_encoder *encoder, int type, int rate,
> int *n_entries)
> {
> if (type == INTEL_OUTPUT_HDMI || type == INTEL_OUTPUT_EDP) {
> - return icl_get_combo_buf_trans(dev_priv, type, rate, n_entries);
> + return icl_get_combo_buf_trans(encoder, type, rate, n_entries);
> } else if (rate > 270000) {
> *n_entries = ARRAY_SIZE(tgl_combo_phy_ddi_translations_dp_hbr2);
> return tgl_combo_phy_ddi_translations_dp_hbr2;
> @@ -1043,7 +1064,7 @@ tgl_get_combo_buf_trans(struct drm_i915_private *dev_priv, int type, int rate,
> }
>
> static const struct tgl_dkl_phy_ddi_buf_trans *
> -tgl_get_dkl_buf_trans(struct drm_i915_private *dev_priv, int type, int rate,
> +tgl_get_dkl_buf_trans(struct intel_encoder *encoder, int type, int rate,
> int *n_entries)
> {
> if (type == INTEL_OUTPUT_HDMI) {
> @@ -1066,34 +1087,34 @@ static int intel_ddi_hdmi_level(struct intel_encoder *encoder)
>
> if (INTEL_GEN(dev_priv) >= 12) {
> if (intel_phy_is_combo(dev_priv, phy))
> - tgl_get_combo_buf_trans(dev_priv, INTEL_OUTPUT_HDMI,
> + tgl_get_combo_buf_trans(encoder, INTEL_OUTPUT_HDMI,
> 0, &n_entries);
> else
> - tgl_get_dkl_buf_trans(dev_priv, INTEL_OUTPUT_HDMI, 0,
> + tgl_get_dkl_buf_trans(encoder, INTEL_OUTPUT_HDMI, 0,
> &n_entries);
> default_entry = n_entries - 1;
> } else if (INTEL_GEN(dev_priv) == 11) {
> if (intel_phy_is_combo(dev_priv, phy))
> - icl_get_combo_buf_trans(dev_priv, INTEL_OUTPUT_HDMI,
> + icl_get_combo_buf_trans(encoder, INTEL_OUTPUT_HDMI,
> 0, &n_entries);
> else
> - icl_get_mg_buf_trans(dev_priv, INTEL_OUTPUT_HDMI, 0,
> + icl_get_mg_buf_trans(encoder, INTEL_OUTPUT_HDMI, 0,
> &n_entries);
> default_entry = n_entries - 1;
> } else if (IS_CANNONLAKE(dev_priv)) {
> - cnl_get_buf_trans_hdmi(dev_priv, &n_entries);
> + cnl_get_buf_trans_hdmi(encoder, &n_entries);
> default_entry = n_entries - 1;
> } else if (IS_GEN9_LP(dev_priv)) {
> - bxt_get_buf_trans_hdmi(dev_priv, &n_entries);
> + bxt_get_buf_trans_hdmi(encoder, &n_entries);
> default_entry = n_entries - 1;
> } else if (IS_GEN9_BC(dev_priv)) {
> - intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
> + intel_ddi_get_buf_trans_hdmi(encoder, &n_entries);
> default_entry = 8;
> } else if (IS_BROADWELL(dev_priv)) {
> - intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
> + intel_ddi_get_buf_trans_hdmi(encoder, &n_entries);
> default_entry = 7;
> } else if (IS_HASWELL(dev_priv)) {
> - intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
> + intel_ddi_get_buf_trans_hdmi(encoder, &n_entries);
> default_entry = 6;
> } else {
> drm_WARN(&dev_priv->drm, 1, "ddi translation table missing\n");
> @@ -1131,10 +1152,10 @@ static void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder,
> ddi_translations = intel_ddi_get_buf_trans_fdi(dev_priv,
> &n_entries);
> else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
> - ddi_translations = intel_ddi_get_buf_trans_edp(dev_priv, port,
> + ddi_translations = intel_ddi_get_buf_trans_edp(encoder, port,
> &n_entries);
> else
> - ddi_translations = intel_ddi_get_buf_trans_dp(dev_priv, port,
> + ddi_translations = intel_ddi_get_buf_trans_dp(encoder, port,
> &n_entries);
>
> /* If we're boosting the current, set bit 31 of trans1 */
> @@ -1163,7 +1184,7 @@ static void intel_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder,
> enum port port = encoder->port;
> const struct ddi_buf_trans *ddi_translations;
>
> - ddi_translations = intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
> + ddi_translations = intel_ddi_get_buf_trans_hdmi(encoder, &n_entries);
>
> if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations))
> return;
> @@ -2098,11 +2119,15 @@ static void skl_ddi_set_iboost(struct intel_encoder *encoder,
> int n_entries;
>
> if (type == INTEL_OUTPUT_HDMI)
> - ddi_translations = intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
> + ddi_translations = intel_ddi_get_buf_trans_hdmi(encoder, &n_entries);
> else if (type == INTEL_OUTPUT_EDP)
> - ddi_translations = intel_ddi_get_buf_trans_edp(dev_priv, port, &n_entries);
> + ddi_translations = intel_ddi_get_buf_trans_edp(encoder,
> + port,
> + &n_entries);
> else
> - ddi_translations = intel_ddi_get_buf_trans_dp(dev_priv, port, &n_entries);
> + ddi_translations = intel_ddi_get_buf_trans_dp(encoder,
> + port,
> + &n_entries);
>
> if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations))
> return;
> @@ -2133,11 +2158,11 @@ static void bxt_ddi_vswing_sequence(struct intel_encoder *encoder,
> int n_entries;
>
> if (type == INTEL_OUTPUT_HDMI)
> - ddi_translations = bxt_get_buf_trans_hdmi(dev_priv, &n_entries);
> + ddi_translations = bxt_get_buf_trans_hdmi(encoder, &n_entries);
> else if (type == INTEL_OUTPUT_EDP)
> - ddi_translations = bxt_get_buf_trans_edp(dev_priv, &n_entries);
> + ddi_translations = bxt_get_buf_trans_edp(encoder, &n_entries);
> else
> - ddi_translations = bxt_get_buf_trans_dp(dev_priv, &n_entries);
> + ddi_translations = bxt_get_buf_trans_dp(encoder, &n_entries);
>
> if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations))
> return;
> @@ -2161,36 +2186,36 @@ static u8 intel_ddi_dp_voltage_max(struct intel_dp *intel_dp)
>
> if (INTEL_GEN(dev_priv) >= 12) {
> if (intel_phy_is_combo(dev_priv, phy))
> - tgl_get_combo_buf_trans(dev_priv, encoder->type,
> + tgl_get_combo_buf_trans(encoder, encoder->type,
> intel_dp->link_rate, &n_entries);
> else
> - tgl_get_dkl_buf_trans(dev_priv, encoder->type,
> + tgl_get_dkl_buf_trans(encoder, encoder->type,
> intel_dp->link_rate, &n_entries);
> } else if (INTEL_GEN(dev_priv) == 11) {
> if (IS_ELKHARTLAKE(dev_priv))
> - ehl_get_combo_buf_trans(dev_priv, encoder->type,
> + ehl_get_combo_buf_trans(encoder, encoder->type,
> intel_dp->link_rate, &n_entries);
> else if (intel_phy_is_combo(dev_priv, phy))
> - icl_get_combo_buf_trans(dev_priv, encoder->type,
> + icl_get_combo_buf_trans(encoder, encoder->type,
> intel_dp->link_rate, &n_entries);
> else
> - icl_get_mg_buf_trans(dev_priv, encoder->type,
> + icl_get_mg_buf_trans(encoder, encoder->type,
> intel_dp->link_rate, &n_entries);
> } else if (IS_CANNONLAKE(dev_priv)) {
> if (encoder->type == INTEL_OUTPUT_EDP)
> - cnl_get_buf_trans_edp(dev_priv, &n_entries);
> + cnl_get_buf_trans_edp(encoder, &n_entries);
> else
> - cnl_get_buf_trans_dp(dev_priv, &n_entries);
> + cnl_get_buf_trans_dp(encoder, &n_entries);
> } else if (IS_GEN9_LP(dev_priv)) {
> if (encoder->type == INTEL_OUTPUT_EDP)
> - bxt_get_buf_trans_edp(dev_priv, &n_entries);
> + bxt_get_buf_trans_edp(encoder, &n_entries);
> else
> - bxt_get_buf_trans_dp(dev_priv, &n_entries);
> + bxt_get_buf_trans_dp(encoder, &n_entries);
> } else {
> if (encoder->type == INTEL_OUTPUT_EDP)
> - intel_ddi_get_buf_trans_edp(dev_priv, port, &n_entries);
> + intel_ddi_get_buf_trans_edp(encoder, port, &n_entries);
> else
> - intel_ddi_get_buf_trans_dp(dev_priv, port, &n_entries);
> + intel_ddi_get_buf_trans_dp(encoder, port, &n_entries);
> }
>
> if (drm_WARN_ON(&dev_priv->drm, n_entries < 1))
> @@ -2223,11 +2248,11 @@ static void cnl_ddi_vswing_program(struct intel_encoder *encoder,
> u32 val;
>
> if (type == INTEL_OUTPUT_HDMI)
> - ddi_translations = cnl_get_buf_trans_hdmi(dev_priv, &n_entries);
> + ddi_translations = cnl_get_buf_trans_hdmi(encoder, &n_entries);
> else if (type == INTEL_OUTPUT_EDP)
> - ddi_translations = cnl_get_buf_trans_edp(dev_priv, &n_entries);
> + ddi_translations = cnl_get_buf_trans_edp(encoder, &n_entries);
> else
> - ddi_translations = cnl_get_buf_trans_dp(dev_priv, &n_entries);
> + ddi_translations = cnl_get_buf_trans_dp(encoder, &n_entries);
>
> if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations))
> return;
> @@ -2344,22 +2369,23 @@ static void cnl_ddi_vswing_sequence(struct intel_encoder *encoder,
> intel_de_write(dev_priv, CNL_PORT_TX_DW5_GRP(port), val);
> }
>
> -static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv,
> - u32 level, enum phy phy, int type,
> - int rate)
> +static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder,
> + u32 level, enum phy phy, int type,
> + int rate)
> {
> + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> const struct cnl_ddi_buf_trans *ddi_translations = NULL;
> u32 n_entries, val;
> int ln;
>
> if (INTEL_GEN(dev_priv) >= 12)
> - ddi_translations = tgl_get_combo_buf_trans(dev_priv, type, rate,
> + ddi_translations = tgl_get_combo_buf_trans(encoder, type, rate,
> &n_entries);
> else if (IS_ELKHARTLAKE(dev_priv))
> - ddi_translations = ehl_get_combo_buf_trans(dev_priv, type, rate,
> + ddi_translations = ehl_get_combo_buf_trans(encoder, type, rate,
> &n_entries);
> else
> - ddi_translations = icl_get_combo_buf_trans(dev_priv, type, rate,
> + ddi_translations = icl_get_combo_buf_trans(encoder, type, rate,
> &n_entries);
> if (!ddi_translations)
> return;
> @@ -2471,7 +2497,7 @@ static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
> intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val);
>
> /* 5. Program swing and de-emphasis */
> - icl_ddi_combo_vswing_program(dev_priv, level, phy, type, rate);
> + icl_ddi_combo_vswing_program(encoder, level, phy, type, rate);
>
> /* 6. Set training enable to trigger update */
> val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN0(phy));
> @@ -2495,7 +2521,7 @@ static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
> rate = intel_dp->link_rate;
> }
>
> - ddi_translations = icl_get_mg_buf_trans(dev_priv, type, rate,
> + ddi_translations = icl_get_mg_buf_trans(encoder, type, rate,
> &n_entries);
> /* The table does not have values for level 3 and level 9. */
> if (level >= n_entries || level == 3 || level == 9) {
> @@ -2640,7 +2666,7 @@ tgl_dkl_phy_ddi_vswing_sequence(struct intel_encoder *encoder, int link_clock,
> rate = intel_dp->link_rate;
> }
>
> - ddi_translations = tgl_get_dkl_buf_trans(dev_priv, encoder->type, rate,
> + ddi_translations = tgl_get_dkl_buf_trans(encoder, encoder->type, rate,
> &n_entries);
>
> if (level >= n_entries)
> --
> 2.27.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2020-07-09 14:11 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-07-08 20:55 [Intel-gfx] [PATCH v4 1/5] drm/i915/display: Replace drm_i915_private in voltage swing functions by intel_encoder José Roberto de Souza
2020-07-08 20:55 ` [Intel-gfx] [PATCH v4 2/5] drm/i915/display: Remove port and phy from voltage swing functions José Roberto de Souza
2020-07-09 14:12 ` Ville Syrjälä
2020-07-08 20:55 ` [Intel-gfx] [PATCH v4 3/5] drm/i915/bios: Parse HOBL parameter José Roberto de Souza
2020-07-08 20:55 ` [Intel-gfx] [PATCH v4 4/5] drm/i915/display: Implement HOBL José Roberto de Souza
2020-07-09 14:24 ` Ville Syrjälä
2020-07-09 19:40 ` Souza, Jose
2020-07-10 11:56 ` Ville Syrjälä
2020-07-08 20:55 ` [Intel-gfx] [PATCH v4 5/5] DO_NOT_MERGE_IT: drm/i915/display: Enable HOBL by default José Roberto de Souza
2020-07-08 22:04 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [v4,1/5] drm/i915/display: Replace drm_i915_private in voltage swing functions by intel_encoder Patchwork
2020-07-08 22:23 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-07-09 2:53 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2020-07-09 14:10 ` Ville Syrjälä [this message]
2020-07-09 16:34 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [v4,1/5] drm/i915/display: Replace drm_i915_private in voltage swing functions by intel_encoder (rev2) Patchwork
2020-07-09 16:53 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-07-09 18:59 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2020-07-09 19:35 ` Souza, Jose
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