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Mon, 13 Jul 2020 14:36:07 -0700 (PDT) Received: from xps15 ([64.188.179.252]) by smtp.gmail.com with ESMTPSA id x19sm1372922ioh.38.2020.07.13.14.36.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Jul 2020 14:36:06 -0700 (PDT) Received: (nullmailer pid 769509 invoked by uid 1000); Mon, 13 Jul 2020 21:36:05 -0000 Date: Mon, 13 Jul 2020 15:36:05 -0600 From: Rob Herring To: Tomasz Nowicki Subject: Re: [PATCH v3 3/4] dt-bindings: arm-smmu: add compatible string for Marvell Armada-AP806 SMMU-500 Message-ID: <20200713213605.GA766184@bogus> References: <20200702201633.22693-1-tn@semihalf.com> <20200702201633.22693-4-tn@semihalf.com> <3172ec21-d773-7fcb-f1ee-f557f72f20c5@arm.com> <972f5cbd-705b-e18a-7477-5f6922804361@semihalf.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <972f5cbd-705b-e18a-7477-5f6922804361@semihalf.com> Cc: devicetree@vger.kernel.org, gregory.clement@bootlin.com, Robin Murphy , linux-kernel@vger.kernel.org, nadavh@marvell.com, iommu@lists.linux-foundation.org, catalin.marinas@arm.com, mw@semihalf.com, will@kernel.org, hannah@marvell.com, linux-arm-kernel@lists.infradead.org X-BeenThere: iommu@lists.linux-foundation.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Development issues for Linux IOMMU support List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Errors-To: iommu-bounces@lists.linux-foundation.org Sender: "iommu" On Fri, Jul 03, 2020 at 11:26:32AM +0200, Tomasz Nowicki wrote: > On 03.07.2020 11:05, Robin Murphy wrote: > > On 2020-07-02 21:16, Tomasz Nowicki wrote: > > > Add specific compatible string for Marvell usage due to errata of > > > accessing 64bits registers of ARM SMMU, in AP806. > > > = > > > AP806 SoC uses the generic ARM-MMU500, and there's no specific > > > implementation of Marvell, this compatible is used for errata only. > > > = > > > Signed-off-by: Hanna Hawa > > > Signed-off-by: Gregory CLEMENT > > > Signed-off-by: Tomasz Nowicki > > > --- > > > =A0 Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 5 +++++ > > > =A0 1 file changed, 5 insertions(+) > > > = > > > diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml > > > b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml > > > index d7ceb4c34423..7beca9c00b12 100644 > > > --- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml > > > +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml > > > @@ -38,6 +38,11 @@ properties: > > > =A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 - qcom,sc7180-smmu-500 > > > =A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 - qcom,sdm845-smmu-500 > > > =A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 - const: arm,mmu-500 > > > +=A0=A0=A0=A0=A0 - description: Marvell SoCs implementing "arm,mmu-50= 0" > > > +=A0=A0=A0=A0=A0=A0=A0 items: > > > +=A0=A0=A0=A0=A0=A0=A0=A0=A0 - enum: > > > +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 - marvell,ap806-smmu-500 > > = > > Isn't a single-valued enum just a constant? :P > = > That's how copy-paste engineering ends up :) It's fine like this if you expect more SoCs to be added. Either way, Reviewed-by: Rob Herring _______________________________________________ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-10.0 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4E9E5C433DF for ; Mon, 13 Jul 2020 21:37:40 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 1B9A72082F for ; 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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Fri, Jul 03, 2020 at 11:26:32AM +0200, Tomasz Nowicki wrote: > On 03.07.2020 11:05, Robin Murphy wrote: > > On 2020-07-02 21:16, Tomasz Nowicki wrote: > > > Add specific compatible string for Marvell usage due to errata of > > > accessing 64bits registers of ARM SMMU, in AP806. > > > = > > > AP806 SoC uses the generic ARM-MMU500, and there's no specific > > > implementation of Marvell, this compatible is used for errata only. > > > = > > > Signed-off-by: Hanna Hawa > > > Signed-off-by: Gregory CLEMENT > > > Signed-off-by: Tomasz Nowicki > > > --- > > > =A0 Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 5 +++++ > > > =A0 1 file changed, 5 insertions(+) > > > = > > > diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml > > > b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml > > > index d7ceb4c34423..7beca9c00b12 100644 > > > --- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml > > > +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml > > > @@ -38,6 +38,11 @@ properties: > > > =A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 - qcom,sc7180-smmu-500 > > > =A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 - qcom,sdm845-smmu-500 > > > =A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 - const: arm,mmu-500 > > > +=A0=A0=A0=A0=A0 - description: Marvell SoCs implementing "arm,mmu-50= 0" > > > +=A0=A0=A0=A0=A0=A0=A0 items: > > > +=A0=A0=A0=A0=A0=A0=A0=A0=A0 - enum: > > > +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 - marvell,ap806-smmu-500 > > = > > Isn't a single-valued enum just a constant? :P > = > That's how copy-paste engineering ends up :) It's fine like this if you expect more SoCs to be added. Either way, Reviewed-by: Rob Herring _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-10.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 62E21C433E5 for ; Mon, 13 Jul 2020 21:36:11 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 43B3420DD4 for ; Mon, 13 Jul 2020 21:36:11 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; 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charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <972f5cbd-705b-e18a-7477-5f6922804361@semihalf.com> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Fri, Jul 03, 2020 at 11:26:32AM +0200, Tomasz Nowicki wrote: > On 03.07.2020 11:05, Robin Murphy wrote: > > On 2020-07-02 21:16, Tomasz Nowicki wrote: > > > Add specific compatible string for Marvell usage due to errata of > > > accessing 64bits registers of ARM SMMU, in AP806. > > > > > > AP806 SoC uses the generic ARM-MMU500, and there's no specific > > > implementation of Marvell, this compatible is used for errata only. > > > > > > Signed-off-by: Hanna Hawa > > > Signed-off-by: Gregory CLEMENT > > > Signed-off-by: Tomasz Nowicki > > > --- > > >   Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 5 +++++ > > >   1 file changed, 5 insertions(+) > > > > > > diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml > > > b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml > > > index d7ceb4c34423..7beca9c00b12 100644 > > > --- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml > > > +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml > > > @@ -38,6 +38,11 @@ properties: > > >                 - qcom,sc7180-smmu-500 > > >                 - qcom,sdm845-smmu-500 > > >             - const: arm,mmu-500 > > > +      - description: Marvell SoCs implementing "arm,mmu-500" > > > +        items: > > > +          - enum: > > > +              - marvell,ap806-smmu-500 > > > > Isn't a single-valued enum just a constant? :P > > That's how copy-paste engineering ends up :) It's fine like this if you expect more SoCs to be added. Either way, Reviewed-by: Rob Herring