From mboxrd@z Thu Jan 1 00:00:00 1970 From: Will Deacon Subject: Re: [PATCH] asm-generic/mmiowb: Get cpu in mmiowb_set_pending Date: Wed, 15 Jul 2020 11:42:46 +0100 Message-ID: <20200715104246.GA3143299@google.com> References: Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Return-path: Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44700 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729010AbgGOKmx (ORCPT ); Wed, 15 Jul 2020 06:42:53 -0400 Received: from mail-wr1-x443.google.com (mail-wr1-x443.google.com [IPv6:2a00:1450:4864:20::443]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 56018C061755 for ; Wed, 15 Jul 2020 03:42:53 -0700 (PDT) Received: by mail-wr1-x443.google.com with SMTP id z2so2089258wrp.2 for ; Wed, 15 Jul 2020 03:42:53 -0700 (PDT) Content-Disposition: inline In-Reply-To: Sender: linux-arch-owner@vger.kernel.org List-ID: To: Palmer Dabbelt Cc: kernel@esmil.dk, guoren@kernel.org, linux-riscv@lists.infradead.org, Arnd Bergmann , Paul Walmsley , linux-arch@vger.kernel.org On Tue, Jul 14, 2020 at 11:45:11PM -0700, Palmer Dabbelt wrote: > > > > > > > > [] regmap_mmio_write32le+0x18/0x46 > > > > > > > > [] check_preemption_disabled+0xa4/0xaa > > > > > > > > [] regmap_mmio_write32le+0x18/0x46 > > > > > > > > [] regmap_mmio_write+0x26/0x44 > > > > > > > > [] regmap_write+0x28/0x48 > > > > > > > > [] sifive_gpio_probe+0xc0/0x1da > > > > > > > > [] rdinit_setup+0x22/0x26 > > > > > > > > [] platform_drv_probe+0x24/0x52 > > > > > > > > [] really_probe+0x92/0x21a > > > > > > > > [] device_driver_attach+0x42/0x4a > > > > > > > > [] device_driver_attach+0x46/0x4a > > > > > > > > [] __driver_attach+0x40/0xac > > > > > > > > [] device_driver_attach+0x46/0x4a > > > > > > > > [] bus_for_each_dev+0x3c/0x64 > > > > > > > > [] bus_add_driver+0x11e/0x184 > > > > > > > > [] driver_register+0x32/0xc6 > > > > > > > > [] gpiolib_sysfs_init+0xaa/0xae > > > > > > > > [] do_one_initcall+0x50/0xfc > > > > > > > > Hmm.. the problem is that preemption is *not* disabled when > > > > smp_processor_id is called, right? > > > > > > Yes! > > > > > > smp_processor_id is defined as: > > > > > > * This is the normal accessor to the CPU id and should be used > > > * whenever possible. > > > * > > > * The CPU id is stable when: > > > * > > > * - IRQs are disabled; > > > * - preemption is disabled; > > > * - the task is CPU affine. > > > * > > > * When CONFIG_DEBUG_PREEMPT; we verify these assumption and WARN > > > * when smp_processor_id() is used when the CPU id is not stable. > > > > > > So regmap_write->regmap_mmio_write should be PREEMPT disabled in > > > sifive_gpio_probe(). > > > > Ah! Sorry, now I think I understand. So you're saying that the real > > problem is that the driver framework should have disabled preemption > > before calling any .probe functions, but for some reason that doesn't > > happen on RISC-V? > > I think it's actually an issue with the generic mmiowb stuff and that we should > just elide the check. I'm adding Will, for context. I'll send out a patch. Hmm. Although I _think_ something like the diff below ought to work, are you sure you want to be doing MMIO writes in preemptible context? Setting '.disable_locking = true' in 'sifive_gpio_regmap_config' implies to me that you should be handling the locking within the driver itself, and all the other regmap writes are protected by '&gc->bgpio_lock'. Given that riscv is one of the few architectures needing an implementation of mmiowb(), doing MMIO in a preemptible section seems especially dangerous as you have no way to ensure completion of the writes without adding an mmiowb() to the CPU migration path (i.e. context switch). Will --->8 diff --git a/include/asm-generic/mmiowb.h b/include/asm-generic/mmiowb.h index 9439ff037b2d..5698fca3bf56 100644 --- a/include/asm-generic/mmiowb.h +++ b/include/asm-generic/mmiowb.h @@ -27,7 +27,7 @@ #include DECLARE_PER_CPU(struct mmiowb_state, __mmiowb_state); -#define __mmiowb_state() this_cpu_ptr(&__mmiowb_state) +#define __mmiowb_state() raw_cpu_ptr(&__mmiowb_state) #else #define __mmiowb_state() arch_mmiowb_state() #endif /* arch_mmiowb_state */ @@ -35,7 +35,9 @@ DECLARE_PER_CPU(struct mmiowb_state, __mmiowb_state); static inline void mmiowb_set_pending(void) { struct mmiowb_state *ms = __mmiowb_state(); - ms->mmiowb_pending = ms->nesting_count; + + if (likely(ms->nesting_count)) + ms->mmiowb_pending = ms->nesting_count; } static inline void mmiowb_spin_lock(void) From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.0 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_ADSP_CUSTOM_MED,DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1252CC433E1 for ; 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Wed, 15 Jul 2020 03:42:51 -0700 (PDT) Received: from google.com ([2a00:79e0:d:110:f693:9fff:fef4:a833]) by smtp.gmail.com with ESMTPSA id n16sm2890572wrq.39.2020.07.15.03.42.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Jul 2020 03:42:51 -0700 (PDT) Date: Wed, 15 Jul 2020 11:42:46 +0100 From: Will Deacon To: Palmer Dabbelt Subject: Re: [PATCH] asm-generic/mmiowb: Get cpu in mmiowb_set_pending Message-ID: <20200715104246.GA3143299@google.com> References: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200715_064254_785322_EBAF0AFE X-CRM114-Status: GOOD ( 23.15 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-arch@vger.kernel.org, kernel@esmil.dk, Arnd Bergmann , guoren@kernel.org, Paul Walmsley , linux-riscv@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Tue, Jul 14, 2020 at 11:45:11PM -0700, Palmer Dabbelt wrote: > > > > > > > > [] regmap_mmio_write32le+0x18/0x46 > > > > > > > > [] check_preemption_disabled+0xa4/0xaa > > > > > > > > [] regmap_mmio_write32le+0x18/0x46 > > > > > > > > [] regmap_mmio_write+0x26/0x44 > > > > > > > > [] regmap_write+0x28/0x48 > > > > > > > > [] sifive_gpio_probe+0xc0/0x1da > > > > > > > > [] rdinit_setup+0x22/0x26 > > > > > > > > [] platform_drv_probe+0x24/0x52 > > > > > > > > [] really_probe+0x92/0x21a > > > > > > > > [] device_driver_attach+0x42/0x4a > > > > > > > > [] device_driver_attach+0x46/0x4a > > > > > > > > [] __driver_attach+0x40/0xac > > > > > > > > [] device_driver_attach+0x46/0x4a > > > > > > > > [] bus_for_each_dev+0x3c/0x64 > > > > > > > > [] bus_add_driver+0x11e/0x184 > > > > > > > > [] driver_register+0x32/0xc6 > > > > > > > > [] gpiolib_sysfs_init+0xaa/0xae > > > > > > > > [] do_one_initcall+0x50/0xfc > > > > > > > > Hmm.. the problem is that preemption is *not* disabled when > > > > smp_processor_id is called, right? > > > > > > Yes! > > > > > > smp_processor_id is defined as: > > > > > > * This is the normal accessor to the CPU id and should be used > > > * whenever possible. > > > * > > > * The CPU id is stable when: > > > * > > > * - IRQs are disabled; > > > * - preemption is disabled; > > > * - the task is CPU affine. > > > * > > > * When CONFIG_DEBUG_PREEMPT; we verify these assumption and WARN > > > * when smp_processor_id() is used when the CPU id is not stable. > > > > > > So regmap_write->regmap_mmio_write should be PREEMPT disabled in > > > sifive_gpio_probe(). > > > > Ah! Sorry, now I think I understand. So you're saying that the real > > problem is that the driver framework should have disabled preemption > > before calling any .probe functions, but for some reason that doesn't > > happen on RISC-V? > > I think it's actually an issue with the generic mmiowb stuff and that we should > just elide the check. I'm adding Will, for context. I'll send out a patch. Hmm. Although I _think_ something like the diff below ought to work, are you sure you want to be doing MMIO writes in preemptible context? Setting '.disable_locking = true' in 'sifive_gpio_regmap_config' implies to me that you should be handling the locking within the driver itself, and all the other regmap writes are protected by '&gc->bgpio_lock'. Given that riscv is one of the few architectures needing an implementation of mmiowb(), doing MMIO in a preemptible section seems especially dangerous as you have no way to ensure completion of the writes without adding an mmiowb() to the CPU migration path (i.e. context switch). Will --->8 diff --git a/include/asm-generic/mmiowb.h b/include/asm-generic/mmiowb.h index 9439ff037b2d..5698fca3bf56 100644 --- a/include/asm-generic/mmiowb.h +++ b/include/asm-generic/mmiowb.h @@ -27,7 +27,7 @@ #include DECLARE_PER_CPU(struct mmiowb_state, __mmiowb_state); -#define __mmiowb_state() this_cpu_ptr(&__mmiowb_state) +#define __mmiowb_state() raw_cpu_ptr(&__mmiowb_state) #else #define __mmiowb_state() arch_mmiowb_state() #endif /* arch_mmiowb_state */ @@ -35,7 +35,9 @@ DECLARE_PER_CPU(struct mmiowb_state, __mmiowb_state); static inline void mmiowb_set_pending(void) { struct mmiowb_state *ms = __mmiowb_state(); - ms->mmiowb_pending = ms->nesting_count; + + if (likely(ms->nesting_count)) + ms->mmiowb_pending = ms->nesting_count; } static inline void mmiowb_spin_lock(void) _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv