From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-11.5 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,USER_AGENT_SANE_1 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0D7F9C433E2 for ; Wed, 15 Jul 2020 16:53:33 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id CC03B2072E for ; Wed, 15 Jul 2020 16:53:32 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="GeZ0yfkV" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org CC03B2072E Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References:Message-ID: Subject:To:From:Date:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=pntkD244Cy9STs/R8K/28NpQGx7KZD4lDwt1fvMN1yU=; b=GeZ0yfkVMAuUnxFV5RjYCDMc3 BKB4ICglOrzlkykIhBokd3ZgrQcpfKU2mStltZ7q8DBQ38VDbaA6OWWvUt+xe5NdhRYd203Yuyoiy /K5WEmrX/Jug9F+GqWE98HB/RUBCUZg7U358KLvR4CaNLIVaaWO6pc6SaKzV5q772LMHZEFp8m4BJ CZMUBoga4ocN6afB7AnUWEqASLFcZj6jytaPe8Hequ8kjgjcV1Tbq0+5m6gvp22dvbqODp1iYxJ0o cQpyRtK4ZeIv6upOTpd4pdm90mKs2cJkaeDW33oG0FHLSNcOngPjbzOhQnpC9eitgFaqYKSULwjW+ afunVg9iA==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1jvkdj-000675-11; Wed, 15 Jul 2020 16:52:15 +0000 Received: from foss.arm.com ([217.140.110.172]) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1jvkdf-000660-Jm for linux-arm-kernel@lists.infradead.org; Wed, 15 Jul 2020 16:52:12 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id E091831B; Wed, 15 Jul 2020 09:52:08 -0700 (PDT) Received: from arm.com (usa-sjc-imap-foss1.foss.arm.com [10.121.207.14]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 6F3853F718; Wed, 15 Jul 2020 09:52:07 -0700 (PDT) Date: Wed, 15 Jul 2020 17:52:05 +0100 From: Dave Martin To: Mark Brown Subject: Re: [PATCH v3 5/8] arm64/sve: Implement a helper to flush SVE registers Message-ID: <20200715165205.GD30452@arm.com> References: <20200629133556.39825-1-broonie@kernel.org> <20200629133556.39825-6-broonie@kernel.org> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20200629133556.39825-6-broonie@kernel.org> User-Agent: Mutt/1.5.23 (2014-03-12) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200715_125211_743541_4FB07F4C X-CRM114-Status: GOOD ( 19.35 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Julien Grall , Catalin Marinas , zhang.lei@jp.fujitsu.com, Julien Grall , Will Deacon , linux-arm-kernel@lists.infradead.org, Daniel Kiss Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Mon, Jun 29, 2020 at 02:35:53PM +0100, Mark Brown wrote: > From: Julien Grall > > Introduce a new helper that will zero all SVE registers but the first > 128-bits of each vector. This will be used by subsequent patches to > avoid costly store/maipulate/reload sequences in places like do_sve_acc(). > > Signed-off-by: Julien Grall > Reviewed-by: Dave Martin > Signed-off-by: Mark Brown > --- > arch/arm64/include/asm/fpsimd.h | 1 + > arch/arm64/include/asm/fpsimdmacros.h | 19 +++++++++++++++++++ > arch/arm64/kernel/entry-fpsimd.S | 8 ++++++++ > 3 files changed, 28 insertions(+) > > diff --git a/arch/arm64/include/asm/fpsimd.h b/arch/arm64/include/asm/fpsimd.h > index 59f10dd13f12..958f642e930d 100644 > --- a/arch/arm64/include/asm/fpsimd.h > +++ b/arch/arm64/include/asm/fpsimd.h > @@ -69,6 +69,7 @@ static inline void *sve_pffr(struct thread_struct *thread) > extern void sve_save_state(void *state, u32 *pfpsr); > extern void sve_load_state(void const *state, u32 const *pfpsr, > unsigned long vq_minus_1); > +extern void sve_flush_live(void); > extern unsigned int sve_get_vl(void); > > struct arm64_cpu_capabilities; > diff --git a/arch/arm64/include/asm/fpsimdmacros.h b/arch/arm64/include/asm/fpsimdmacros.h > index feef5b371fba..af43367534c7 100644 > --- a/arch/arm64/include/asm/fpsimdmacros.h > +++ b/arch/arm64/include/asm/fpsimdmacros.h > @@ -164,6 +164,13 @@ > | ((\np) << 5) > .endm > > +/* PFALSE P\np.B */ > +.macro _sve_pfalse np > + _sve_check_preg \np > + .inst 0x2518e400 \ > + | (\np) > +.endm > + > .macro __for from:req, to:req > .if (\from) == (\to) > _for__body %\from > @@ -198,6 +205,18 @@ > 921: > .endm > > +/* Preserve the first 128-bits of Znz and zero the rest. */ > +.macro _sve_flush_z nz > + _sve_check_zreg \nz > + mov v\nz\().16b, v\nz\().16b > +.endm > + > +.macro sve_flush > + _for n, 0, 31, _sve_flush_z \n > + _for n, 0, 15, _sve_pfalse \n > + _sve_wrffr 0 Side note, but as and when hardware is available for benchmarking, it could be worth investigating how sequences like this perform. Because WRFFR is self-synchronising, it is a potentially expensive operation; especially so if there could be in-flight SVE operations. This isn't directly relevant to this patch, but could be worth a look later on. [...] Cheers ---Dave _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel