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linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.rutland@arm.com, devicetree@vger.kernel.org, dineshk@xilinx.com, hyunk@xilinx.com, sandipk@xilinx.com, linux-kernel@vger.kernel.org, Hans Verkuil , robh+dt@kernel.org, michals@xilinx.com, joe@perches.com, mchehab@kernel.org, linux-arm-kernel@lists.infradead.org, linux-media@vger.kernel.org Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org SGkgVmlzaGFsLAoKVGhhbmsgeW91IGZvciB0aGUgcGF0Y2guCgpIYW5zLCB0aGVyZSBhcmUgYSBm ZXcgcXVlc3Rpb25zIGZvciB5b3UgYmVsb3cuCgpPbiBUaHUsIEp1biAyNSwgMjAyMCBhdCAxMTo0 MzowMUFNICswMjAwLCBIYW5zIFZlcmt1aWwgd3JvdGU6Cj4gT24gMTgvMDYvMjAyMCAwNzozMywg VmlzaGFsIFNhZ2FyIHdyb3RlOgo+ID4gVGhlIFhpbGlueCBVSEQtU0RJIFJ4IHN1YnN5c3RlbSBz b2Z0IElQIGlzIHVzZWQgdG8gY2FwdHVyZSBuYXRpdmUgU0RJCj4gPiBzdHJlYW1zIGZyb20gU0RJ IHNvdXJjZXMgbGlrZSBTREkgYnJvYWRjYXN0IGVxdWlwbWVudCBsaWtlIGNhbWVyYXMgYW5kCj4g PiBtaXhlcnMuIFRoaXMgYmxvY2sgb3V0cHV0cyBlaXRoZXIgbmF0aXZlIFNESSwgbmF0aXZlIHZp ZGVvIG9yCj4gPiBBWEk0LVN0cmVhbSBjb21wbGlhbnQgZGF0YSBzdHJlYW0gZm9yIGZ1cnRoZXIg cHJvY2Vzc2luZy4gUGxlYXNlIHJlZmVyCj4gPiB0byBQRzI5MCBmb3IgZGV0YWlscy4KPiA+IAo+ ID4gVGhlIGRyaXZlciBpcyB1c2VkIHRvIGNvbmZpZ3VyZSB0aGUgSVAgdG8gYWRkIGZyYW1lciwg c2VhcmNoIGZvcgo+ID4gc3BlY2lmaWMgbW9kZXMsIGdldCB0aGUgZGV0ZWN0ZWQgbW9kZSwgc3Ry ZWFtIHBhcmFtZXRlcnMsIGVycm9ycywgZXRjLgo+ID4gSXQgYWxzbyBnZW5lcmF0ZXMgZXZlbnRz IGZvciB2aWRlbyBsb2NrL3VubG9jaywgYnJpZGdlIG92ZXIvdW5kZXIgZmxvdy4KPiA+IAo+ID4g VGhlIGRyaXZlciBzdXBwb3J0cyAxMC8xMiBicGMgWVVWIDQyMiBtZWRpYSBidXMgZm9ybWF0IGN1 cnJlbnRseS4gSXQKPiA+IGFsc28gZGVjb2RlcyB0aGUgc3RyZWFtIHBhcmFtZXRlcnMgYmFzZWQg b24gdGhlIFNUMzUyIHBhY2tldCBlbWJlZGRlZCBpbiB0aGUKPiA+IHN0cmVhbS4gSW4gY2FzZSB0 aGUgU1QzNTIgcGFja2V0IGlzbid0IHByZXNlbnQgaW4gdGhlIHN0cmVhbSwgdGhlIGNvcmUncwo+ ID4gZGV0ZWN0ZWQgcHJvcGVydGllcyBhcmUgdXNlZCB0byBzZXQgc3RyZWFtIHByb3BlcnRpZXMu Cj4gPiAKPiA+IFRoZSBkcml2ZXIgY3VycmVudGx5IHN1cHBvcnRzIG9ubHkgdGhlIEFYSTQtU3Ry ZWFtIElQIGNvbmZpZ3VyYXRpb24uCj4gPiAKPiA+IFNpZ25lZC1vZmYtYnk6IFZpc2hhbCBTYWdh ciA8dmlzaGFsLnNhZ2FyQHhpbGlueC5jb20+Cj4gPiAtLS0KPiA+IHYzCj4gPiAtIGZpeGVkIEtD b25maWcgd2l0aCBiZXR0ZXIgZGVzY3JpcHRpb24KPiA+IC0gcmVtb3ZlZCB1bm5lY2Vzc2FyeSBo ZWFkZXIgZmlsZXMKPiA+IC0gY29udmVydGVkIHVwcGVyY2FzZSB0byBsb3dlcmNhc2UgZm9yIGFs bCBoZXggdmFsdWVzCj4gPiAtIG1lcmdlZCBjb3JlIHN0cnVjdCB0byBzdGF0ZSBzdHJ1Y3QKPiA+ IC0gcmVtb3ZlZCBtb3N0IG9uZSBsaW5lIGZ1bmN0aW9ucyBhbmQgcmVwbGFjZWQgd2l0aCBkaXJl Y3QgcmVnCj4gPiAgIHJlYWQvd3JpdGUgb3IgbWFjcm9zCj4gPiAtIGR0IHByb3BlcnR5IGJwcCB0 byBicGMuIGRlZmF1bHQgMTAuIG5vdCBtYW5kYXRvcnkuCj4gPiAtIGZpeGVkIHN1YnNjcmliZSBl dmVudHMsIGxvZ19zdGF0dXMsIHNfc3RyZWFtCj4gPiAtIG1lcmdlZCBvdmVyZmxvdy91bmRlcmZs b3cgdG8gb25lIGV2ZW50Cj4gPiAtIG1vdmVkIGFsbCBjb250cm9scyB0byB4aWxpbngtc2Rpcnhz cy5oCj4gPiAtIG1heCBldmVudHMgZnJvbSAxMjggdG8gOAo+ID4gLSB1c2VkIEZJRUxEX0dFVCgp IGluc3RlYWQgb2YgY3VzdG9tIG1hY3JvCj4gPiAtIHVwZGF0ZWQgdGhlIGNvbnRyb2xzIGRvY3Vt ZW50YXRpb24KPiA+IC0gYWRkZWQgc3BpbmxvY2sKPiA+IC0gcmVtb3ZlZCAzR0IgY29udHJvbCBh bmQgYWRkZWQgbW9kZSB0byBkZXRlY3QgYml0bWFzawo+ID4gLSBmaXhlZCBmb3JtYXQgZm9yICh3 aWR0aCwgaGVpZ2h0LCBjb2xvcnNwYWNlLCB4ZmVyIGZ1bmMsIGV0YykKPiA+IC0gYWRkZWQgZHZf dGltaW5nc19jYXAsIHMvZ19kdl90aW1pbmdzCj4gPiAtIGZpeGVkIHNldC9nZXRfZm9ybWF0Cj4g PiAtIGZpeCB2NGwgY29udHJvbCByZWdpc3RyYXRpb25zCj4gPiAtIGZpeCBvcmRlciBvZiByZWdp c3RyYXRpb24gLyBkZXJlZ2lzdHJhdGlvbiBpbiBwcm9iZSgpIHJlbW92ZSgpCj4gPiAtIGZpeGVk IG90aGVyIGNvbW1lbnRzIGZyb20gSHl1biwgTGF1cmVudCBhbmQgSGFucwo+ID4gLSB0aGluZ3Mg eWV0IHRvIGNsb3NlCj4gPiAgIC0gYWRkaW5nIHNvdXJjZSBwb3J0IGZvciBjb25uZWN0b3IgKExh dXJlbnQncyBzdWdnZXN0aW9uKQo+ID4gICAtIGFkZGluZyBuZXcgRklFTEQgdHlwZSBmb3IgVHJh bnNwb3J0IFN0cmVhbSBWNEwyX0ZJRUxEX0FMVEVSTkFURV9QUk9HIChIYW4ncyBzdWdnZXN0aW9u KQo+ID4gICAtIFVwZGF0ZSAvIHJlbW92ZSBFREggb3IgQ1JDIHJlbGF0ZWQgY29udHJvbHMKPiA+ IAo+ID4gdjIKPiA+IC0gQWRkZWQgRFYgdGltaW5nIHN1cHBvcnQgYmFzZWQgb24gSGFucyBWZXJr dWlsxZsgZmVlZGJhY2sKPiA+IC0gTW9yZSBkb2N1bWVudGF0aW9uIHRvIGN1c3RvbSB2NGwgY29u dHJvbHMgYW5kIGV2ZW50cwo+ID4gLSBGaXhlZCBIeXVuxZsgY29tbWVudHMKPiA+IC0gQWRkZWQg bWFjcm8gZm9yIG1hc2tpbmcgYW5kIHNoaWZ0aW5nIGFzIHBlciBKb2UgUGVyY2hlcyBjb21tZW50 cwo+ID4gLSBVcGRhdGVkIHRvIGxhdGVzdCBhcyBwZXIgWGlsaW54IGdpdGh1YiByZXBvIGRyaXZl ciBsaWtlCj4gPiAgIGFkZGluZyBuZXcgRFYgdGltaW5ncyBub3QgaW4gbWFpbmxpbmUgeWV0IHVw dGlsbCAwMy8yMS8yMAo+ID4gCj4gPiAgZHJpdmVycy9tZWRpYS9wbGF0Zm9ybS94aWxpbngvS2Nv bmZpZyAgICAgICAgIHwgICAxMSArCj4gPiAgZHJpdmVycy9tZWRpYS9wbGF0Zm9ybS94aWxpbngv TWFrZWZpbGUgICAgICAgIHwgICAgMSArCj4gPiAgLi4uL21lZGlhL3BsYXRmb3JtL3hpbGlueC94 aWxpbngtc2Rpcnhzcy5jICAgIHwgMjEyMSArKysrKysrKysrKysrKysrKwo+ID4gIGluY2x1ZGUv dWFwaS9saW51eC92NGwyLWNvbnRyb2xzLmggICAgICAgICAgICB8ICAgIDYgKwo+ID4gIGluY2x1 ZGUvdWFwaS9saW51eC94aWxpbngtc2Rpcnhzcy5oICAgICAgICAgICB8ICAyODMgKysrCj4gPiAg NSBmaWxlcyBjaGFuZ2VkLCAyNDIyIGluc2VydGlvbnMoKykKPiA+ICBjcmVhdGUgbW9kZSAxMDA2 NDQgZHJpdmVycy9tZWRpYS9wbGF0Zm9ybS94aWxpbngveGlsaW54LXNkaXJ4c3MuYwo+ID4gIGNy ZWF0ZSBtb2RlIDEwMDY0NCBpbmNsdWRlL3VhcGkvbGludXgveGlsaW54LXNkaXJ4c3MuaAo+ID4g Cj4gPiBkaWZmIC0tZ2l0IGEvZHJpdmVycy9tZWRpYS9wbGF0Zm9ybS94aWxpbngvS2NvbmZpZyBi L2RyaXZlcnMvbWVkaWEvcGxhdGZvcm0veGlsaW54L0tjb25maWcKPiA+IGluZGV4IDAxYzk2ZmI2 NjQxNC4uNTc4Y2RjYzEwMzZlIDEwMDY0NAo+ID4gLS0tIGEvZHJpdmVycy9tZWRpYS9wbGF0Zm9y bS94aWxpbngvS2NvbmZpZwo+ID4gKysrIGIvZHJpdmVycy9tZWRpYS9wbGF0Zm9ybS94aWxpbngv S2NvbmZpZwo+ID4gQEAgLTEyLDYgKzEyLDE3IEBAIGNvbmZpZyBWSURFT19YSUxJTlgKPiA+ICAK PiA+ICBpZiBWSURFT19YSUxJTlgKPiA+ICAKPiA+ICtjb25maWcgVklERU9fWElMSU5YX1NESVJY U1MKPiA+ICsJdHJpc3RhdGUgIlhpbGlueCBVSEQgU0RJIFJ4IFN1YnN5c3RlbSIKPiA+ICsJaGVs cAo+ID4gKwkgIERyaXZlciBmb3IgWGlsaW54IFVIRC1TREkgUnggU3Vic3lzdGVtLiBUaGlzIGlz IGEgVjRMIHN1Yi1kZXZpY2UKPiA+ICsJICBiYXNlZCBkcml2ZXIgdGhhdCB0YWtlcyBpbnB1dCBm cm9tIGEgU0RJIHNvdXJjZSBsaWtlIFNESSBjYW1lcmEgYW5kCj4gPiArCSAgY29udmVydHMgaXQg aW50byBhbiBBWEk0LVN0cmVhbS4gVGhlIHN1YnN5c3RlbSBjb21wcmlzZXMgYSBTTVBURQo+ID4g KwkgIFVIRC1TREkgUnggY29yZSwgYSBTREkgUnggdG8gTmF0aXZlIFZpZGVvIGJyaWRnZSBhbmQg YSBWaWRlbyBJbiB0bwo+ID4gKwkgIEFYSTQtU3RyZWFtIGJyaWRnZS4gVGhlIGRyaXZlciBpcyB1 c2VkIHRvIHNldCBkaWZmZXJlbnQgc3RyZWFtCj4gPiArCSAgZGV0ZWN0aW9uIG1vZGVzIGFuZCBp ZGVudGlmeSBzdHJlYW0gcHJvcGVydGllcyB0byBwcm9wZXJseSBjb25maWd1cmUKPiA+ICsJICBk b3duc3RyZWFtLgo+ID4gKwo+ID4gIGNvbmZpZyBWSURFT19YSUxJTlhfVFBHCj4gPiAgCXRyaXN0 YXRlICJYaWxpbnggVmlkZW8gVGVzdCBQYXR0ZXJuIEdlbmVyYXRvciIKPiA+ICAJZGVwZW5kcyBv biBWSURFT19YSUxJTlgKPiA+IGRpZmYgLS1naXQgYS9kcml2ZXJzL21lZGlhL3BsYXRmb3JtL3hp bGlueC9NYWtlZmlsZSBiL2RyaXZlcnMvbWVkaWEvcGxhdGZvcm0veGlsaW54L01ha2VmaWxlCj4g PiBpbmRleCA0Y2RjMGIxZWM3YTUuLjNiZWFmMjRkODMyYyAxMDA2NDQKPiA+IC0tLSBhL2RyaXZl cnMvbWVkaWEvcGxhdGZvcm0veGlsaW54L01ha2VmaWxlCj4gPiArKysgYi9kcml2ZXJzL21lZGlh L3BsYXRmb3JtL3hpbGlueC9NYWtlZmlsZQo+ID4gQEAgLTMsNSArMyw2IEBACj4gPiAgeGlsaW54 LXZpZGVvLW9ianMgKz0geGlsaW54LWRtYS5vIHhpbGlueC12aXAubyB4aWxpbngtdmlwcC5vCj4g PiAgCj4gPiAgb2JqLSQoQ09ORklHX1ZJREVPX1hJTElOWCkgKz0geGlsaW54LXZpZGVvLm8KPiA+ ICtvYmotJChDT05GSUdfVklERU9fWElMSU5YX1NESVJYU1MpICs9IHhpbGlueC1zZGlyeHNzLm8K PiA+ICBvYmotJChDT05GSUdfVklERU9fWElMSU5YX1RQRykgKz0geGlsaW54LXRwZy5vCj4gPiAg b2JqLSQoQ09ORklHX1ZJREVPX1hJTElOWF9WVEMpICs9IHhpbGlueC12dGMubwo+ID4gZGlmZiAt LWdpdCBhL2RyaXZlcnMvbWVkaWEvcGxhdGZvcm0veGlsaW54L3hpbGlueC1zZGlyeHNzLmMgYi9k cml2ZXJzL21lZGlhL3BsYXRmb3JtL3hpbGlueC94aWxpbngtc2Rpcnhzcy5jCj4gPiBuZXcgZmls ZSBtb2RlIDEwMDY0NAo+ID4gaW5kZXggMDAwMDAwMDAwMDAwLi5lMzlhYWI3YzY1NmEKPiA+IC0t LSAvZGV2L251bGwKPiA+ICsrKyBiL2RyaXZlcnMvbWVkaWEvcGxhdGZvcm0veGlsaW54L3hpbGlu eC1zZGlyeHNzLmMKPiA+IEBAIC0wLDAgKzEsMjEyMSBAQAo+ID4gKy8vIFNQRFgtTGljZW5zZS1J ZGVudGlmaWVyOiBHUEwtMi4wCj4gPiArLyoKPiA+ICsgKiBEcml2ZXIgZm9yIFhpbGlueCBTREkg UnggU3Vic3lzdGVtCj4gPiArICoKPiA+ICsgKiBDb3B5cmlnaHQgKEMpIDIwMTcgLSAyMDIwIFhp bGlueCwgSW5jLgo+ID4gKyAqCj4gPiArICogQ29udGFjdHM6IFZpc2hhbCBTYWdhciA8dmlzaGFs LnNhZ2FyQHhpbGlueC5jb20+Cj4gPiArICovCj4gPiArCj4gPiArI2luY2x1ZGUgPGR0LWJpbmRp bmdzL21lZGlhL3hpbGlueC1zZGkuaD4KPiA+ICsjaW5jbHVkZSA8bGludXgvYml0cy5oPgo+ID4g KyNpbmNsdWRlIDxsaW51eC9iaXRmaWVsZC5oPgo+ID4gKyNpbmNsdWRlIDxsaW51eC9jbGsuaD4K PiA+ICsjaW5jbHVkZSA8bGludXgvbW9kdWxlLmg+Cj4gPiArI2luY2x1ZGUgPGxpbnV4L3BsYXRm b3JtX2RldmljZS5oPgo+ID4gKyNpbmNsdWRlIDxsaW51eC94aWxpbngtc2Rpcnhzcy5oPgoKVGhh dCdzIGFuIGltcHJlc3NpdmUgdHJpbSBkb3duIG9mIGhlYWRlcnMsIGJ1dCBJIHRoaW5rIGl0IG1h eSBoYXZlIGdvbmUKYSBiaXQgdG9vIGZhciA6LVMgSSd2ZSBwb2ludGVkIG91dCB0byBoZWFkZXJz IHRoYXQgYXJlIG5vdCBuZWVkZWQgaW4gdjIsCmJ1dCB5b3UndmUgcmVtb3ZlZCBhbGwgaGVhZGVy cyB0aGF0IGFyZSBpbXBsaWNpdGx5IGluY2x1ZGVkIHRocm91Z2gKb3RoZXIgaGVhZGVycy4gVGhp cyBtYWtlcyB0aGUgZHJpdmVyIG1vcmUgZnJhZ2lsZSwgYXMgaWYgaGVhZGVycyBhcmUKcmVmYWN0 b3JlZCwgdGhlcmUncyBhIGxhcmdlIHJpc2sgb2YgY29tcGlsYXRpb24gYnJlYWthZ2VzLgoKPiA+ ICsjaW5jbHVkZSA8bWVkaWEvbWVkaWEtZW50aXR5Lmg+Cj4gPiArI2luY2x1ZGUgPG1lZGlhL3Y0 bDItY3RybHMuaD4KPiA+ICsjaW5jbHVkZSA8bWVkaWEvdjRsMi1kdi10aW1pbmdzLmg+Cj4gPiAr I2luY2x1ZGUgPG1lZGlhL3Y0bDItZXZlbnQuaD4KPiA+ICsjaW5jbHVkZSA8bWVkaWEvdjRsMi1z dWJkZXYuaD4KPiA+ICsKPiA+ICsvKgo+ID4gKyAqIFNESSBSeCByZWdpc3RlciBtYXAsIGJpdG1h c2sgYW5kIG9mZnNldHMKPiA+ICsgKi8KPiA+ICsjZGVmaW5lIFhTRElSWF9SU1RfQ1RSTF9SRUcJ CTB4MDAKPiA+ICsjZGVmaW5lIFhTRElSWF9NRExfQ1RSTF9SRUcJCTB4MDQKPiA+ICsjZGVmaW5l IFhTRElSWF9HTEJMX0lFUl9SRUcJCTB4MGMKPiA+ICsjZGVmaW5lIFhTRElSWF9JU1JfUkVHCQkJ MHgxMAo+ID4gKyNkZWZpbmUgWFNESVJYX0lFUl9SRUcJCQkweDE0Cj4gPiArI2RlZmluZSBYU0RJ UlhfU1QzNTJfVkFMSURfUkVHCQkweDE4Cj4gPiArI2RlZmluZSBYU0RJUlhfU1QzNTJfRFMxX1JF RwkJMHgxYwo+ID4gKyNkZWZpbmUgWFNESVJYX1NUMzUyX0RTM19SRUcJCTB4MjAKPiA+ICsjZGVm aW5lIFhTRElSWF9TVDM1Ml9EUzVfUkVHCQkweDI0Cj4gPiArI2RlZmluZSBYU0RJUlhfU1QzNTJf RFM3X1JFRwkJMHgyOAo+ID4gKyNkZWZpbmUgWFNESVJYX1NUMzUyX0RTOV9SRUcJCTB4MmMKPiA+ ICsjZGVmaW5lIFhTRElSWF9TVDM1Ml9EUzExX1JFRwkJMHgzMAo+ID4gKyNkZWZpbmUgWFNESVJY X1NUMzUyX0RTMTNfUkVHCQkweDM0Cj4gPiArI2RlZmluZSBYU0RJUlhfU1QzNTJfRFMxNV9SRUcJ CTB4MzgKPiA+ICsjZGVmaW5lIFhTRElSWF9WRVJTSU9OX1JFRwkJMHgzYwo+ID4gKyNkZWZpbmUg WFNESVJYX1NTX0NPTkZJR19SRUcJCTB4NDAKPiA+ICsjZGVmaW5lIFhTRElSWF9NT0RFX0RFVF9T VEFUX1JFRwkweDQ0Cj4gPiArI2RlZmluZSBYU0RJUlhfVFNfREVUX1NUQVRfUkVHCQkweDQ4Cj4g PiArI2RlZmluZSBYU0RJUlhfRURIX1NUQVRfUkVHCQkweDRjCj4gPiArI2RlZmluZSBYU0RJUlhf RURIX0VSUkNOVF9FTl9SRUcJMHg1MAo+ID4gKyNkZWZpbmUgWFNESVJYX0VESF9FUlJDTlRfUkVH CQkweDU0Cj4gPiArI2RlZmluZSBYU0RJUlhfQ1JDX0VSUkNOVF9SRUcJCTB4NTgKPiA+ICsjZGVm aW5lIFhTRElSWF9WSURfTE9DS19XSU5ET1dfUkVHCTB4NWMKPiA+ICsjZGVmaW5lIFhTRElSWF9T VDM1Ml9EUzJfUkVHCQkweDcwCj4gPiArI2RlZmluZSBYU0RJUlhfU1QzNTJfRFM0X1JFRwkJMHg3 NAo+ID4gKyNkZWZpbmUgWFNESVJYX1NUMzUyX0RTNl9SRUcJCTB4NzgKPiA+ICsjZGVmaW5lIFhT RElSWF9TVDM1Ml9EUzhfUkVHCQkweDdjCj4gPiArI2RlZmluZSBYU0RJUlhfU1QzNTJfRFMxMF9S RUcJCTB4ODAKPiA+ICsjZGVmaW5lIFhTRElSWF9TVDM1Ml9EUzEyX1JFRwkJMHg4NAo+ID4gKyNk ZWZpbmUgWFNESVJYX1NUMzUyX0RTMTRfUkVHCQkweDg4Cj4gPiArI2RlZmluZSBYU0RJUlhfU1Qz NTJfRFMxNl9SRUcJCTB4OGMKPiA+ICsKPiA+ICsjZGVmaW5lIFhTRElSWF9SU1RfQ1RSTF9TU19F Tl9NQVNLCQkJQklUKDApCj4gPiArI2RlZmluZSBYU0RJUlhfUlNUX0NUUkxfU1JTVF9NQVNLCQkJ QklUKDEpCj4gPiArI2RlZmluZSBYU0RJUlhfUlNUX0NUUkxfUlNUX0NSQ19FUlJDTlRfTUFTSwkJ QklUKDIpCj4gPiArI2RlZmluZSBYU0RJUlhfUlNUX0NUUkxfUlNUX0VESF9FUlJDTlRfTUFTSwkJ QklUKDMpCj4gPiArI2RlZmluZSBYU0RJUlhfUlNUX0NUUkxfU0RJUlhfQlJJREdFX0VOQl9NQVNL CQlCSVQoOCkKPiA+ICsjZGVmaW5lIFhTRElSWF9SU1RfQ1RSTF9WSURJTl9BWEk0U19NT0RfRU5C X01BU0sJQklUKDkpCj4gPiArI2RlZmluZSBYU0RJUlhfUlNUX0NUUkxfQlJJREdFX0NIX0ZNVF9P RkZTRVQJCTEwCj4gPiArI2RlZmluZSBYU0RJUlhfUlNUX0NUUkxfQlJJREdFX0NIX0ZNVF9NQVNL CQlHRU5NQVNLKDEyLCAxMCkKPiA+ICsjZGVmaW5lIFhTRElSWF9SU1RfQ1RSTF9CUklER0VfQ0hf Rk1UX1lVVjQ0NAkJMQo+ID4gKwo+ID4gKyNkZWZpbmUgWFNESVJYX01ETF9DVFJMX0ZSTV9FTl9N QVNLCQlCSVQoNCkKPiA+ICsjZGVmaW5lIFhTRElSWF9NRExfQ1RSTF9NT0RFX0RFVF9FTl9NQVNL CUJJVCg1KQo+ID4gKyNkZWZpbmUgWFNESVJYX01ETF9DVFJMX01PREVfSERfRU5fTUFTSwkJQklU KDgpCj4gPiArI2RlZmluZSBYU0RJUlhfTURMX0NUUkxfTU9ERV9TRF9FTl9NQVNLCQlCSVQoOSkK PiA+ICsjZGVmaW5lIFhTRElSWF9NRExfQ1RSTF9NT0RFXzNHX0VOX01BU0sJCUJJVCgxMCkKPiA+ ICsjZGVmaW5lIFhTRElSWF9NRExfQ1RSTF9NT0RFXzZHX0VOX01BU0sJCUJJVCgxMSkKPiA+ICsj ZGVmaW5lIFhTRElSWF9NRExfQ1RSTF9NT0RFXzEyR0lfRU5fTUFTSwlCSVQoMTIpCj4gPiArI2Rl ZmluZSBYU0RJUlhfTURMX0NUUkxfTU9ERV8xMkdGX0VOX01BU0sJQklUKDEzKQo+ID4gKyNkZWZp bmUgWFNESVJYX01ETF9DVFJMX01PREVfQVVUT19ERVRfTUFTSwlHRU5NQVNLKDEzLCA4KQo+ID4g Kwo+ID4gKyNkZWZpbmUgWFNESVJYX01ETF9DVFJMX0ZPUkNFRF9NT0RFX09GRlNFVAkxNgo+ID4g KyNkZWZpbmUgWFNESVJYX01ETF9DVFJMX0ZPUkNFRF9NT0RFX01BU0sJR0VOTUFTSygxOCwgMTYp Cj4gPiArCj4gPiArI2RlZmluZSBYU0RJUlhfR0xCTF9JTlRSX0VOX01BU0sJQklUKDApCj4gPiAr Cj4gPiArI2RlZmluZSBYU0RJUlhfSU5UUl9WSURMT0NLX01BU0sJQklUKDApCj4gPiArI2RlZmlu ZSBYU0RJUlhfSU5UUl9WSURVTkxPQ0tfTUFTSwlCSVQoMSkKPiA+ICsjZGVmaW5lIFhTRElSWF9J TlRSX09WRVJGTE9XX01BU0sJQklUKDkpCj4gPiArI2RlZmluZSBYU0RJUlhfSU5UUl9VTkRFUkZM T1dfTUFTSwlCSVQoMTApCj4gPiArCj4gPiArI2RlZmluZSBYU0RJUlhfSU5UUl9BTExfTUFTSwko WFNESVJYX0lOVFJfVklETE9DS19NQVNLIHxcCj4gPiArCQkJCVhTRElSWF9JTlRSX1ZJRFVOTE9D S19NQVNLIHxcCj4gPiArCQkJCVhTRElSWF9JTlRSX09WRVJGTE9XX01BU0sgfFwKPiA+ICsJCQkJ WFNESVJYX0lOVFJfVU5ERVJGTE9XX01BU0spCj4gPiArCj4gPiArI2RlZmluZSBYU0RJUlhfU1Qz NTJfVkFMSURfRFMxX01BU0sJQklUKDApCj4gPiArI2RlZmluZSBYU0RJUlhfU1QzNTJfVkFMSURf RFMzX01BU0sJQklUKDEpCj4gPiArI2RlZmluZSBYU0RJUlhfU1QzNTJfVkFMSURfRFM1X01BU0sJ QklUKDIpCj4gPiArI2RlZmluZSBYU0RJUlhfU1QzNTJfVkFMSURfRFM3X01BU0sJQklUKDMpCj4g PiArI2RlZmluZSBYU0RJUlhfU1QzNTJfVkFMSURfRFM5X01BU0sJQklUKDQpCj4gPiArI2RlZmlu ZSBYU0RJUlhfU1QzNTJfVkFMSURfRFMxMV9NQVNLCUJJVCg1KQo+ID4gKyNkZWZpbmUgWFNESVJY X1NUMzUyX1ZBTElEX0RTMTNfTUFTSwlCSVQoNikKPiA+ICsjZGVmaW5lIFhTRElSWF9TVDM1Ml9W QUxJRF9EUzE1X01BU0sJQklUKDcpCj4gPiArCj4gPiArI2RlZmluZSBYU0RJUlhfTU9ERV9ERVRf U1RBVF9SWF9NT0RFX01BU0sJR0VOTUFTSygyLCAwKQo+ID4gKyNkZWZpbmUgWFNESVJYX01PREVf REVUX1NUQVRfTU9ERV9MT0NLX01BU0sJQklUKDMpCj4gPiArI2RlZmluZSBYU0RJUlhfTU9ERV9E RVRfU1RBVF9BQ1RfU1RSRUFNX01BU0sJR0VOTUFTSyg2LCA0KQo+ID4gKyNkZWZpbmUgWFNESVJY X01PREVfREVUX1NUQVRfQUNUX1NUUkVBTV9PRkZTRVQJNAo+ID4gKyNkZWZpbmUgWFNESVJYX01P REVfREVUX1NUQVRfTFZMQl8zR19NQVNLCUJJVCg3KQo+ID4gKwo+ID4gKyNkZWZpbmUgWFNESVJY X1RTX0RFVF9TVEFUX0xPQ0tFRF9NQVNLCQlCSVQoMCkKPiA+ICsjZGVmaW5lIFhTRElSWF9UU19E RVRfU1RBVF9TQ0FOX01BU0sJCUJJVCgxKQo+ID4gKyNkZWZpbmUgWFNESVJYX1RTX0RFVF9TVEFU X0ZBTUlMWV9NQVNLCQlHRU5NQVNLKDcsIDQpCj4gPiArI2RlZmluZSBYU0RJUlhfVFNfREVUX1NU QVRfUkFURV9NQVNLCQlHRU5NQVNLKDExLCA4KQo+ID4gKwo+ID4gKyNkZWZpbmUgWFNESVJYX1RT X0RFVF9TVEFUX1JBVEVfTk9ORQkJMHgwCj4gPiArI2RlZmluZSBYU0RJUlhfVFNfREVUX1NUQVRf UkFURV8yM185OEhaCQkweDIKPiA+ICsjZGVmaW5lIFhTRElSWF9UU19ERVRfU1RBVF9SQVRFXzI0 SFoJCTB4Mwo+ID4gKyNkZWZpbmUgWFNESVJYX1RTX0RFVF9TVEFUX1JBVEVfNDdfOTVIWgkJMHg0 Cj4gPiArI2RlZmluZSBYU0RJUlhfVFNfREVUX1NUQVRfUkFURV8yNUhaCQkweDUKPiA+ICsjZGVm aW5lIFhTRElSWF9UU19ERVRfU1RBVF9SQVRFXzI5Xzk3SFoJCTB4Ngo+ID4gKyNkZWZpbmUgWFNE SVJYX1RTX0RFVF9TVEFUX1JBVEVfMzBIWgkJMHg3Cj4gPiArI2RlZmluZSBYU0RJUlhfVFNfREVU X1NUQVRfUkFURV80OEhaCQkweDgKPiA+ICsjZGVmaW5lIFhTRElSWF9UU19ERVRfU1RBVF9SQVRF XzUwSFoJCTB4OQo+ID4gKyNkZWZpbmUgWFNESVJYX1RTX0RFVF9TVEFUX1JBVEVfNTlfOTRIWgkJ MHhhCj4gPiArI2RlZmluZSBYU0RJUlhfVFNfREVUX1NUQVRfUkFURV82MEhaCQkweGIKPiA+ICsK PiA+ICsjZGVmaW5lIFhTRElSWF9FREhfU1RBVF9FREhfQVBfTUFTSwlCSVQoMCkKPiA+ICsjZGVm aW5lIFhTRElSWF9FREhfU1RBVF9FREhfRkZfTUFTSwlCSVQoMSkKPiA+ICsjZGVmaW5lIFhTRElS WF9FREhfU1RBVF9FREhfQU5DX01BU0sJQklUKDIpCj4gPiArI2RlZmluZSBYU0RJUlhfRURIX1NU QVRfQVBfRkxBR19NQVNLCUdFTk1BU0soOCwgNCkKPiA+ICsjZGVmaW5lIFhTRElSWF9FREhfU1RB VF9GRl9GTEFHX01BU0sJR0VOTUFTSygxMywgOSkKPiA+ICsjZGVmaW5lIFhTRElSWF9FREhfU1RB VF9BTkNfRkxBR19NQVNLCUdFTk1BU0soMTgsIDE0KQo+ID4gKyNkZWZpbmUgWFNESVJYX0VESF9T VEFUX1BLVF9GTEFHX01BU0sJR0VOTUFTSygyMiwgMTkpCj4gPiArCj4gPiArI2RlZmluZSBYU0RJ UlhfRURIX0VSUkNOVF9DT1VOVF9NQVNLCUdFTk1BU0soMTUsIDApCj4gPiArCj4gPiArI2RlZmlu ZSBYU0RJUlhfQ1JDX0VSUkNOVF9DT1VOVF9NQVNLCUdFTk1BU0soMzEsIDE2KQo+ID4gKyNkZWZp bmUgWFNESVJYX0NSQ19FUlJDTlRfRFNfQ1JDX01BU0sJR0VOTUFTSygxNSwgMCkKPiA+ICsKPiA+ ICsjZGVmaW5lIFhTRElSWF9WRVJTSU9OX1JFVl9NQVNLCQlHRU5NQVNLKDcsIDApCj4gPiArI2Rl ZmluZSBYU0RJUlhfVkVSU0lPTl9QQVRDSElEX01BU0sJR0VOTUFTSygxMSwgOCkKPiA+ICsjZGVm aW5lIFhTRElSWF9WRVJTSU9OX1ZFUl9SRVZfTUFTSwlHRU5NQVNLKDE1LCAxMikKPiA+ICsjZGVm aW5lIFhTRElSWF9WRVJTSU9OX1ZFUl9NSU5fTUFTSwlHRU5NQVNLKDIzLCAxNikKPiA+ICsjZGVm aW5lIFhTRElSWF9WRVJTSU9OX1ZFUl9NQUpfTUFTSwlHRU5NQVNLKDMxLCAyNCkKPiA+ICsKPiA+ ICsjZGVmaW5lIFhTRElSWF9TU19DT05GSUdfRURIX0lOQ0xVREVEX01BU0sJCUJJVCgxKQo+ID4g Kwo+ID4gKyNkZWZpbmUgWFNESVJYX1NUQVRfU0JfUlhfVERBVEFfQ0hBTkdFX0RPTkVfTUFTSwlC SVQoMCkKPiA+ICsjZGVmaW5lIFhTRElSWF9TVEFUX1NCX1JYX1REQVRBX0NIQU5HRV9GQUlMX01B U0sJQklUKDEpCj4gPiArI2RlZmluZSBYU0RJUlhfU1RBVF9TQl9SWF9UREFUQV9HVF9SRVNFVERP TkVfTUFTSwlCSVQoMikKPiA+ICsjZGVmaW5lIFhTRElSWF9TVEFUX1NCX1JYX1REQVRBX0dUX0JJ VFJBVEVfTUFTSwkJQklUKDMpCj4gPiArCj4gPiArI2RlZmluZSBYU0RJUlhfREVGQVVMVF9XSURU SAkxOTIwCj4gPiArI2RlZmluZSBYU0RJUlhfREVGQVVMVF9IRUlHSFQJMTA4MAo+ID4gKwo+ID4g KyNkZWZpbmUgWFNESVJYX01BWF9TVFJfTEVOR1RICTE2Cj4gPiArCj4gPiArI2RlZmluZSBYU0RJ UlhfREVGQVVMVF9WSURFT19MT0NLX1dJTkRPVwkweDMwMDAKPiA+ICsKPiA+ICsjZGVmaW5lIFhT RElSWF9NT0RFX0hEX01BU0sJMHgwCj4gPiArI2RlZmluZSBYU0RJUlhfTU9ERV9TRF9NQVNLCTB4 MQo+ID4gKyNkZWZpbmUgWFNESVJYX01PREVfM0dfTUFTSwkweDIKPiA+ICsjZGVmaW5lIFhTRElS WF9NT0RFXzZHX01BU0sJMHg0Cj4gPiArI2RlZmluZSBYU0RJUlhfTU9ERV8xMkdJX01BU0sJMHg1 Cj4gPiArI2RlZmluZSBYU0RJUlhfTU9ERV8xMkdGX01BU0sJMHg2Cj4gPiArCj4gPiArLyogTWF4 aW11bSBudW1iZXIgb2YgZXZlbnRzIHBlciBmaWxlIGhhbmRsZS4gKi8KPiA+ICsjZGVmaW5lIFhT RElSWF9NQVhfRVZFTlRTCTgKPiA+ICsKPiA+ICsvKiBTVDM1MiByZWxhdGVkIG1hY3JvcyAqLwo+ ID4gKyNkZWZpbmUgWFNUMzUyX1BBWUxPQURfQllURTFfTUFTSwlHRU5NQVNLKDcsIDApCj4gPiAr I2RlZmluZSBYU1QzNTJfUEFZTE9BRF9CWVRFMl9PRkZTRVQJOAo+ID4gKyNkZWZpbmUgWFNUMzUy X1BBWUxPQURfQllURTNfT0ZGU0VUCTE2Cj4gPiArI2RlZmluZSBYU1QzNTJfUEFZTE9BRF9CWVRF NF9PRkZTRVQJMjQKPiA+ICsKPiA+ICsjZGVmaW5lIFhTVDM1Ml9CWVRFMV9TVDI5Ml8xeDcyMExf MV81RwkJMHg4NAo+ID4gKyNkZWZpbmUgWFNUMzUyX0JZVEUxX1NUMjkyXzF4MTA4MExfMV81RwkJ MHg4NQo+ID4gKyNkZWZpbmUgWFNUMzUyX0JZVEUxX1NUNDI1XzIwMDhfNzUwTF8zR0IJMHg4OAo+ ID4gKyNkZWZpbmUgWFNUMzUyX0JZVEUxX1NUNDI1XzIwMDhfMTEyNUxfM0dBCTB4ODkKPiA+ICsj ZGVmaW5lIFhTVDM1Ml9CWVRFMV9TVDM3Ml9ETF8zR0IJCTB4OGEKPiA+ICsjZGVmaW5lIFhTVDM1 Ml9CWVRFMV9TVDM3Ml8yeDcyMExfM0dCCQkweDhiCj4gPiArI2RlZmluZSBYU1QzNTJfQllURTFf U1QzNzJfMngxMDgwTF8zR0IJCTB4OGMKPiA+ICsjZGVmaW5lIFhTVDM1Ml9CWVRFMV9TVDIwODFf MTBfMjE2MExfNkcJCTB4YzAKPiA+ICsjZGVmaW5lIFhTVDM1Ml9CWVRFMV9TVDIwODFfMTBfMl8x MDgwTF82RwkweGMxCj4gPiArI2RlZmluZSBYU1QzNTJfQllURTFfU1QyMDgxXzEwX0RMXzIxNjBM XzZHCTB4YzIKPiA+ICsjZGVmaW5lIFhTVDM1Ml9CWVRFMV9TVDIwODJfMTBfMjE2MExfMTJHCTB4 Y2UKPiA+ICsKPiA+ICsjZGVmaW5lIFhTVDM1Ml9CWVRFMl9UU19UWVBFX01BU0sJCUJJVCgxNSkK PiA+ICsjZGVmaW5lIFhTVDM1Ml9CWVRFMl9QSUNfVFlQRV9NQVNLCQlCSVQoMTQpCj4gPiArI2Rl ZmluZSBYU1QzNTJfQllURTJfVFNfUElDX1RZUEVfSU5URVJMQUNFRAkwCj4gPiArI2RlZmluZSBY U1QzNTJfQllURTJfVFNfUElDX1RZUEVfUFJPR1JFU1NJVkUJMQo+ID4gKwo+ID4gKyNkZWZpbmUg WFNUMzUyX0JZVEUyX0ZQU19NQVNLCQkJR0VOTUFTSygxMSwgOCkKPiA+ICsjZGVmaW5lIFhTVDM1 Ml9CWVRFMl9GUFNfMjRGCQkJMHgyCj4gPiArI2RlZmluZSBYU1QzNTJfQllURTJfRlBTXzI0CQkJ MHgzCj4gPiArI2RlZmluZSBYU1QzNTJfQllURTJfRlBTXzQ4RgkJCTB4NAo+ID4gKyNkZWZpbmUg WFNUMzUyX0JZVEUyX0ZQU18yNQkJCTB4NQo+ID4gKyNkZWZpbmUgWFNUMzUyX0JZVEUyX0ZQU18z MEYJCQkweDYKPiA+ICsjZGVmaW5lIFhTVDM1Ml9CWVRFMl9GUFNfMzAJCQkweDcKPiA+ICsjZGVm aW5lIFhTVDM1Ml9CWVRFMl9GUFNfNDgJCQkweDgKPiA+ICsjZGVmaW5lIFhTVDM1Ml9CWVRFMl9G UFNfNTAJCQkweDkKPiA+ICsjZGVmaW5lIFhTVDM1Ml9CWVRFMl9GUFNfNjBGCQkJMHhhCj4gPiAr I2RlZmluZSBYU1QzNTJfQllURTJfRlBTXzYwCQkJMHhiCj4gPiArLyogVGFibGUgNCBTVCAyMDgx LTEwOjIwMTUgKi8KPiA+ICsjZGVmaW5lIFhTVDM1Ml9CWVRFMl9GUFNfOTYJCQkweGMKPiA+ICsj ZGVmaW5lIFhTVDM1Ml9CWVRFMl9GUFNfMTAwCQkJMHhkCj4gPiArI2RlZmluZSBYU1QzNTJfQllU RTJfRlBTXzEyMAkJCTB4ZQo+ID4gKyNkZWZpbmUgWFNUMzUyX0JZVEUyX0ZQU18xMjBGCQkJMHhm Cj4gPiArCj4gPiArI2RlZmluZSBYU1QzNTJfQllURTNfQUNUX0xVTUFfQ09VTlRfTUFTSwlCSVQo MjIpCj4gPiArCj4gPiArI2RlZmluZSBYU1QzNTJfQllURTNfQ09MT1JfRk9STUFUX01BU0sJCUdF Tk1BU0soMTksIDE2KQo+ID4gKyNkZWZpbmUgWFNUMzUyX0JZVEUzX0NPTE9SX0ZPUk1BVF80MjIJ CTB4MAo+ID4gKyNkZWZpbmUgWFNUMzUyX0JZVEUzX0NPTE9SX0ZPUk1BVF9ZVVY0NDQJMHgxCj4g PiArI2RlZmluZSBYU1QzNTJfQllURTNfQ09MT1JfRk9STUFUXzQyMAkJMHgzCj4gPiArI2RlZmlu ZSBYU1QzNTJfQllURTNfQ09MT1JfRk9STUFUX0dCUgkJMHgyCj4gPiArCj4gPiArI2RlZmluZSBY U1QzNTJfQllURTNfQ09MT1JJTUVUUllfTUFTSwkJR0VOTUFTSygyMSwgMjApCj4gPiArI2RlZmlu ZSBYU1QzNTJfQllURTNfQ09MT1JJTUVUUllfQlQ3MDkJCTAKPiA+ICsjZGVmaW5lIFhTVDM1Ml9C WVRFM19DT0xPUklNRVRSWV9DT0xPUl9WQU5DCTEKPiA+ICsjZGVmaW5lIFhTVDM1Ml9CWVRFM19D T0xPUklNRVRSWV9VSERUVgkJMgo+ID4gKyNkZWZpbmUgWFNUMzUyX0JZVEUzX0NPTE9SSU1FVFJZ X1VOS05PV04JMwo+ID4gKwo+ID4gKyNkZWZpbmUgWFNUMzUyX0JZVEU0X0JJVF9ERVBUSF9NQVNL CQlHRU5NQVNLKDI1LCAyNCkKPiA+ICsjZGVmaW5lIFhTVDM1Ml9CWVRFNF9CSVRfREVQVEhfMTAJ CTB4MQo+ID4gKyNkZWZpbmUgWFNUMzUyX0JZVEU0X0JJVF9ERVBUSF8xMgkJMHgyCj4gPiArCj4g PiArLyogR1QgaW5wdXQgY2xvY2sgZm9yIHNkaV9yeF9jbGsgKi8KPiA+ICsjZGVmaW5lIENMS19J TlQJCTE0ODUwMDAwMFVMCj4gPiArCj4gPiArI2RlZmluZSBYU0RJUlhTU19XSURUSF9NSU4gICAg ICAgICAgICAgICAgICAgIDcyMAo+ID4gKyNkZWZpbmUgWFNESVJYU1NfV0lEVEhfTUFYICAgICAg ICAgICAgICAgICAgICA0MDk2Cj4gPiArI2RlZmluZSBYU0RJUlhTU19IRUlHSFRfTUlOICAgICAg ICAgICAgICAgICAgIDI0Mwo+ID4gKyNkZWZpbmUgWFNESVJYU1NfSEVJR0hUX01BWCAgICAgICAg ICAgICAgICAgICAyMTYwCj4gPiArI2RlZmluZSBYU0RJUlhTU19QSVhFTENMT0NLX01JTiAgICAg ICAgICAgICAgIDEzNTAwMDAwCj4gPiArI2RlZmluZSBYU0RJUlhTU19QSVhFTENMT0NLX01BWCAg ICAgICAgICAgICAgIDU5NDAwMDAwMAo+ID4gKwo+ID4gKy8qKgo+ID4gKyAqIGVudW0gc2RpX2Zh bWlseV9lbmMgLSBTREkgVHJhbnNwb3J0IFZpZGVvIEZvcm1hdCBEZXRlY3RlZCB3aXRoIEFjdGl2 ZSBQaXhlbHMKPiA+ICsgKiBAWFNESVJYX1NNUFRFX1NUXzI3NDogU01QVEUgU1QgMjc0IGRldGVj dGVkIHdpdGggQVAgMTkyMHgxMDgwCj4gPiArICogQFhTRElSWF9TTVBURV9TVF8yOTY6IFNNUFRF IFNUIDI5NiBkZXRlY3RlZCB3aXRoIEFQIDEyODB4NzIwCj4gPiArICogQFhTRElSWF9TTVBURV9T VF8yMDQ4XzI6IFNNUFRFIFNUIDIwNDgtMiBkZXRlY3RlZCB3aXRoIEFQIDIwNDh4MTA4MAo+ID4g KyAqIEBYU0RJUlhfU01QVEVfU1RfMjk1OiBTTVBURSBTVCAyOTUgZGV0ZWN0ZWQgd2l0aCBBUCAx OTIweDEwODAKPiA+ICsgKiBAWFNESVJYX05UU0M6IE5UU0MgZW5jb2RpbmcgZGV0ZWN0ZWQgd2l0 aCBBUCA3MjB4NDg2Cj4gPiArICogQFhTRElSWF9QQUw6IFBBTCBlbmNvZGluZyBkZXRlY3RlZCB3 aXRoIEFQIDcyMHg1NzYKPiA+ICsgKiBAWFNESVJYX1RTX1VOS05PV046IFVua25vd24gU01QVEUg VHJhbnNwb3J0IGZhbWlseSB0eXBlCj4gPiArICovCj4gPiArZW51bSBzZGlfZmFtaWx5X2VuYyB7 Cj4gPiArCVhTRElSWF9TTVBURV9TVF8yNzQJPSAwLAo+ID4gKwlYU0RJUlhfU01QVEVfU1RfMjk2 CT0gMSwKPiA+ICsJWFNESVJYX1NNUFRFX1NUXzIwNDhfMgk9IDIsCj4gPiArCVhTRElSWF9TTVBU RV9TVF8yOTUJPSAzLAo+ID4gKwlYU0RJUlhfTlRTQwkJPSA4LAo+ID4gKwlYU0RJUlhfUEFMCQk9 IDksCj4gPiArCVhTRElSWF9UU19VTktOT1dOCT0gMTUKPiA+ICt9Owo+ID4gKwo+ID4gKy8qKgo+ ID4gKyAqIHN0cnVjdCB4c2Rpcnhzc19zdGF0ZSAtIFNESSBSeCBTdWJzeXN0ZW0gZGV2aWNlIHN0 cnVjdHVyZQo+ID4gKyAqIEBzdWJkZXY6IFRoZSB2NGwyIHN1YmRldiBzdHJ1Y3R1cmUKPiA+ICsg KiBAY3RybF9oYW5kbGVyOiBjb250cm9sIGhhbmRsZXIKPiA+ICsgKiBAZGVmYXVsdF9mb3JtYXQ6 IGRlZmF1bHQgVjRMMiBtZWRpYSBidXMgZm9ybWF0Cj4gPiArICogQHBhZDogc291cmNlIG1lZGlh IHBhZAo+ID4gKyAqIEBkZXY6IFBsYXRmb3JtIHN0cnVjdHVyZQo+ID4gKyAqIEBpb21lbTogQmFz ZSBhZGRyZXNzIG9mIHN1YnN5c3RlbQo+ID4gKyAqIEBjbGtzOiBhcnJheSBvZiBjbG9ja3MKPiA+ ICsgKiBAcHJldl9pc19mcmFjOiBQcmV2aW91cyBjbG9jayBpcyBmcmFjdGlvbmFsIG9yIG5vdCBm bGFnCj4gPiArICogQGJwYzogQml0cyBwZXIgY29tcG9uZW50LCBjYW4gYmUgMTAgb3IgMTIKPiA+ ICsgKiBAbW9kZTogM0cvNkcvMTJHIG1vZGUKPiA+ICsgKiBAbnVtX2Nsa3M6IG51bWJlciBvZiBj bG9ja3MKPiA+ICsgKiBAaW5jbHVkZV9lZGg6IEVESCBwcm9jZXNzb3IgcHJlc2VuY2UKPiA+ICsg KiBAc2xvY2s6IHNwaW5sb2NrIHRvIHByb3RlY3QgYmVsb3cgbWVtYmVycwo+ID4gKyAqIEBmb3Jt YXQ6IEFjdGl2ZSBWNEwyIGZvcm1hdCBkZXRlY3RlZAo+ID4gKyAqIEBzcmNfZm9ybWF0OiBBY3Rp dmUgVjRMMiBmb3JtYXQgb24gc291cmNlIHBhZAo+ID4gKyAqIEBmcmFtZV9pbnRlcnZhbDogQ2Fw dHVyZXMgdGhlIGZyYW1lIHJhdGUKPiA+ICsgKiBAY3VycmVudF90aW1pbmdzOiBEViB0aW1pbmdz IGZyb20gYXBwbGljYXRpb24KPiA+ICsgKiBAZGV0ZWN0ZWRfdGltaW5nc19pbmRleDogaW5kZXgg b2YgRFYgdGltaW5ncyBkZXRlY3RlZCBvbiBpbmNvbWluZyBzdHJlYW0KPiA+ICsgKiBAdmlkbG9j a3dpbjogVmlkZW8gbG9jayB3aW5kb3cgdmFsdWUgc2V0IGJ5IGNvbnRyb2wKPiA+ICsgKiBAZWRo bWFzazogRURIIG1hc2sgc2V0IGJ5IGNvbnRyb2wKPiA+ICsgKiBAc2VhcmNobWFzazogU2VhcmNo IG1hc2sgc2V0IGJ5IGNvbnRyb2wKPiA+ICsgKiBAc3RyZWFtaW5nOiBGbGFnIGZvciBzdG9yaW5n IHN0cmVhbWluZyBzdGF0ZQo+ID4gKyAqIEB2aWRsb2NrZWQ6IEZsYWcgaW5kaWNhdGluZyBTREkg UnggaGFzIGxvY2tlZCBvbnRvIHZpZGVvIHN0cmVhbQo+ID4gKyAqIEB0c19pc19pbnRlcmxhY2Vk OiBGbGFnIGluZGljYXRpbmcgVHJhbnNwb3J0IFN0cmVhbSBpcyBpbnRlcmxhY2VkLgo+ID4gKyAq IEBmcmFtZXJfZW5hYmxlOiBGbGFnIGZvciBmcmFtZXIgZW5hYmxlZCBvciBub3Qgc2V0IGJ5IGNv bnRyb2wKPiA+ICsgKgo+ID4gKyAqIFRoaXMgc3RydWN0dXJlIGNvbnRhaW5zIHRoZSBkZXZpY2Ug ZHJpdmVyIHJlbGF0ZWQgcGFyYW1ldGVycwo+ID4gKyAqLwo+ID4gK3N0cnVjdCB4c2Rpcnhzc19z dGF0ZSB7Cj4gPiArCXN0cnVjdCB2NGwyX3N1YmRldiBzdWJkZXY7Cj4gPiArCXN0cnVjdCB2NGwy X2N0cmxfaGFuZGxlciBjdHJsX2hhbmRsZXI7Cj4gPiArCXN0cnVjdCB2NGwyX21idXNfZnJhbWVm bXQgZGVmYXVsdF9mb3JtYXQ7Cj4gPiArCXN0cnVjdCBtZWRpYV9wYWQgcGFkOwo+ID4gKwlzdHJ1 Y3QgZGV2aWNlICpkZXY7Cj4gPiArCXZvaWQgX19pb21lbSAqaW9tZW07Cj4gPiArCXN0cnVjdCBj bGtfYnVsa19kYXRhICpjbGtzOwo+ID4gKwlpbnQgcHJldl9pc19mcmFjOwoKSWYgSSB1bmRlcnN0 YW5kIHRoZSBjb2RlIGNvcnJlY3RseSwgdGhpcyBmaWVsZCBkb2Vzbid0IHN0b3JlIHRoZQpwcmV2 aW91cyB2YWx1ZSBidXQgdGhlIGN1cnJlbnQgdmFsdWUgcHJvZ3JhbW1lZCB0byB0aGUgaGFyZHdh cmUuIEl0CmNvdWxkIGJlIG5hbWVkIGNsa19pc19mcmFjIG9yIHNvbWV0aGluZyBzaW1pbGFyLgoK PiA+ICsJdTMyIGJwYzsKPiA+ICsJdTMyIG1vZGU7Cj4gPiArCXVuc2lnbmVkIGludCBudW1fY2xr czsKPiA+ICsJYm9vbCBpbmNsdWRlX2VkaDsKPiA+ICsKPiA+ICsJLyoKPiA+ICsJICogVGhpcyBz cGlubG9jayBpcyB1c2VkIHRvIHByb3RlY3QgdGhlIGJlbG93IG1lbWJlcnMKPiA+ICsJICogZm9y bWF0LCBzcmNfZm9ybWF0LCBmcmFtZV9pbnRlcnZhbCwgY3VycmVudF90aW1pbmdzLAo+ID4gKwkg KiBkZXRlY3RlZF90aW1pbmdzX2luZGV4LCB2aWRsb2Nrd2luLCBlZGhtYXNrLCBzZWFyY2htYXNr LAo+ID4gKwkgKiBzdHJlYW1pbmcsIHZpZGxvY2tlZCwgdHNfaXNfaW50ZXJsYWNlZCwgZnJhbWVy X2VuYWJsZQo+ID4gKwkgKi8KPiA+ICsJc3BpbmxvY2tfdCBzbG9jazsKPiA+ICsJc3RydWN0IHY0 bDJfbWJ1c19mcmFtZWZtdCBmb3JtYXQ7Cj4gPiArCXN0cnVjdCB2NGwyX21idXNfZnJhbWVmbXQg c3JjX2Zvcm1hdDsKPiA+ICsJc3RydWN0IHY0bDJfZnJhY3QgZnJhbWVfaW50ZXJ2YWw7Cj4gPiAr CXN0cnVjdCB2NGwyX2R2X3RpbWluZ3MgY3VycmVudF90aW1pbmdzOwo+ID4gKwl1MzIgZGV0ZWN0 ZWRfdGltaW5nc19pbmRleDsKPiA+ICsJdTMyIHZpZGxvY2t3aW47Cj4gPiArCXUzMiBlZGhtYXNr Owo+ID4gKwl1MTYgc2VhcmNobWFzazsKPiA+ICsJYm9vbCBzdHJlYW1pbmc7Cj4gPiArCWJvb2wg dmlkbG9ja2VkOwo+ID4gKwlib29sIHRzX2lzX2ludGVybGFjZWQ7Cj4gPiArCWJvb2wgZnJhbWVy X2VuYWJsZTsKPiA+ICt9Owo+ID4gKwo+ID4gKy8qIExpc3Qgb2YgY2xvY2tzIHJlcXVpcmVkIGJ5 IFVIRC1TREkgUnggc3Vic3lzdGVtICovCj4gPiArc3RhdGljIGNvbnN0IGNoYXIgKiBjb25zdCB4 c2Rpcnhzc19jbGtzW10gPSB7Cj4gPiArCSJzX2F4aV9hY2xrIiwgInNkaV9yeF9jbGsiLCAidmlk ZW9fb3V0X2NsayIsCj4gPiArfTsKPiA+ICsKPiA+ICsvKiBUT0RPIC0gQWRkIFlVViA0NDQvNDIw IGFuZCBSQkcgMTAvMTIgYnBjIG1idXMgZm9ybWF0cyBoZXJlICovCj4gPiArc3RhdGljIGNvbnN0 IHUzMiB4c2Rpcnhzc18xMGJwY19tYnVzX2ZtdHNbXSA9IHsKPiA+ICsJTUVESUFfQlVTX0ZNVF9V WVZZMTBfMVgyMCwKPiA+ICt9Owo+ID4gKwo+ID4gK3N0YXRpYyBjb25zdCB1MzIgeHNkaXJ4c3Nf MTJicGNfbWJ1c19mbXRzW10gPSB7Cj4gPiArCU1FRElBX0JVU19GTVRfVVlWWTEyXzFYMjQsCj4g PiArfTsKPiA+ICsKPiA+ICtzdGF0aWMgY29uc3Qgc3RydWN0IHY0bDJfZHZfdGltaW5ncyBmbXRf Y2FwW10gPSB7Cj4gPiArCVY0TDJfRFZfQlRfU0RJXzcyMFg0ODdJNjAsCj4gPiArCVY0TDJfRFZf QlRfQ0VBXzcyMFg1NzZJNTAsCj4gPiArCVY0TDJfRFZfQlRfQ0VBXzEyODBYNzIwUDI0LAo+ID4g KwlWNEwyX0RWX0JUX0NFQV8xMjgwWDcyMFAyNSwKPiA+ICsJVjRMMl9EVl9CVF9DRUFfMTI4MFg3 MjBQMzAsCj4gPiArCVY0TDJfRFZfQlRfQ0VBXzEyODBYNzIwUDUwLAo+ID4gKwlWNEwyX0RWX0JU X0NFQV8xMjgwWDcyMFA2MCwKPiA+ICsJVjRMMl9EVl9CVF9DRUFfMTkyMFgxMDgwUDI0LAo+ID4g KwlWNEwyX0RWX0JUX0NFQV8xOTIwWDEwODBQMzAsCj4gPiArCVY0TDJfRFZfQlRfQ0VBXzE5MjBY MTA4MEk1MCwKPiA+ICsJVjRMMl9EVl9CVF9DRUFfMTkyMFgxMDgwSTYwLAo+ID4gKwlWNEwyX0RW X0JUX0NFQV8xOTIwWDEwODBQNDgsCj4gPiArCVY0TDJfRFZfQlRfQ0VBXzE5MjBYMTA4MFA1MCwK PiA+ICsJVjRMMl9EVl9CVF9DRUFfMTkyMFgxMDgwUDYwLAo+ID4gKwlWNEwyX0RWX0JUX0NFQV8z ODQwWDIxNjBQMjQsCj4gPiArCVY0TDJfRFZfQlRfQ0VBXzM4NDBYMjE2MFAzMCwKPiA+ICsJVjRM Ml9EVl9CVF9DRUFfMzg0MFgyMTYwUDQ4LAo+ID4gKwlWNEwyX0RWX0JUX0NFQV8zODQwWDIxNjBQ NTAsCj4gPiArCVY0TDJfRFZfQlRfQ0VBXzM4NDBYMjE2MFA2MCwKPiA+ICsJVjRMMl9EVl9CVF9D RUFfNDA5NlgyMTYwUDI0LAo+ID4gKwlWNEwyX0RWX0JUX0NFQV80MDk2WDIxNjBQMjUsCj4gPiAr CVY0TDJfRFZfQlRfQ0VBXzQwOTZYMjE2MFAzMCwKPiA+ICsJVjRMMl9EVl9CVF9DRUFfNDA5Nlgy MTYwUDQ4LAo+ID4gKwlWNEwyX0RWX0JUX0NFQV80MDk2WDIxNjBQNTAsCj4gPiArCVY0TDJfRFZf QlRfQ0VBXzQwOTZYMjE2MFA2MCwKPiA+ICsKPiA+ICsJWExOWF9WNEwyX0RWX0JUXzIwNDhYMTA4 MFAyNCwKPiA+ICsJWExOWF9WNEwyX0RWX0JUXzIwNDhYMTA4MFAyNSwKPiA+ICsJWExOWF9WNEwy X0RWX0JUXzIwNDhYMTA4MFAzMCwKPiA+ICsJWExOWF9WNEwyX0RWX0JUXzIwNDhYMTA4MEk0OCwK PiA+ICsJWExOWF9WNEwyX0RWX0JUXzIwNDhYMTA4MEk1MCwKPiA+ICsJWExOWF9WNEwyX0RWX0JU XzIwNDhYMTA4MEk2MCwKPiA+ICsJWExOWF9WNEwyX0RWX0JUXzIwNDhYMTA4MFA0OCwKPiA+ICsJ WExOWF9WNEwyX0RWX0JUXzIwNDhYMTA4MFA1MCwKPiA+ICsJWExOWF9WNEwyX0RWX0JUXzIwNDhY MTA4MFA2MCwKPiA+ICsJWExOWF9WNEwyX0RWX0JUXzE5MjBYMTA4MEk0OCwKPiAKPiBMb29raW5n IGF0IHRoaXM6Cj4gCj4gaHR0cHM6Ly93d3cuc21wdGUub3JnL3NpdGVzL2RlZmF1bHQvZmlsZXMv aW1hZ2VzL1NNUFRFJTIwd2FsbGNoYXJ0JTIzMi42XzIwXzE3LUpVTFklMjAyMDE3LnBkZgo+IAo+ IEkgd291bGQgdGhpbmsgdGhhdCB0aGVzZSBmb3JtYXRzIGFyZSBkZWZpbmVkIGluIG9uZSBvZiB0 aGUgc21wdGUgc3RhbmRhcmRzLAo+IHByb2JhYmx5IFNUIDIwNDgtMi4KPiAKPiBDYW4geW91IHRh a2UgYSBsb29rIGlmIHlvdSBoYXZlIHRoaXMgc3RhbmRhcmQ/Cj4gCj4gPiArfTsKPiA+ICsKPiA+ ICtzdHJ1Y3QgeHNkaXJ4c3NfZHZfbWFwIHsKPiA+ICsJdTMyIHdpZHRoOwo+ID4gKwl1MzIgaGVp Z2h0Owo+ID4gKwl1MzIgZnBzOwo+ID4gKwlzdHJ1Y3QgdjRsMl9kdl90aW1pbmdzIHRpbWluZzsK PiA+ICt9Owo+ID4gKwo+ID4gK3N0YXRpYyBjb25zdCBzdHJ1Y3QgeHNkaXJ4c3NfZHZfbWFwIHhz ZGlyeHNzX2R2X3RpbWluZ3NbXSA9IHsKPiA+ICsJLyogU0QgLSA3MjB4NDg3aTYwICovCj4gPiAr CXsgNzIwLCAyNDMsIDMwLCBWNEwyX0RWX0JUX1NESV83MjBYNDg3STYwIH0sCj4gPiArCS8qIFNE IC0gNzIweDU3Nmk1MCAqLwo+ID4gKwl7IDcyMCwgMjg4LCAyNSwgVjRMMl9EVl9CVF9DRUFfNzIw WDU3Nkk1MCB9LAo+ID4gKwkvKiBIRCAtIDEyODB4NzIwcDIzLjk4ICovCj4gPiArCS8qIEhEIC0g MTI4MHg3MjBwMjQgKi8KPiA+ICsJeyAxMjgwLCA3MjAsIDI0LCBWNEwyX0RWX0JUX0NFQV8xMjgw WDcyMFAyNCB9LAo+ID4gKwkvKiBIRCAtIDEyODB4NzIwcDI1ICovCj4gPiArCXsgMTI4MCwgNzIw LCAyNSwgVjRMMl9EVl9CVF9DRUFfMTI4MFg3MjBQMjUgfSwKPiA+ICsJLyogSEQgLSAxMjgweDcy MHAyOS45NyAqLwo+ID4gKwkvKiBIRCAtIDEyODB4NzIwcDMwICovCj4gPiArCXsgMTI4MCwgNzIw LCAzMCwgVjRMMl9EVl9CVF9DRUFfMTI4MFg3MjBQMzAgfSwKPiA+ICsJLyogSEQgLSAxMjgweDcy MHA1MCAqLwo+ID4gKwl7IDEyODAsIDcyMCwgNTAsIFY0TDJfRFZfQlRfQ0VBXzEyODBYNzIwUDUw IH0sCj4gPiArCS8qIEhEIC0gMTI4MHg3MjBwNTkuOTQgKi8KPiA+ICsJLyogSEQgLSAxMjgweDcy MHA2MCAqLwo+ID4gKwl7IDEyODAsIDcyMCwgNjAsIFY0TDJfRFZfQlRfQ0VBXzEyODBYNzIwUDYw IH0sCj4gPiArCS8qIEhEIC0gMTkyMHgxMDgwcDIzLjk4ICovCj4gPiArCS8qIEhEIC0gMTkyMHgx MDgwcDI0ICovCj4gPiArCXsgMTkyMCwgMTA4MCwgMjQsIFY0TDJfRFZfQlRfQ0VBXzE5MjBYMTA4 MFAyNCB9LAo+ID4gKwkvKiBIRCAtIDE5MjB4MTA4MHAyNSAqLwo+ID4gKwl7IDE5MjAsIDEwODAs IDI1LCBWNEwyX0RWX0JUX0NFQV8xOTIwWDEwODBQMjUgfSwKPiA+ICsJLyogSEQgLSAxOTIweDEw ODBwMjkuOTcgKi8KPiA+ICsJLyogSEQgLSAxOTIweDEwODBwMzAgKi8KPiA+ICsJeyAxOTIwLCAx MDgwLCAzMCwgVjRMMl9EVl9CVF9DRUFfMTkyMFgxMDgwUDMwIH0sCj4gPiArCj4gPiArCS8qIEhE IC0gMjA0OHgxMDgwcDIzLjk4ICovCj4gPiArCS8qIEhEIC0gMjA0OHgxMDgwcDI0ICovCj4gPiAr CXsgMjA0OCwgMTA4MCwgMjQsIFhMTlhfVjRMMl9EVl9CVF8yMDQ4WDEwODBQMjQgfSwKPiA+ICsJ LyogSEQgLSAyMDQ4eDEwODBwMjUgKi8KPiA+ICsJeyAyMDQ4LCAxMDgwLCAyNCwgWExOWF9WNEwy X0RWX0JUXzIwNDhYMTA4MFAyNSB9LAo+ID4gKwkvKiBIRCAtIDIwNDh4MTA4MHAyOS45NyAqLwo+ ID4gKwkvKiBIRCAtIDIwNDh4MTA4MHAzMCAqLwo+ID4gKwl7IDIwNDgsIDEwODAsIDI0LCBYTE5Y X1Y0TDJfRFZfQlRfMjA0OFgxMDgwUDMwIH0sCj4gPiArCS8qIEhEIC0gMTkyMHgxMDgwaTQ3Ljk1 ICovCj4gPiArCS8qIEhEIC0gMTkyMHgxMDgwaTQ4ICovCj4gPiArCXsgMTkyMCwgNTQwLCAyNCwg WExOWF9WNEwyX0RWX0JUXzE5MjBYMTA4MEk0OCB9LAo+ID4gKwo+ID4gKwkvKiBIRCAtIDE5MjB4 MTA4MGk1MCAqLwo+ID4gKwl7IDE5MjAsIDU0MCwgMjUsIFY0TDJfRFZfQlRfQ0VBXzE5MjBYMTA4 MEk1MCB9LAo+ID4gKwkvKiBIRCAtIDE5MjB4MTA4MGk1OS45NCAqLwo+ID4gKwkvKiBIRCAtIDE5 MjB4MTA4MGk2MCAqLwo+ID4gKwl7IDE5MjAsIDU0MCwgMzAsIFY0TDJfRFZfQlRfQ0VBXzE5MjBY MTA4MEk2MCB9LAo+ID4gKwo+ID4gKwkvKiBIRCAtIDIwNDh4MTA4MGk0Ny45NSAqLwo+ID4gKwkv KiBIRCAtIDIwNDh4MTA4MGk0OCAqLwo+ID4gKwl7IDIwNDgsIDU0MCwgMjQsIFhMTlhfVjRMMl9E Vl9CVF8yMDQ4WDEwODBJNDggfSwKPiA+ICsJLyogSEQgLSAyMDQ4eDEwODBpNTAgKi8KPiA+ICsJ eyAyMDQ4LCA1NDAsIDI1LCBYTE5YX1Y0TDJfRFZfQlRfMjA0OFgxMDgwSTUwIH0sCj4gPiArCS8q IEhEIC0gMjA0OHgxMDgwaTU5Ljk0ICovCj4gPiArCS8qIEhEIC0gMjA0OHgxMDgwaTYwICovCj4g PiArCXsgMjA0OCwgNTQwLCAzMCwgWExOWF9WNEwyX0RWX0JUXzIwNDhYMTA4MEk2MCB9LAo+ID4g KwkvKiAzRyAtIDE5MjB4MTA4MHA0Ny45NSAqLwo+ID4gKwkvKiAzRyAtIDE5MjB4MTA4MHA0OCAq Lwo+ID4gKwl7IDE5MjAsIDEwODAsIDQ4LCBWNEwyX0RWX0JUX0NFQV8xOTIwWDEwODBQNDggfSwK PiA+ICsKPiA+ICsJLyogM0cgLSAxOTIweDEwODBwNTAgMTQ4LjUgKi8KPiA+ICsJeyAxOTIwLCAx MDgwLCA1MCwgVjRMMl9EVl9CVF9DRUFfMTkyMFgxMDgwUDUwIH0sCj4gPiArCS8qIDNHIC0gMTky MHgxMDgwcDU5Ljk0IDE0OC41LzEuMDAxICovCj4gPiArCS8qIDNHIC0gMTkyMHgxMDgwcDYwIDE0 OC41ICovCj4gPiArCXsgMTkyMCwgMTA4MCwgNjAsIFY0TDJfRFZfQlRfQ0VBXzE5MjBYMTA4MFA2 MCB9LAo+ID4gKwo+ID4gKwkvKiAzRyAtIDIwNDh4MTA4MHA0Ny45NSAqLwo+ID4gKwkvKiAzRyAt IDIwNDh4MTA4MHA0OCAqLwo+ID4gKwl7IDIwNDgsIDEwODAsIDQ4LCBYTE5YX1Y0TDJfRFZfQlRf MjA0OFgxMDgwUDQ4IH0sCj4gPiArCS8qIDNHIC0gMjA0OHgxMDgwcDUwICovCj4gPiArCXsgMjA0 OCwgMTA4MCwgNTAsIFhMTlhfVjRMMl9EVl9CVF8yMDQ4WDEwODBQNTAgfSwKPiA+ICsJLyogM0cg LSAyMDQ4eDEwODBwNTkuOTQgKi8KPiA+ICsJLyogM0cgLSAyMDQ4eDEwODBwNjAgKi8KPiA+ICsJ eyAyMDQ4LCAxMDgwLCA2MCwgWExOWF9WNEwyX0RWX0JUXzIwNDhYMTA4MFA2MCB9LAo+ID4gKwo+ ID4gKwkvKiA2RyAtIDM4NDBYMjE2MHAyMy45OCAqLwo+ID4gKwkvKiA2RyAtIDM4NDBYMjE2MHAy NCAqLwo+ID4gKwl7IDM4NDAsIDIxNjAsIDI0LCBWNEwyX0RWX0JUX0NFQV8zODQwWDIxNjBQMjQg fSwKPiA+ICsJLyogNkcgLSAzODQwWDIxNjBwMjUgKi8KPiA+ICsJeyAzODQwLCAyMTYwLCAyNSwg VjRMMl9EVl9CVF9DRUFfMzg0MFgyMTYwUDI1IH0sCj4gPiArCS8qIDZHIC0gMzg0MFgyMTYwcDI5 Ljk3ICovCj4gPiArCS8qIDZHIC0gMzg0MFgyMTYwcDMwICovCj4gPiArCXsgMzg0MCwgMjE2MCwg MzAsIFY0TDJfRFZfQlRfQ0VBXzM4NDBYMjE2MFAzMCB9LAo+ID4gKwkvKiA2RyAtIDQwOTZYMjE2 MHAyMy45OCAqLwo+ID4gKwkvKiA2RyAtIDQwOTZYMjE2MHAyNCAqLwo+ID4gKwl7IDQwOTYsIDIx NjAsIDI0LCBWNEwyX0RWX0JUX0NFQV80MDk2WDIxNjBQMjQgfSwKPiA+ICsJLyogNkcgLSA0MDk2 WDIxNjBwMjUgKi8KPiA+ICsJeyA0MDk2LCAyMTYwLCAyNSwgVjRMMl9EVl9CVF9DRUFfNDA5Nlgy MTYwUDI1IH0sCj4gPiArCS8qIDZHIC0gNDA5NlgyMTYwcDI5Ljk3ICovCj4gPiArCS8qIDZHIC0g NDA5NlgyMTYwcDMwICovCj4gPiArCXsgNDA5NiwgMjE2MCwgMzAsIFY0TDJfRFZfQlRfQ0VBXzQw OTZYMjE2MFAzMCB9LAo+ID4gKwkvKiAxMkcgLSAzODQwWDIxNjBwNDcuOTUgKi8KPiA+ICsJLyog MTJHIC0gMzg0MFgyMTYwcDQ4ICovCj4gPiArCXsgMzg0MCwgMjE2MCwgNDgsIFY0TDJfRFZfQlRf Q0VBXzM4NDBYMjE2MFA0OCB9LAo+ID4gKwo+ID4gKwkvKiAxMkcgLSAzODQwWDIxNjBwNTAgKi8K PiA+ICsJeyAzODQwLCAyMTYwLCA1MCwgVjRMMl9EVl9CVF9DRUFfMzg0MFgyMTYwUDUwIH0sCj4g PiArCS8qIDEyRyAtIDM4NDBYMjE2MHA1OS45NCAqLwo+ID4gKwkvKiAxMkcgLSAzODQwWDIxNjBw NjAgKi8KPiA+ICsJeyAzODQwLCAyMTYwLCA2MCwgVjRMMl9EVl9CVF9DRUFfMzg0MFgyMTYwUDYw IH0sCj4gPiArCj4gPiArCS8qIDEyRyAtIDQwOTZYMjE2MHA0Ny45NSAqLwo+ID4gKwkvKiAxMkcg LSA0MDk2WDIxNjBwNDggKi8KPiA+ICsJeyAzODQwLCAyMTYwLCA0OCwgVjRMMl9EVl9CVF9DRUFf NDA5NlgyMTYwUDQ4IH0sCj4gPiArCj4gPiArCS8qIDEyRyAtIDQwOTZYMjE2MHA1MCAqLwo+ID4g Kwl7IDQwOTYsIDIxNjAsIDUwLCBWNEwyX0RWX0JUX0NFQV80MDk2WDIxNjBQNTAgfSwKPiA+ICsJ LyogMTJHIC0gNDA5NlgyMTYwcDU5Ljk0ICovCj4gPiArCS8qIDEyRyAtIDQwOTZYMjE2MHA2MCAq Lwo+ID4gKwl7IDQwOTYsIDIxNjAsIDYwLCBWNEwyX0RWX0JUX0NFQV80MDk2WDIxNjBQNjAgfSwK PiA+ICt9Owo+ID4gKwo+ID4gK3N0YXRpYyBjb25zdCBzdHJ1Y3QgdjRsMl9kdl90aW1pbmdzX2Nh cCB4c2Rpcnhzc190aW1pbmdzX2NhcCA9IHsKPiA+ICsJLnR5cGUgPSBWNEwyX0RWX0JUXzY1Nl8x MTIwLAo+ID4gKwkucGFkID0gMCwKPiA+ICsJLnJlc2VydmVkID0geyAwIH0sCj4gPiArCVY0TDJf SU5JVF9CVF9USU1JTkdTKFhTRElSWFNTX1dJRFRIX01JTiwgWFNESVJYU1NfV0lEVEhfTUFYLAo+ ID4gKwkJCSAgICAgWFNESVJYU1NfSEVJR0hUX01JTiwgWFNESVJYU1NfSEVJR0hUX01BWCwKPiA+ ICsJCQkgICAgIFhTRElSWFNTX1BJWEVMQ0xPQ0tfTUlOLCBYU0RJUlhTU19QSVhFTENMT0NLX01B WCwKPiA+ICsJCQkgICAgIFY0TDJfRFZfQlRfU1REX0NFQTg2MSB8IFY0TDJfRFZfQlRfU1REX1NE SSwKPiA+ICsJCQkgICAgIFY0TDJfRFZfQlRfQ0FQX1BST0dSRVNTSVZFCj4gPiArCQkJICAgICB8 IFY0TDJfRFZfQlRfQ0FQX0lOVEVSTEFDRUQpCj4gPiArCj4gPiArfTsKCkFzIHRoaXMgaXMgb25s eSB1c2VkIGluIHhzZGlyeHNzX2R2X3RpbWluZ3NfY2FwKCksIEkgd291bGQganVzdCBzZXQgdGhl CmZpZWxkcyB0aGVyZS4gVXAgdG8geW91LgoKPiA+ICsKPiA+ICtzdHJ1Y3QgcmVnbWFwIHsKPiA+ ICsJY29uc3QgY2hhciAqbmFtZTsKPiA+ICsJdTMyIG9mZnNldDsKPiA+ICt9Owo+ID4gKwo+ID4g K3N0YXRpYyBjb25zdCBzdHJ1Y3QgcmVnbWFwIHhzZGlyeHNzX3JlZ21hcFtdID0gewo+ID4gKwl7 IC5uYW1lID0gIlJlc2V0IENvbnRyb2wiLCAub2Zmc2V0ID0gWFNESVJYX1JTVF9DVFJMX1JFRyB9 LAo+ID4gKwl7IC5uYW1lID0gIk1vZHVsZSBDb250cm9sIiwgLm9mZnNldCA9IFhTRElSWF9NRExf Q1RSTF9SRUcgfSwKPiA+ICsJeyAubmFtZSA9ICJJbnRlcnJ1cHQgRW5hYmxlIiwgLm9mZnNldCA9 IFhTRElSWF9JRVJfUkVHIH0sCj4gPiArCXsgLm5hbWUgPSAiR2xvYmFsIEludGVycnVwdCBFbmFi bGUiLCAub2Zmc2V0ID0gWFNESVJYX0dMQkxfSUVSX1JFRyB9LAo+ID4gKwl7IC5uYW1lID0gIlNU MzUyIFZhbGlkIiwgLm9mZnNldCA9IFhTRElSWF9TVDM1Ml9WQUxJRF9SRUcgfSwKPiA+ICsJeyAu bmFtZSA9ICJTVDM1MiBEUzEiLCAub2Zmc2V0ID0gWFNESVJYX1NUMzUyX0RTMV9SRUcgfSwKPiA+ ICsJeyAubmFtZSA9ICJTVDM1MiBEUzIiLCAub2Zmc2V0ID0gWFNESVJYX1NUMzUyX0RTMl9SRUcg fSwKPiA+ICsJeyAubmFtZSA9ICJTVDM1MiBEUzMiLCAub2Zmc2V0ID0gWFNESVJYX1NUMzUyX0RT M19SRUcgfSwKPiA+ICsJeyAubmFtZSA9ICJTVDM1MiBEUzQiLCAub2Zmc2V0ID0gWFNESVJYX1NU MzUyX0RTNF9SRUcgfSwKPiA+ICsJeyAubmFtZSA9ICJTVDM1MiBEUzUiLCAub2Zmc2V0ID0gWFNE SVJYX1NUMzUyX0RTNV9SRUcgfSwKPiA+ICsJeyAubmFtZSA9ICJTVDM1MiBEUzYiLCAub2Zmc2V0 ID0gWFNESVJYX1NUMzUyX0RTNl9SRUcgfSwKPiA+ICsJeyAubmFtZSA9ICJTVDM1MiBEUzciLCAu b2Zmc2V0ID0gWFNESVJYX1NUMzUyX0RTN19SRUcgfSwKPiA+ICsJeyAubmFtZSA9ICJTVDM1MiBE UzgiLCAub2Zmc2V0ID0gWFNESVJYX1NUMzUyX0RTOF9SRUcgfSwKPiA+ICsJeyAubmFtZSA9ICJT VDM1MiBEUzkiLCAub2Zmc2V0ID0gWFNESVJYX1NUMzUyX0RTOV9SRUcgfSwKPiA+ICsJeyAubmFt ZSA9ICJTVDM1MiBEUzEwIiwgLm9mZnNldCA9IFhTRElSWF9TVDM1Ml9EUzEwX1JFRyB9LAo+ID4g Kwl7IC5uYW1lID0gIlNUMzUyIERTMTEiLCAub2Zmc2V0ID0gWFNESVJYX1NUMzUyX0RTMTFfUkVH IH0sCj4gPiArCXsgLm5hbWUgPSAiU1QzNTIgRFMxMiIsIC5vZmZzZXQgPSBYU0RJUlhfU1QzNTJf RFMxMl9SRUcgfSwKPiA+ICsJeyAubmFtZSA9ICJTVDM1MiBEUzEzIiwgLm9mZnNldCA9IFhTRElS WF9TVDM1Ml9EUzEzX1JFRyB9LAo+ID4gKwl7IC5uYW1lID0gIlNUMzUyIERTMTQiLCAub2Zmc2V0 ID0gWFNESVJYX1NUMzUyX0RTMTRfUkVHIH0sCj4gPiArCXsgLm5hbWUgPSAiU1QzNTIgRFMxNSIs IC5vZmZzZXQgPSBYU0RJUlhfU1QzNTJfRFMxNV9SRUcgfSwKPiA+ICsJeyAubmFtZSA9ICJTVDM1 MiBEUzE2IiwgLm9mZnNldCA9IFhTRElSWF9TVDM1Ml9EUzE2X1JFRyB9LAo+ID4gKwl7IC5uYW1l ID0gIlZlcnNpb24iLCAub2Zmc2V0ID0gWFNESVJYX1ZFUlNJT05fUkVHIH0sCj4gPiArCXsgLm5h bWUgPSAiU3Vic3lzdGVtIENvbmZpZyAiLCAub2Zmc2V0ID0gWFNESVJYX1NTX0NPTkZJR19SRUcg fSwKPiA+ICsJeyAubmFtZSA9ICJNb2RlIERldGVjdCIsIC5vZmZzZXQgPSBYU0RJUlhfTU9ERV9E RVRfU1RBVF9SRUcgfSwKPiA+ICsJeyAubmFtZSA9ICJUcmFuc3BvcnQgU3RyZWFtIERldGVjdCIs IC5vZmZzZXQgPSBYU0RJUlhfVFNfREVUX1NUQVRfUkVHIH0sCj4gPiArCXsgLm5hbWUgPSAiRURI IFN0YXR1cyIsIC5vZmZzZXQgPSBYU0RJUlhfRURIX1NUQVRfUkVHIH0sCj4gPiArCXsgLm5hbWUg PSAiRURIIEVycm9yIENvdW50IiwgLm9mZnNldCA9IFhTRElSWF9FREhfRVJSQ05UX0VOX1JFRyB9 LAo+ID4gKwl7IC5uYW1lID0gIkNSQyBlcnJvciBpbmRpY2F0aW9uIiwgLm9mZnNldCA9IFhTRElS WF9DUkNfRVJSQ05UX1JFRyB9LAo+ID4gKwl7IC5uYW1lID0gIlZpZGVvIExvY2sgV2luZG93Iiwg Lm9mZnNldCA9IFhTRElSWF9WSURfTE9DS19XSU5ET1dfUkVHIH0sCj4gPiArfTsKPiA+ICsKPiA+ ICtzdGF0aWMgaW5saW5lIHN0cnVjdCB4c2Rpcnhzc19zdGF0ZSAqCj4gPiArdG9feHNkaXJ4c3Nz dGF0ZShzdHJ1Y3QgdjRsMl9zdWJkZXYgKnN1YmRldikKPiA+ICt7Cj4gPiArCXJldHVybiBjb250 YWluZXJfb2Yoc3ViZGV2LCBzdHJ1Y3QgeHNkaXJ4c3Nfc3RhdGUsIHN1YmRldik7Cj4gPiArfQo+ ID4gKwo+ID4gKy8qCj4gPiArICogUmVnaXN0ZXIgcmVsYXRlZCBvcGVyYXRpb25zCj4gPiArICov Cj4gPiArc3RhdGljIGlubGluZSB1MzIgeHNkaXJ4c3NfcmVhZChzdHJ1Y3QgeHNkaXJ4c3Nfc3Rh dGUgKnhzZGlyeHNzLCB1MzIgYWRkcikKPiA+ICt7Cj4gPiArCXJldHVybiBpb3JlYWQzMih4c2Rp cnhzcy0+aW9tZW0gKyBhZGRyKTsKPiA+ICt9Cj4gPiArCj4gPiArc3RhdGljIGlubGluZSB2b2lk IHhzZGlyeHNzX3dyaXRlKHN0cnVjdCB4c2Rpcnhzc19zdGF0ZSAqeHNkaXJ4c3MsIHUzMiBhZGRy LAo+ID4gKwkJCQkgIHUzMiB2YWx1ZSkKPiA+ICt7Cj4gPiArCWlvd3JpdGUzMih2YWx1ZSwgeHNk aXJ4c3MtPmlvbWVtICsgYWRkcik7Cj4gPiArfQo+ID4gKwo+ID4gK3N0YXRpYyBpbmxpbmUgdm9p ZCB4c2Rpcnhzc19jbHIoc3RydWN0IHhzZGlyeHNzX3N0YXRlICp4c2RpcnhzcywgdTMyIGFkZHIs Cj4gPiArCQkJCXUzMiBjbHIpCj4gPiArewo+ID4gKwl4c2Rpcnhzc193cml0ZSh4c2Rpcnhzcywg YWRkciwgeHNkaXJ4c3NfcmVhZCh4c2RpcnhzcywgYWRkcikgJiB+Y2xyKTsKPiA+ICt9Cj4gPiAr Cj4gPiArc3RhdGljIGlubGluZSB2b2lkIHhzZGlyeHNzX3NldChzdHJ1Y3QgeHNkaXJ4c3Nfc3Rh dGUgKnhzZGlyeHNzLCB1MzIgYWRkciwKPiA+ICsJCQkJdTMyIHNldCkKPiA+ICt7Cj4gPiArCXhz ZGlyeHNzX3dyaXRlKHhzZGlyeHNzLCBhZGRyLCB4c2Rpcnhzc19yZWFkKHhzZGlyeHNzLCBhZGRy KSB8IHNldCk7Cj4gPiArfQo+ID4gKwo+ID4gKyNkZWZpbmUgWFNESVJYX0NPUkVfRElTQUJMRShz dGF0ZSkgIHhzZGlyeHNzX2Nscigoc3RhdGUpLCBYU0RJUlhfUlNUX0NUUkxfUkVHLFwKPiA+ICsJ CQkJCQkgWFNESVJYX1JTVF9DVFJMX1NTX0VOX01BU0spCj4gPiArCj4gPiArI2RlZmluZSBYU0RJ UlhfQ09SRV9FTkFCTEUoc3RhdGUpICB4c2Rpcnhzc19zZXQoKHN0YXRlKSwgWFNESVJYX1JTVF9D VFJMX1JFRyxcCj4gPiArCQkJCQkJWFNESVJYX1JTVF9DVFJMX1NTX0VOX01BU0spCj4gPiArCj4g PiArI2RlZmluZSBYU0RJUlhfR0xPQkFMX0lOVFJfRU5BQkxFKHN0YXRlKQlcCj4gPiArCXhzZGly eHNzX3NldCgoc3RhdGUpLCBYU0RJUlhfR0xCTF9JRVJfUkVHLCBYU0RJUlhfR0xCTF9JTlRSX0VO X01BU0spCj4gPiArCj4gPiArI2RlZmluZSBYU0RJUlhfR0xPQkFMX0lOVFJfRElTQUJMRShzdGF0 ZSkJXAo+ID4gKwl4c2Rpcnhzc19jbHIoKHN0YXRlKSwgWFNESVJYX0dMQkxfSUVSX1JFRywgWFNE SVJYX0dMQkxfSU5UUl9FTl9NQVNLKQoKQW55IHJlYXNvbiB0byBtYWtlIHRoZXNlIG1hY3JvcyBh bmQgbm90IGlubGluZSBmdW5jdGlvbnMgPwoKPiA+ICsKPiA+ICtzdGF0aWMgaW50IHhzZGlyeF9z ZXRfbW9kZWRldGVjdChzdHJ1Y3QgeHNkaXJ4c3Nfc3RhdGUgKnN0YXRlLCB1MTYgbWFzaykKPiA+ ICt7Cj4gPiArCXUzMiB2YWw7Cj4gPiArCXN0cnVjdCBkZXZpY2UgKmRldiA9IHN0YXRlLT5kZXY7 Cj4gPiArCj4gPiArCW1hc2sgJj0gWFNESVJYX0RFVEVDVF9BTExfTU9ERVM7Cj4gPiArCWlmICgh bWFzaykgewo+ID4gKwkJZGV2X2VycihkZXYsICJJbnZhbGlkIGJpdCBtYXNrID0gMHglMDh4XG4i LCBtYXNrKTsKPiA+ICsJCXJldHVybiAtRUlOVkFMOwo+ID4gKwl9Cj4gPiArCj4gPiArCWRldl9k YmcoZGV2LCAibWFzayA9IDB4JXhcbiIsIG1hc2spOwo+ID4gKwo+ID4gKwl2YWwgPSB4c2Rpcnhz c19yZWFkKHN0YXRlLCBYU0RJUlhfTURMX0NUUkxfUkVHKTsKPiA+ICsJdmFsICY9IH5YU0RJUlhf TURMX0NUUkxfTU9ERV9ERVRfRU5fTUFTSzsKPiA+ICsJdmFsICY9IH5YU0RJUlhfTURMX0NUUkxf TU9ERV9BVVRPX0RFVF9NQVNLOwo+ID4gKwl2YWwgJj0gflhTRElSWF9NRExfQ1RSTF9GT1JDRURf TU9ERV9NQVNLOwo+ID4gKwo+ID4gKwlpZiAoaHdlaWdodDE2KG1hc2spID4gMSkgewo+ID4gKwkJ LyogTXVsdGkgbW9kZSBkZXRlY3Rpb24gYXMgbW9yZSB0aGFuIDEgYml0IHNldCBpbiBtYXNrICov Cj4gPiArCQlkZXZfZGJnKGRldiwgIkRldGVjdCBtdWx0aXBsZSBtb2Rlc1xuIik7Cj4gPiArCj4g PiArCQlpZiAobWFzayAmIEJJVChYU0RJUlhfTU9ERV9TRF9PRkZTRVQpKQo+ID4gKwkJCXZhbCB8 PSBYU0RJUlhfTURMX0NUUkxfTU9ERV9TRF9FTl9NQVNLOwo+ID4gKwkJaWYgKG1hc2sgJiBCSVQo WFNESVJYX01PREVfSERfT0ZGU0VUKSkKPiA+ICsJCQl2YWwgfD0gWFNESVJYX01ETF9DVFJMX01P REVfSERfRU5fTUFTSzsKPiA+ICsJCS8qCj4gPiArCQkgKiBUaGVyZSBpcyBvbmx5IG9uZSBiaXQg aW4gSVAgdG8gZGV0ZWN0IDNHIG1vZGUuCj4gPiArCQkgKiBTbyBzZXQgaXQgd2hlbiAzR0Egb3Ig M0dCIG1hc2sgaXMgc2V0Lgo+ID4gKwkJICovCj4gPiArCQlpZiAobWFzayAmIChCSVQoWFNESVJY X01PREVfM0dBX09GRlNFVCkgfAo+ID4gKwkJCSAgICBCSVQoWFNESVJYX01PREVfM0dCX09GRlNF VCkpKQo+ID4gKwkJCXZhbCB8PSBYU0RJUlhfTURMX0NUUkxfTU9ERV8zR19FTl9NQVNLOwo+ID4g KwkJaWYgKG1hc2sgJiBCSVQoWFNESVJYX01PREVfNkdfT0ZGU0VUKSkKPiA+ICsJCQl2YWwgfD0g WFNESVJYX01ETF9DVFJMX01PREVfNkdfRU5fTUFTSzsKPiA+ICsJCWlmIChtYXNrICYgQklUKFhT RElSWF9NT0RFXzEyR0lfT0ZGU0VUKSkKPiA+ICsJCQl2YWwgfD0gWFNESVJYX01ETF9DVFJMX01P REVfMTJHSV9FTl9NQVNLOwo+ID4gKwkJaWYgKG1hc2sgJiBCSVQoWFNESVJYX01PREVfMTJHRl9P RkZTRVQpKQo+ID4gKwkJCXZhbCB8PSBYU0RJUlhfTURMX0NUUkxfTU9ERV8xMkdGX0VOX01BU0s7 Cj4gPiArCj4gPiArCQl2YWwgfD0gWFNESVJYX01ETF9DVFJMX01PREVfREVUX0VOX01BU0s7Cj4g PiArCX0gZWxzZSB7Cj4gPiArCQkvKiBGaXhlZCBNb2RlICovCj4gPiArCQl1MzIgZm9yY2VkX21v ZGVfbWFzazsKPiA+ICsKPiA+ICsJCWRldl9kYmcoZGV2LCAiRGV0ZWN0IGZpeGVkIG1vZGVcbiIp Owo+ID4gKwo+ID4gKwkJLyogRmluZCBvZmZzZXQgb2YgZmlyc3QgYml0IHNldCAqLwo+ID4gKwkJ c3dpdGNoIChtYXNrKSB7Cj4gPiArCQljYXNlIFhTRElSWF9NT0RFX1NEX09GRlNFVDoKPiA+ICsJ CQlmb3JjZWRfbW9kZV9tYXNrID0gWFNESVJYX01PREVfU0RfTUFTSzsKPiA+ICsJCQlicmVhazsK PiA+ICsJCWNhc2UgWFNESVJYX01PREVfSERfT0ZGU0VUOgo+ID4gKwkJCWZvcmNlZF9tb2RlX21h c2sgPSBYU0RJUlhfTU9ERV9IRF9NQVNLOwo+ID4gKwkJCWJyZWFrOwo+ID4gKwkJLyoKPiA+ICsJ CSAqIFRoZXJlIGlzIG9ubHkgb25lIGJpdCBpbiBJUCB0byBkZXRlY3QgM0cgbW9kZS4KPiA+ICsJ CSAqIFNvIHNldCBpdCB3aGVuIDNHQSBvciAzR0IgbWFzayBpcyBzZXQuCj4gPiArCQkgKi8KPiA+ ICsJCWNhc2UgWFNESVJYX01PREVfM0dBX09GRlNFVDoKPiA+ICsJCWNhc2UgWFNESVJYX01PREVf M0dCX09GRlNFVDoKPiA+ICsJCQlmb3JjZWRfbW9kZV9tYXNrID0gWFNESVJYX01PREVfM0dfTUFT SzsKPiA+ICsJCQlicmVhazsKPiA+ICsJCWNhc2UgWFNESVJYX01PREVfNkdfT0ZGU0VUOgo+ID4g KwkJCWZvcmNlZF9tb2RlX21hc2sgPSBYU0RJUlhfTU9ERV82R19NQVNLOwo+ID4gKwkJCWJyZWFr Owo+ID4gKwkJY2FzZSBYU0RJUlhfTU9ERV8xMkdJX09GRlNFVDoKPiA+ICsJCQlmb3JjZWRfbW9k ZV9tYXNrID0gWFNESVJYX01PREVfMTJHSV9NQVNLOwo+ID4gKwkJCWJyZWFrOwo+ID4gKwkJY2Fz ZSBYU0RJUlhfTU9ERV8xMkdGX09GRlNFVDoKPiA+ICsJCQlmb3JjZWRfbW9kZV9tYXNrID0gWFNE SVJYX01PREVfMTJHRl9NQVNLOwo+ID4gKwkJCWJyZWFrOwo+ID4gKwkJZGVmYXVsdDoKPiA+ICsJ CQlkZXZfZXJyKGRldiwgIkludmFsaWQgbWFzayBmb3IgZml4ZWQgZGV0ZWN0IG1vZGVcbiIpOwo+ ID4gKwkJCXJldHVybiAtRUlOVkFMOwo+ID4gKwkJfQo+ID4gKwkJZGV2X2RiZyhkZXYsICJGb3Jj ZWQgTW9kZSBNYXNrIDogMHgleFxuIiwKPiA+ICsJCQlmb3JjZWRfbW9kZV9tYXNrKTsKPiA+ICsJ CXZhbCB8PSBmb3JjZWRfbW9kZV9tYXNrIDw8IFhTRElSWF9NRExfQ1RSTF9GT1JDRURfTU9ERV9P RkZTRVQ7Cj4gPiArCX0KPiA+ICsKPiA+ICsJZGV2X2RiZyhkZXYsICJNb2RlcyB0byBiZSBkZXRl Y3RlZCA6IHNkaSBjdHJsIHJlZyA9IDB4JTA4eFxuIiwKPiA+ICsJCXZhbCk7Cj4gPiArCXhzZGly eHNzX3dyaXRlKHN0YXRlLCBYU0RJUlhfTURMX0NUUkxfUkVHLCB2YWwpOwo+ID4gKwo+ID4gKwly ZXR1cm4gMDsKPiA+ICt9Cj4gPiArCj4gPiArc3RhdGljIHZvaWQgeHNkaXJ4X3N0cmVhbWZsb3df Y29udHJvbChzdHJ1Y3QgeHNkaXJ4c3Nfc3RhdGUgKnN0YXRlLCBib29sIGVuYWJsZSkKPiA+ICt7 Cj4gPiArCS8qIFRoZSBzZGkgdG8gbmF0aXZlIGJyaWRnZSBpcyBmb2xsb3dlZCBieSBuYXRpdmUg dG8gYXhpczQgYnJpZGdlICovCj4gPiArCS8qCj4gPiArCSAqIFRPRE8gLSBFbmFibGUgWVVWNDQ0 L1JCRyBmb3JtYXQgaW4gdGhlIGJyaWRnZSBiYXNlZAo+ID4gKwkgKiBvbiBCWVRFMyBjb2xvciBm b3JtYXQuCj4gPiArCSAqIFhTRElSWF9SU1RfQ1RSTF9CUklER0VfQ0hfRk1UX1lVVjQ0NAo+ID4g KwkgKi8KPiA+ICsJaWYgKGVuYWJsZSkgewo+ID4gKwkJeHNkaXJ4c3Nfc2V0KHN0YXRlLCBYU0RJ UlhfUlNUX0NUUkxfUkVHLAo+ID4gKwkJCSAgICAgWFNESVJYX1JTVF9DVFJMX1ZJRElOX0FYSTRT X01PRF9FTkJfTUFTSyk7Cj4gPiArCQl4c2Rpcnhzc19zZXQoc3RhdGUsIFhTRElSWF9SU1RfQ1RS TF9SRUcsCj4gPiArCQkJICAgICBYU0RJUlhfUlNUX0NUUkxfU0RJUlhfQlJJREdFX0VOQl9NQVNL KTsKPiA+ICsJfSBlbHNlIHsKPiA+ICsJCXhzZGlyeHNzX2NscihzdGF0ZSwgWFNESVJYX1JTVF9D VFJMX1JFRywKPiA+ICsJCQkgICAgIFhTRElSWF9SU1RfQ1RSTF9TRElSWF9CUklER0VfRU5CX01B U0spOwo+ID4gKwkJeHNkaXJ4c3NfY2xyKHN0YXRlLCBYU0RJUlhfUlNUX0NUUkxfUkVHLAo+ID4g KwkJCSAgICAgWFNESVJYX1JTVF9DVFJMX1ZJRElOX0FYSTRTX01PRF9FTkJfTUFTSyk7Cj4gPiAr CX0KPiA+ICsJc3RhdGUtPnN0cmVhbWluZyA9IGVuYWJsZTsKPiA+ICt9Cj4gPiArCj4gPiArc3Rh dGljIHZvaWQgeHNkaXJ4c3NfZ2V0X2ZyYW1lcmF0ZShzdHJ1Y3QgdjRsMl9mcmFjdCAqZnJhbWVf aW50ZXJ2YWwsCj4gPiArCQkJCSAgIHUzMiBmcmFtZXJhdGUpCj4gPiArewo+ID4gKwlzd2l0Y2gg KGZyYW1lcmF0ZSkgewo+ID4gKwljYXNlIFhTRElSWF9UU19ERVRfU1RBVF9SQVRFXzIzXzk4SFo6 Cj4gPiArCQlmcmFtZV9pbnRlcnZhbC0+bnVtZXJhdG9yID0gMTAwMTsKPiA+ICsJCWZyYW1lX2lu dGVydmFsLT5kZW5vbWluYXRvciA9IDI0MDAwOwo+ID4gKwkJYnJlYWs7Cj4gPiArCWNhc2UgWFNE SVJYX1RTX0RFVF9TVEFUX1JBVEVfMjRIWjoKPiA+ICsJCWZyYW1lX2ludGVydmFsLT5udW1lcmF0 b3IgPSAxMDAwOwo+ID4gKwkJZnJhbWVfaW50ZXJ2YWwtPmRlbm9taW5hdG9yID0gMjQwMDA7Cj4g PiArCQlicmVhazsKPiA+ICsJY2FzZSBYU0RJUlhfVFNfREVUX1NUQVRfUkFURV8yNUhaOgo+ID4g KwkJZnJhbWVfaW50ZXJ2YWwtPm51bWVyYXRvciA9IDEwMDA7Cj4gPiArCQlmcmFtZV9pbnRlcnZh bC0+ZGVub21pbmF0b3IgPSAyNTAwMDsKPiA+ICsJCWJyZWFrOwo+ID4gKwljYXNlIFhTRElSWF9U U19ERVRfU1RBVF9SQVRFXzI5Xzk3SFo6Cj4gPiArCQlmcmFtZV9pbnRlcnZhbC0+bnVtZXJhdG9y ID0gMTAwMTsKPiA+ICsJCWZyYW1lX2ludGVydmFsLT5kZW5vbWluYXRvciA9IDMwMDAwOwo+ID4g KwkJYnJlYWs7Cj4gPiArCWNhc2UgWFNESVJYX1RTX0RFVF9TVEFUX1JBVEVfMzBIWjoKPiA+ICsJ CWZyYW1lX2ludGVydmFsLT5udW1lcmF0b3IgPSAxMDAwOwo+ID4gKwkJZnJhbWVfaW50ZXJ2YWwt PmRlbm9taW5hdG9yID0gMzAwMDA7Cj4gPiArCQlicmVhazsKPiA+ICsJY2FzZSBYU0RJUlhfVFNf REVUX1NUQVRfUkFURV80N185NUhaOgo+ID4gKwkJZnJhbWVfaW50ZXJ2YWwtPm51bWVyYXRvciA9 IDEwMDE7Cj4gPiArCQlmcmFtZV9pbnRlcnZhbC0+ZGVub21pbmF0b3IgPSA0ODAwMDsKPiA+ICsJ CWJyZWFrOwo+ID4gKwljYXNlIFhTRElSWF9UU19ERVRfU1RBVF9SQVRFXzQ4SFo6Cj4gPiArCQlm cmFtZV9pbnRlcnZhbC0+bnVtZXJhdG9yID0gMTAwMDsKPiA+ICsJCWZyYW1lX2ludGVydmFsLT5k ZW5vbWluYXRvciA9IDQ4MDAwOwo+ID4gKwkJYnJlYWs7Cj4gPiArCWNhc2UgWFNESVJYX1RTX0RF VF9TVEFUX1JBVEVfNTBIWjoKPiA+ICsJCWZyYW1lX2ludGVydmFsLT5udW1lcmF0b3IgPSAxMDAw Owo+ID4gKwkJZnJhbWVfaW50ZXJ2YWwtPmRlbm9taW5hdG9yID0gNTAwMDA7Cj4gPiArCQlicmVh azsKPiA+ICsJY2FzZSBYU0RJUlhfVFNfREVUX1NUQVRfUkFURV81OV85NEhaOgo+ID4gKwkJZnJh bWVfaW50ZXJ2YWwtPm51bWVyYXRvciA9IDEwMDE7Cj4gPiArCQlmcmFtZV9pbnRlcnZhbC0+ZGVu b21pbmF0b3IgPSA2MDAwMDsKPiA+ICsJCWJyZWFrOwo+ID4gKwljYXNlIFhTRElSWF9UU19ERVRf U1RBVF9SQVRFXzYwSFo6Cj4gPiArCQlmcmFtZV9pbnRlcnZhbC0+bnVtZXJhdG9yID0gMTAwMDsK PiA+ICsJCWZyYW1lX2ludGVydmFsLT5kZW5vbWluYXRvciA9IDYwMDAwOwo+ID4gKwkJYnJlYWs7 Cj4gPiArCWRlZmF1bHQ6Cj4gPiArCQlmcmFtZV9pbnRlcnZhbC0+bnVtZXJhdG9yID0gMTsKPiA+ ICsJCWZyYW1lX2ludGVydmFsLT5kZW5vbWluYXRvciA9IDE7Cj4gPiArCX0KPiA+ICt9Cj4gPiAr Cj4gPiArc3RhdGljIHZvaWQgeHNkaXJ4c3Nfc2V0X2d0Y2xrKHN0cnVjdCB4c2Rpcnhzc19zdGF0 ZSAqc3RhdGUpCj4gPiArewo+ID4gKwlzdHJ1Y3QgY2xrICpndGNsazsKPiA+ICsJdW5zaWduZWQg bG9uZyBjbGtyYXRlOwo+ID4gKwlpbnQgcmV0LCBpc19mcmFjOwo+ID4gKwl1MzIgbW9kZTsKPiA+ ICsKPiA+ICsJbW9kZSA9IHhzZGlyeHNzX3JlYWQoc3RhdGUsIFhTRElSWF9NT0RFX0RFVF9TVEFU X1JFRyk7Cj4gPiArCW1vZGUgJj0gWFNESVJYX01PREVfREVUX1NUQVRfUlhfTU9ERV9NQVNLOwo+ ID4gKwo+ID4gKwkvKgo+ID4gKwkgKiBUT0RPOiBGb3Igbm93LCBkb24ndCBjaGFuZ2UgdGhlIGNs b2NrIHJhdGUgZm9yIGFueSBtb2RlIGV4Y2VwdCAxMkcuCj4gPiArCSAqIEluIGZ1dHVyZSwgY29u ZmlndXJlIGd0IGNsb2NrIGZvciBhbGwgbW9kZXMgYW5kIGVuYWJsZSBjbG9jayBvbmx5Cj4gPiAr CSAqIHdoZW4gbmVlZGVkIChzdHJlYW0gb24vb2ZmKS4KPiA+ICsJICovCj4gPiArCWlmIChtb2Rl ICE9IFhTRElSWF9NT0RFXzEyR0lfTUFTSyAmJiBtb2RlICE9IFhTRElSWF9NT0RFXzEyR0ZfTUFT SykKPiA+ICsJCXJldHVybjsKPiA+ICsKPiA+ICsJLyogV2hlbiBudW1lcmF0b3IgaXMgMTAwMSB0 aGVuIGZyYW1lIHJhdGUgaXMgZnJhY3Rpb25hbCBlbHNlIGludGVnZXIgKi8KPiA+ICsJaXNfZnJh YyA9IHN0YXRlLT5mcmFtZV9pbnRlcnZhbC5udW1lcmF0b3IgPT0gMTAwMSA/IDEgOiAwOwo+ID4g Kwo+ID4gKwlpZiAoc3RhdGUtPnByZXZfaXNfZnJhYyA9PSBpc19mcmFjKQo+ID4gKwkJcmV0dXJu Owo+ID4gKwo+ID4gKwlYU0RJUlhfR0xPQkFMX0lOVFJfRElTQUJMRShzdGF0ZSk7Cj4gPiArCXhz ZGlyeHNzX2NscihzdGF0ZSwgWFNESVJYX0lFUl9SRUcsIFhTRElSWF9JTlRSX0FMTF9NQVNLKTsK PiA+ICsJWFNESVJYX0NPUkVfRElTQUJMRShzdGF0ZSk7Cj4gPiArCj4gPiArCS8qIGdldCBzZGlf cnhfY2xrICovCj4gPiArCWd0Y2xrID0gc3RhdGUtPmNsa3NbMV0uY2xrOwo+ID4gKwo+ID4gKwkv KiBjYWxjdWxhdGUgY2xrcmF0ZSAqLwo+ID4gKwlpZiAoIWlzX2ZyYWMpCj4gPiArCQljbGtyYXRl ID0gQ0xLX0lOVDsKPiA+ICsJZWxzZQo+ID4gKwkJY2xrcmF0ZSA9IChDTEtfSU5UICogMTAwMCkg LyAxMDAxOwo+ID4gKwo+ID4gKwlyZXQgPSBjbGtfc2V0X3JhdGUoZ3RjbGssIGNsa3JhdGUpOwoK VGhpcyBmdW5jdGlvbiBpcyBjYWxsZWQgZnJvbSB0aGUgSVJRIGhhbmRsZXIsIGFuZCB3aXRoIGEg c3BpbmxvY2sgaGVsZC4KY2xrX3NldF9yYXRlKCkgY2FuIHNsZWVwIGFzIHRoZSBjbG9jayBzb3Vy Y2UgY2FuIGJlIGFuIGV4dGVybmFsCkkyQy1jb250cm9sbGVkIGNoaXAuIEhhdmUgeW91IHRlc3Rl ZCB0aGlzIGNvZGUgcGF0aCA/IEkgdGhpbmsgdGFraW5nIHRoZQpzcGlubG9jayBhdCB0b3AgbGV2 ZWwgbG9jYXRpb25zIHdpbGwgbmVlZCB0byBiZSByZWNvbnNpZGVyZWQuCgo+ID4gKwlpZiAocmV0 KQo+ID4gKwkJZGV2X2VycihzdGF0ZS0+ZGV2LCAiZmFpbGVkIHRvIHNldCBjbGsgcmF0ZSA9ICVk XG4iLCByZXQpOwo+ID4gKwo+ID4gKwlzdGF0ZS0+cHJldl9pc19mcmFjID0gaXNfZnJhYzsKPiA+ ICsJY2xrcmF0ZSA9IGNsa19nZXRfcmF0ZShndGNsayk7Cj4gPiArCj4gPiArCWRldl9kYmcoc3Rh dGUtPmRldiwgImNsa3JhdGUgPSAlbHUgaXNfZnJhYyA9ICVkXG4iLAo+ID4gKwkJY2xrcmF0ZSwg aXNfZnJhYyk7Cj4gPiArCj4gPiArCWlmIChzdGF0ZS0+ZnJhbWVyX2VuYWJsZSkgewo+ID4gKwkJ eHNkaXJ4c3Nfc2V0KHN0YXRlLCBYU0RJUlhfTURMX0NUUkxfUkVHLAo+ID4gKwkJCSAgICAgWFNE SVJYX01ETF9DVFJMX0ZSTV9FTl9NQVNLKTsKPiA+ICsJfSBlbHNlIHsKPiA+ICsJCXhzZGlyeHNz X2NscihzdGF0ZSwgWFNESVJYX01ETF9DVFJMX1JFRywKPiA+ICsJCQkgICAgIFhTRElSWF9NRExf Q1RSTF9GUk1fRU5fTUFTSyk7Cj4gPiArCX0KCk5vIG5lZWQgZm9yIGJyYWNlcy4KCj4gPiArCXhz ZGlyeHNzX3dyaXRlKHN0YXRlLCBYU0RJUlhfRURIX0VSUkNOVF9FTl9SRUcsCj4gPiArCQkgICAg ICAgc3RhdGUtPmVkaG1hc2sgJiBYU0RJUlhfRURIX0FMTEVSUl9NQVNLKTsKPiA+ICsJeHNkaXJ4 c3Nfd3JpdGUoc3RhdGUsIFhTRElSWF9WSURfTE9DS19XSU5ET1dfUkVHLCBzdGF0ZS0+dmlkbG9j a2VkKTsKPiA+ICsJeHNkaXJ4X3NldF9tb2RlZGV0ZWN0KHN0YXRlLCBzdGF0ZS0+c2VhcmNobWFz ayk7Cj4gPiArCVhTRElSWF9DT1JFX0VOQUJMRShzdGF0ZSk7Cj4gPiArCXhzZGlyeHNzX3NldChz dGF0ZSwgWFNESVJYX0lFUl9SRUcsIFhTRElSWF9JTlRSX0FMTF9NQVNLKTsKPiA+ICsJWFNESVJY X0dMT0JBTF9JTlRSX0VOQUJMRShzdGF0ZSk7Cj4gPiArfQo+ID4gKwo+ID4gKy8qKgo+ID4gKyAq IHhzZGlyeF9nZXRfc3RyZWFtX3Byb3BlcnRpZXMgLSBHZXQgU0RJIFJ4IHN0cmVhbSBwcm9wZXJ0 aWVzCj4gPiArICogQHN0YXRlOiBwb2ludGVyIHRvIGRyaXZlciBzdGF0ZQo+ID4gKyAqCj4gPiAr ICogVGhpcyBmdW5jdGlvbiBkZWNvZGVzIHRoZSBzdHJlYW0ncyBTVDM1MiBwYXlsb2FkIChpZiBh dmFpbGFibGUpIHRvIGdldAo+ID4gKyAqIHN0cmVhbSBwcm9wZXJ0aWVzIGxpa2Ugd2lkdGgsIGhl aWdodCwgcGljdHVyZSB0eXBlIChpbnRlcmxhY2VkL3Byb2dyZXNzaXZlKSwKPiA+ICsgKiBldGMu Cj4gPiArICoKPiA+ICsgKiBSZXR1cm46IDAgZm9yIHN1Y2Nlc3MgZWxzZSBlcnJvcnMKPiA+ICsg Ki8KPiA+ICtzdGF0aWMgaW50IHhzZGlyeF9nZXRfc3RyZWFtX3Byb3BlcnRpZXMoc3RydWN0IHhz ZGlyeHNzX3N0YXRlICpzdGF0ZSkKPiA+ICt7Cj4gPiArCXN0cnVjdCBkZXZpY2UgKmRldiA9IHN0 YXRlLT5kZXY7Cj4gPiArCXUzMiBtb2RlLCBwYXlsb2FkID0gMCwgdmFsLCBmYW1pbHksIHZhbGlk LCB0c2NhbjsKPiA+ICsJdTggYnl0ZTEgPSAwLCBhY3RpdmVfbHVtYSA9IDAsIHBpY190eXBlID0g MCwgZnJhbWVyYXRlID0gMDsKPiA+ICsJdTggc2FtcGxpbmcgPSBYU1QzNTJfQllURTNfQ09MT1Jf Rk9STUFUXzQyMjsKPiA+ICsJc3RydWN0IHY0bDJfbWJ1c19mcmFtZWZtdCAqZm9ybWF0ID0gJnN0 YXRlLT5mb3JtYXQ7Cj4gPiArCXUzMiBicGMgPSBYU1QzNTJfQllURTRfQklUX0RFUFRIXzEwOwo+ ID4gKwl1MzIgY29sb3JpbWV0cnkgPSBYU1QzNTJfQllURTNfQ09MT1JJTUVUUllfQlQ3MDk7Cj4g PiArCj4gPiArCW1vZGUgPSB4c2Rpcnhzc19yZWFkKHN0YXRlLCBYU0RJUlhfTU9ERV9ERVRfU1RB VF9SRUcpOwo+ID4gKwltb2RlICY9IFhTRElSWF9NT0RFX0RFVF9TVEFUX1JYX01PREVfTUFTSzsK PiA+ICsKPiA+ICsJdmFsaWQgPSB4c2Rpcnhzc19yZWFkKHN0YXRlLCBYU0RJUlhfU1QzNTJfVkFM SURfUkVHKTsKPiA+ICsKPiA+ICsJaWYgKG1vZGUgPj0gWFNESVJYX01PREVfM0dfTUFTSyAmJiAh dmFsaWQpIHsKPiA+ICsJCWRldl9lcnIoZGV2LCAiTm8gdmFsaWQgU1QzNTIgcGF5bG9hZCBwcmVz ZW50IGV2ZW4gZm9yIDNHIG1vZGUgYW5kIGFib3ZlXG4iKTsKPiA+ICsJCXJldHVybiAtRUlOVkFM Owo+ID4gKwl9Cj4gPiArCj4gPiArCXZhbCA9IHhzZGlyeHNzX3JlYWQoc3RhdGUsIFhTRElSWF9U U19ERVRfU1RBVF9SRUcpOwo+ID4gKwlpZiAodmFsaWQgJiBYU0RJUlhfU1QzNTJfVkFMSURfRFMx X01BU0spIHsKPiA+ICsJCXBheWxvYWQgPSB4c2Rpcnhzc19yZWFkKHN0YXRlLCBYU0RJUlhfU1Qz NTJfRFMxX1JFRyk7Cj4gPiArCQlieXRlMSA9IEZJRUxEX0dFVChYU1QzNTJfUEFZTE9BRF9CWVRF MV9NQVNLLCBwYXlsb2FkKTsKPiA+ICsJCWFjdGl2ZV9sdW1hID0gRklFTERfR0VUKFhTVDM1Ml9C WVRFM19BQ1RfTFVNQV9DT1VOVF9NQVNLLAo+ID4gKwkJCQkJcGF5bG9hZCk7Cj4gPiArCQlwaWNf dHlwZSA9IEZJRUxEX0dFVChYU1QzNTJfQllURTJfUElDX1RZUEVfTUFTSywgcGF5bG9hZCk7Cj4g PiArCQlmcmFtZXJhdGUgPSBGSUVMRF9HRVQoWFNUMzUyX0JZVEUyX0ZQU19NQVNLLCBwYXlsb2Fk KTsKPiA+ICsJCXRzY2FuID0gRklFTERfR0VUKFhTVDM1Ml9CWVRFMl9UU19UWVBFX01BU0ssIHBh eWxvYWQpOwo+ID4gKwkJc2FtcGxpbmcgPSBGSUVMRF9HRVQoWFNUMzUyX0JZVEUzX0NPTE9SX0ZP Uk1BVF9NQVNLLCBwYXlsb2FkKTsKPiA+ICsJCWJwYyA9IEZJRUxEX0dFVChYU1QzNTJfQllURTRf QklUX0RFUFRIX01BU0ssIHBheWxvYWQpOwo+ID4gKwkJY29sb3JpbWV0cnkgPSBGSUVMRF9HRVQo WFNUMzUyX0JZVEUzX0NPTE9SSU1FVFJZX01BU0ssIHBheWxvYWQpOwo+ID4gKwl9IGVsc2Ugewo+ ID4gKwkJZGV2X2RiZyhkZXYsICJObyBTVDM1MiBwYXlsb2FkIGF2YWlsYWJsZSA6IE1vZGUgPSAl ZFxuIiwgbW9kZSk7Cj4gPiArCQlmcmFtZXJhdGUgPSBGSUVMRF9HRVQoWFNESVJYX1RTX0RFVF9T VEFUX1JBVEVfTUFTSywgdmFsKTsKPiA+ICsJCXRzY2FuID0gRklFTERfR0VUKFhTRElSWF9UU19E RVRfU1RBVF9TQ0FOX01BU0ssIHZhbCk7Cj4gPiArCX0KPiA+ICsKPiA+ICsJaWYgKChicGMgPT0g WFNUMzUyX0JZVEU0X0JJVF9ERVBUSF8xMCAmJiBzdGF0ZS0+YnBjICE9IDEwKSB8fAo+ID4gKwkg ICAgKGJwYyA9PSBYU1QzNTJfQllURTRfQklUX0RFUFRIXzEyICYmIHN0YXRlLT5icGMgIT0gMTIp KSB7Cj4gPiArCQlkZXZfZGJnKGRldiwgIkJpdCBkZXB0aCBub3Qgc3VwcG9ydGVkLiBicGMgPSAl ZCBzdGF0ZS0+YnBjID0gJWRcbiIsCj4gPiArCQkJYnBjLCBzdGF0ZS0+YnBjKTsKPiA+ICsJCXJl dHVybiAtRUlOVkFMOwo+ID4gKwl9Cj4gPiArCj4gPiArCWZhbWlseSA9IEZJRUxEX0dFVChYU0RJ UlhfVFNfREVUX1NUQVRfRkFNSUxZX01BU0ssIHZhbCk7Cj4gPiArCXN0YXRlLT50c19pc19pbnRl cmxhY2VkID0gdHNjYW4gPyBmYWxzZSA6IHRydWU7Cj4gPiArCj4gPiArCWRldl9kYmcoZGV2LCAi dHNfaXNfaW50ZXJsYWNlZCA9ICVkLCBmYW1pbHkgPSAlZFxuIiwKPiA+ICsJCXN0YXRlLT50c19p c19pbnRlcmxhY2VkLCBmYW1pbHkpOwo+ID4gKwo+ID4gKwlzd2l0Y2ggKG1vZGUpIHsKPiA+ICsJ Y2FzZSBYU0RJUlhfTU9ERV9IRF9NQVNLOgo+ID4gKwkJaWYgKCF2YWxpZCkgewo+ID4gKwkJCS8q IE5vIHBheWxvYWQgb2J0YWluZWQgKi8KPiA+ICsJCQlkZXZfZGJnKGRldiwgImZyYW1lIHJhdGUg OiAlZCwgdHNjYW4gPSAlZFxuIiwKPiA+ICsJCQkJZnJhbWVyYXRlLCB0c2Nhbik7Cj4gPiArCQkJ LyoKPiA+ICsJCQkgKiBOT1RFIDogQSBwcm9ncmVzc2l2ZSBzZWdtZW50ZWQgZnJhbWUgcFNGIHdp bGwgYmUKPiA+ICsJCQkgKiByZXBvcnRlZCBpbmNvcnJlY3RseSBhcyBJbnRlcmxhY2VkIGFzIHdl IHJlbHkgb24gSVAncwo+ID4gKwkJCSAqIHRyYW5zcG9ydCBzY2FuIGxvY2tlZCBiaXQuCj4gPiAr CQkJICovCj4gPiArCQkJZGV2X3dhcm4oZGV2LCAicFNGIHdpbGwgYmUgaW5jb3JyZWN0bHkgcmVw b3J0ZWQgYXMgSW50ZXJsYWNlZFxuIik7Cj4gPiArCj4gPiArCQkJc3dpdGNoIChmcmFtZXJhdGUp IHsKPiA+ICsJCQljYXNlIFhTRElSWF9UU19ERVRfU1RBVF9SQVRFXzIzXzk4SFo6Cj4gPiArCQkJ Y2FzZSBYU0RJUlhfVFNfREVUX1NUQVRfUkFURV8yNEhaOgo+ID4gKwkJCWNhc2UgWFNESVJYX1RT X0RFVF9TVEFUX1JBVEVfMjVIWjoKPiA+ICsJCQljYXNlIFhTRElSWF9UU19ERVRfU1RBVF9SQVRF XzI5Xzk3SFo6Cj4gPiArCQkJY2FzZSBYU0RJUlhfVFNfREVUX1NUQVRfUkFURV8zMEhaOgo+ID4g KwkJCQlpZiAoZmFtaWx5ID09IFhTRElSWF9TTVBURV9TVF8yOTYpIHsKPiA+ICsJCQkJCWZvcm1h dC0+d2lkdGggPSAxMjgwOwo+ID4gKwkJCQkJZm9ybWF0LT5oZWlnaHQgPSA3MjA7Cj4gPiArCQkJ CQlmb3JtYXQtPmZpZWxkID0gVjRMMl9GSUVMRF9OT05FOwo+ID4gKwkJCQl9IGVsc2UgaWYgKGZh bWlseSA9PSBYU0RJUlhfU01QVEVfU1RfMjA0OF8yKSB7Cj4gPiArCQkJCQlmb3JtYXQtPndpZHRo ID0gMjA0ODsKPiA+ICsJCQkJCWZvcm1hdC0+aGVpZ2h0ID0gMTA4MDsKPiA+ICsJCQkJCWlmICh0 c2NhbikKPiA+ICsJCQkJCQlmb3JtYXQtPmZpZWxkID0gVjRMMl9GSUVMRF9OT05FOwo+ID4gKwkJ CQkJZWxzZQo+ID4gKwkJCQkJCWZvcm1hdC0+ZmllbGQgPQo+ID4gKwkJCQkJCQlWNEwyX0ZJRUxE X0FMVEVSTkFURTsKPiA+ICsJCQkJfSBlbHNlIHsKPiA+ICsJCQkJCWZvcm1hdC0+d2lkdGggPSAx OTIwOwo+ID4gKwkJCQkJZm9ybWF0LT5oZWlnaHQgPSAxMDgwOwo+ID4gKwkJCQkJaWYgKHRzY2Fu KQo+ID4gKwkJCQkJCWZvcm1hdC0+ZmllbGQgPSBWNEwyX0ZJRUxEX05PTkU7Cj4gPiArCQkJCQll bHNlCj4gPiArCQkJCQkJZm9ybWF0LT5maWVsZCA9Cj4gPiArCQkJCQkJCVY0TDJfRklFTERfQUxU RVJOQVRFOwo+ID4gKwkJCQl9Cj4gPiArCQkJCWJyZWFrOwo+ID4gKwkJCWNhc2UgWFNESVJYX1RT X0RFVF9TVEFUX1JBVEVfNTBIWjoKPiA+ICsJCQljYXNlIFhTRElSWF9UU19ERVRfU1RBVF9SQVRF XzU5Xzk0SFo6Cj4gPiArCQkJY2FzZSBYU0RJUlhfVFNfREVUX1NUQVRfUkFURV82MEhaOgo+ID4g KwkJCQlpZiAoZmFtaWx5ID09IFhTRElSWF9TTVBURV9TVF8yNzQpIHsKPiA+ICsJCQkJCWZvcm1h dC0+d2lkdGggPSAxOTIwOwo+ID4gKwkJCQkJZm9ybWF0LT5oZWlnaHQgPSAxMDgwOwo+ID4gKwkJ CQl9IGVsc2Ugewo+ID4gKwkJCQkJZm9ybWF0LT53aWR0aCA9IDEyODA7Cj4gPiArCQkJCQlmb3Jt YXQtPmhlaWdodCA9IDcyMDsKPiA+ICsJCQkJfQo+ID4gKwkJCQlmb3JtYXQtPmZpZWxkID0gVjRM Ml9GSUVMRF9OT05FOwo+ID4gKwkJCQlicmVhazsKPiA+ICsJCQlkZWZhdWx0Ogo+ID4gKwkJCQlm b3JtYXQtPndpZHRoID0gMTkyMDsKPiA+ICsJCQkJZm9ybWF0LT5oZWlnaHQgPSAxMDgwOwo+ID4g KwkJCQlmb3JtYXQtPmZpZWxkID0gVjRMMl9GSUVMRF9OT05FOwo+ID4gKwkJCX0KPiA+ICsJCX0g ZWxzZSB7Cj4gPiArCQkJZGV2X2RiZyhkZXYsICJHb3QgdGhlIHBheWxvYWRcbiIpOwo+ID4gKwkJ CXN3aXRjaCAoYnl0ZTEpIHsKPiA+ICsJCQljYXNlIFhTVDM1Ml9CWVRFMV9TVDI5Ml8xeDcyMExf MV81RzoKPiA+ICsJCQkJLyogU01QVEUgU1QgMjkyLTEgZm9yIDcyMCBsaW5lIHBheWxvYWRzICov Cj4gPiArCQkJCWZvcm1hdC0+d2lkdGggPSAxMjgwOwo+ID4gKwkJCQlmb3JtYXQtPmhlaWdodCA9 IDcyMDsKPiA+ICsJCQkJYnJlYWs7Cj4gPiArCQkJY2FzZSBYU1QzNTJfQllURTFfU1QyOTJfMXgx MDgwTF8xXzVHOgo+ID4gKwkJCQkvKiBTTVBURSBTVCAyOTItMSBmb3IgMTA4MCBsaW5lIHBheWxv YWRzICovCj4gPiArCQkJCWZvcm1hdC0+aGVpZ2h0ID0gMTA4MDsKPiA+ICsJCQkJaWYgKGFjdGl2 ZV9sdW1hKQo+ID4gKwkJCQkJZm9ybWF0LT53aWR0aCA9IDIwNDg7Cj4gPiArCQkJCWVsc2UKPiA+ ICsJCQkJCWZvcm1hdC0+d2lkdGggPSAxOTIwOwo+ID4gKwkJCQlicmVhazsKPiA+ICsJCQlkZWZh dWx0Ogo+ID4gKwkJCQlkZXZfZGJnKGRldiwgIlVua25vd24gSEQgTW9kZSBTTVBURSBzdGFuZGFy ZFxuIik7Cj4gPiArCQkJCXJldHVybiAtRUlOVkFMOwo+ID4gKwkJCX0KPiA+ICsJCX0KPiA+ICsJ CWJyZWFrOwo+ID4gKwljYXNlIFhTRElSWF9NT0RFX1NEX01BU0s6Cj4gPiArCQlmb3JtYXQtPmZp ZWxkID0gVjRMMl9GSUVMRF9BTFRFUk5BVEU7Cj4gPiArCj4gPiArCQlzd2l0Y2ggKGZhbWlseSkg ewo+ID4gKwkJY2FzZSBYU0RJUlhfTlRTQzoKPiA+ICsJCQlmb3JtYXQtPndpZHRoID0gNzIwOwo+ ID4gKwkJCWZvcm1hdC0+aGVpZ2h0ID0gNDg2Owo+ID4gKwkJCWJyZWFrOwo+ID4gKwkJY2FzZSBY U0RJUlhfUEFMOgo+ID4gKwkJCWZvcm1hdC0+d2lkdGggPSA3MjA7Cj4gPiArCQkJZm9ybWF0LT5o ZWlnaHQgPSA1NzY7Cj4gPiArCQkJYnJlYWs7Cj4gPiArCQlkZWZhdWx0Ogo+ID4gKwkJCWRldl9k YmcoZGV2LCAiVW5rbm93biBTRCBNb2RlIFNNUFRFIHN0YW5kYXJkXG4iKTsKPiA+ICsJCQlyZXR1 cm4gLUVJTlZBTDsKPiA+ICsJCX0KPiA+ICsJCWJyZWFrOwo+ID4gKwljYXNlIFhTRElSWF9NT0RF XzNHX01BU0s6Cj4gPiArCQlzd2l0Y2ggKGJ5dGUxKSB7Cj4gPiArCQljYXNlIFhTVDM1Ml9CWVRF MV9TVDQyNV8yMDA4Xzc1MExfM0dCOgo+ID4gKwkJCS8qIFNlYyA0LjEuNi4xIFNNUFRFIDQyNS0y MDA4ICovCj4gPiArCQljYXNlIFhTVDM1Ml9CWVRFMV9TVDM3Ml8yeDcyMExfM0dCOgo+ID4gKwkJ CS8qIFRhYmxlIDEzIFNNUFRFIDQyNS0yMDA4ICovCj4gPiArCQkJZm9ybWF0LT53aWR0aCA9IDEy ODA7Cj4gPiArCQkJZm9ybWF0LT5oZWlnaHQgPSA3MjA7Cj4gPiArCQkJYnJlYWs7Cj4gPiArCQlj YXNlIFhTVDM1Ml9CWVRFMV9TVDQyNV8yMDA4XzExMjVMXzNHQToKPiA+ICsJCQkvKiBTVDM1MiBU YWJsZSBTTVBURSA0MjUtMSAqLwo+ID4gKwkJY2FzZSBYU1QzNTJfQllURTFfU1QzNzJfRExfM0dC Ogo+ID4gKwkJCS8qIFRhYmxlIDEzIFNNUFRFIDQyNS0yMDA4ICovCj4gPiArCQljYXNlIFhTVDM1 Ml9CWVRFMV9TVDM3Ml8yeDEwODBMXzNHQjoKPiA+ICsJCQkvKiBUYWJsZSAxMyBTTVBURSA0MjUt MjAwOCAqLwo+ID4gKwkJCWZvcm1hdC0+aGVpZ2h0ID0gMTA4MDsKPiA+ICsJCQlpZiAoYWN0aXZl X2x1bWEpCj4gPiArCQkJCWZvcm1hdC0+d2lkdGggPSAyMDQ4Owo+ID4gKwkJCWVsc2UKPiA+ICsJ CQkJZm9ybWF0LT53aWR0aCA9IDE5MjA7Cj4gPiArCQkJYnJlYWs7Cj4gPiArCQlkZWZhdWx0Ogo+ ID4gKwkJCWRldl9kYmcoZGV2LCAiVW5rbm93biAzRyBNb2RlIFNNUFRFIHN0YW5kYXJkXG4iKTsK PiA+ICsJCQlyZXR1cm4gLUVJTlZBTDsKPiA+ICsJCX0KPiA+ICsJCWJyZWFrOwo+ID4gKwljYXNl IFhTRElSWF9NT0RFXzZHX01BU0s6Cj4gPiArCQlzd2l0Y2ggKGJ5dGUxKSB7Cj4gPiArCQljYXNl IFhTVDM1Ml9CWVRFMV9TVDIwODFfMTBfRExfMjE2MExfNkc6Cj4gPiArCQkJLyogRHVhbCBsaW5r IDZHICovCj4gPiArCQljYXNlIFhTVDM1Ml9CWVRFMV9TVDIwODFfMTBfMjE2MExfNkc6Cj4gPiAr CQkJLyogVGFibGUgMyBTTVBURSBTVCAyMDgxLTEwICovCj4gPiArCQkJZm9ybWF0LT5oZWlnaHQg PSAyMTYwOwo+ID4gKwkJCWlmIChhY3RpdmVfbHVtYSkKPiA+ICsJCQkJZm9ybWF0LT53aWR0aCA9 IDQwOTY7Cj4gPiArCQkJZWxzZQo+ID4gKwkJCQlmb3JtYXQtPndpZHRoID0gMzg0MDsKPiA+ICsJ CQlicmVhazsKPiA+ICsJCWNhc2UgWFNUMzUyX0JZVEUxX1NUMjA4MV8xMF8yXzEwODBMXzZHOgo+ ID4gKwkJCWZvcm1hdC0+aGVpZ2h0ID0gMTA4MDsKPiA+ICsJCQlpZiAoYWN0aXZlX2x1bWEpCj4g PiArCQkJCWZvcm1hdC0+d2lkdGggPSAyMDQ4Owo+ID4gKwkJCWVsc2UKPiA+ICsJCQkJZm9ybWF0 LT53aWR0aCA9IDE5MjA7Cj4gPiArCQkJYnJlYWs7Cj4gPiArCQlkZWZhdWx0Ogo+ID4gKwkJCWRl dl9kYmcoZGV2LCAiVW5rbm93biA2RyBNb2RlIFNNUFRFIHN0YW5kYXJkXG4iKTsKPiA+ICsJCQly ZXR1cm4gLUVJTlZBTDsKPiA+ICsJCX0KPiA+ICsJCWJyZWFrOwo+ID4gKwljYXNlIFhTRElSWF9N T0RFXzEyR0lfTUFTSzoKPiA+ICsJY2FzZSBYU0RJUlhfTU9ERV8xMkdGX01BU0s6Cj4gPiArCQlz d2l0Y2ggKGJ5dGUxKSB7Cj4gPiArCQljYXNlIFhTVDM1Ml9CWVRFMV9TVDIwODJfMTBfMjE2MExf MTJHOgo+ID4gKwkJCS8qIFNlY3Rpb24gNC4zLjEgU01QVEUgU1QgMjA4Mi0xMCAqLwo+ID4gKwkJ CWZvcm1hdC0+aGVpZ2h0ID0gMjE2MDsKPiA+ICsJCQlpZiAoYWN0aXZlX2x1bWEpCj4gPiArCQkJ CWZvcm1hdC0+d2lkdGggPSA0MDk2Owo+ID4gKwkJCWVsc2UKPiA+ICsJCQkJZm9ybWF0LT53aWR0 aCA9IDM4NDA7Cj4gPiArCQkJYnJlYWs7Cj4gPiArCQlkZWZhdWx0Ogo+ID4gKwkJCWRldl9kYmco ZGV2LCAiVW5rbm93biAxMkcgTW9kZSBTTVBURSBzdGFuZGFyZFxuIik7Cj4gPiArCQkJcmV0dXJu IC1FSU5WQUw7Cj4gPiArCQl9Cj4gPiArCQlicmVhazsKPiA+ICsJZGVmYXVsdDoKPiA+ICsJCWRl dl9lcnIoZGV2LCAiSW52YWxpZCBNb2RlXG4iKTsKPiA+ICsJCXJldHVybiAtRUlOVkFMOwo+ID4g Kwl9Cj4gPiArCj4gPiArCWlmICh2YWxpZCkgewo+ID4gKwkJaWYgKHBpY190eXBlKQo+ID4gKwkJ CWZvcm1hdC0+ZmllbGQgPSBWNEwyX0ZJRUxEX05PTkU7Cj4gPiArCQllbHNlCj4gPiArCQkJZm9y bWF0LT5maWVsZCA9IFY0TDJfRklFTERfQUxURVJOQVRFOwo+ID4gKwo+ID4gKwkJaWYgKGZvcm1h dC0+aGVpZ2h0ID09IDEwODAgJiYgcGljX3R5cGUgJiYgIXRzY2FuKQo+ID4gKwkJCWZvcm1hdC0+ ZmllbGQgPSBWNEwyX0ZJRUxEX0FMVEVSTkFURTsKPiA+ICsKPiA+ICsJCS8qCj4gPiArCQkgKiBJ biAzR0IgREwgcFNGIG1vZGUgdGhlIHZpZGVvIGlzIHNpbWlsYXIgdG8gaW50ZXJsYWNlZC4KPiA+ ICsJCSAqIFNvIHRob3VnaCBpdCBpcyBhIHByb2dyZXNzaXZlIHZpZGVvLCBpdHMgdHJhbnNwb3J0 IGlzCj4gPiArCQkgKiBpbnRlcmxhY2VkIGFuZCBpcyBzZW50IGFzIHR3byB3aWR0aCB4IChoZWln aHQvMikgYnVmZmVycy4KPiA+ICsJCSAqLwo+ID4gKwkJaWYgKGJ5dGUxID09IFhTVDM1Ml9CWVRF MV9TVDM3Ml9ETF8zR0IpIHsKPiA+ICsJCQlpZiAoc3RhdGUtPnRzX2lzX2ludGVybGFjZWQpCj4g PiArCQkJCWZvcm1hdC0+ZmllbGQgPSBWNEwyX0ZJRUxEX0FMVEVSTkFURTsKPiA+ICsJCQllbHNl Cj4gPiArCQkJCWZvcm1hdC0+ZmllbGQgPSBWNEwyX0ZJRUxEX05PTkU7Cj4gPiArCQl9Cj4gPiAr CX0KPiA+ICsKPiA+ICsJaWYgKGZvcm1hdC0+ZmllbGQgPT0gVjRMMl9GSUVMRF9BTFRFUk5BVEUp Cj4gPiArCQlmb3JtYXQtPmhlaWdodCA9IGZvcm1hdC0+aGVpZ2h0IC8gMjsKPiA+ICsKPiA+ICsJ c3dpdGNoIChzYW1wbGluZykgewo+ID4gKwljYXNlIFhTVDM1Ml9CWVRFM19DT0xPUl9GT1JNQVRf NDIyOgo+ID4gKwkJaWYgKHN0YXRlLT5icGMgPT0gMTApCj4gPiArCQkJZm9ybWF0LT5jb2RlID0g TUVESUFfQlVTX0ZNVF9VWVZZMTBfMVgyMDsKPiA+ICsJCWVsc2UKPiA+ICsJCQlmb3JtYXQtPmNv ZGUgPSBNRURJQV9CVVNfRk1UX1VZVlkxMl8xWDI0Owo+ID4gKwkJYnJlYWs7Cj4gPiArCWNhc2Ug WFNUMzUyX0JZVEUzX0NPTE9SX0ZPUk1BVF80MjA6Cj4gPiArCWNhc2UgWFNUMzUyX0JZVEUzX0NP TE9SX0ZPUk1BVF9ZVVY0NDQ6Cj4gPiArCWNhc2UgWFNUMzUyX0JZVEUzX0NPTE9SX0ZPUk1BVF9H QlI6Cj4gPiArCQlmb3JtYXQtPmNvZGUgPSAwOwo+ID4gKwkJZGV2X2RiZyhkZXYsICJObyBjb3Jy ZXNwb25kaW5nIG1lZGlhIGJ1cyBmb3JtYXRzXG4iKTsKPiA+ICsJCWJyZWFrOwo+ID4gKwlkZWZh dWx0Ogo+ID4gKwkJZGV2X2VycihkZXYsICJVbnN1cHBvcnRlZCBjb2xvciBmb3JtYXQgOiAlZFxu Iiwgc2FtcGxpbmcpOwo+ID4gKwkJcmV0dXJuIC1FSU5WQUw7Cj4gPiArCX0KPiA+ICsKPiA+ICsJ LyogUmVmZXIgVGFibGUgMyBTTVBURSBTVCAyMDgxLTEwOjIwMTggKi8KPiA+ICsJc3dpdGNoIChj b2xvcmltZXRyeSkgewo+ID4gKwljYXNlIFhTVDM1Ml9CWVRFM19DT0xPUklNRVRSWV9CVDcwOToK PiA+ICsJCWZvcm1hdC0+Y29sb3JzcGFjZSA9IFY0TDJfQ09MT1JTUEFDRV9SRUM3MDk7Cj4gPiAr CQlicmVhazsKPiA+ICsJLyogV2hlbiBIRFIgc3VwcG9ydCBpcyBhZGRlZCBVSERUViB3aWxsIGhh dmUgQlQyMDIwIGNvbG9yc3BhY2UgKi8KPiA+ICsJY2FzZSBYU1QzNTJfQllURTNfQ09MT1JJTUVU UllfVUhEVFY6Cj4gPiArCWNhc2UgWFNUMzUyX0JZVEUzX0NPTE9SSU1FVFJZX0NPTE9SX1ZBTkM6 Cj4gPiArCWNhc2UgWFNUMzUyX0JZVEUzX0NPTE9SSU1FVFJZX1VOS05PV046Cj4gPiArCWRlZmF1 bHQ6Cj4gPiArCQlkZXZfZXJyKGRldiwgIlVua25vd24gY29sb3JpbWV0cnkgOiAlZFxuIiwgY29s b3JpbWV0cnkpOwo+IAo+IEknbSBhIGJpdCBzdXJwcmlzZWQuIEkgd291bGQgZXhwZWN0IHRoYXQg U0RUViBvdmVyIFNESSB3b3VsZCB1c2UKPiBWNEwyX0NPTE9SU1BBQ0VfU01QVEUxNzBNLCBidXQg SSBkb24ndCBzZWUgdGhhdCBoZXJlLgo+IAo+ID4gKwkJcmV0dXJuIC1FSU5WQUw7Cj4gPiArCX0K PiA+ICsKPiA+ICsJeHNkaXJ4c3NfZ2V0X2ZyYW1lcmF0ZSgmc3RhdGUtPmZyYW1lX2ludGVydmFs LCBmcmFtZXJhdGUpOwo+ID4gKwo+ID4gKwlkZXZfZGJnKGRldiwgIlN0cmVhbSB3aWR0aCA9ICVk IGhlaWdodCA9ICVkIEZpZWxkID0gJWQgcGF5bG9hZCA9IDB4JTA4eCB0cyA9IDB4JTA4eFxuIiwK PiA+ICsJCWZvcm1hdC0+d2lkdGgsIGZvcm1hdC0+aGVpZ2h0LCBmb3JtYXQtPmZpZWxkLCBwYXls b2FkLCB2YWwpOwo+ID4gKwlkZXZfZGJnKGRldiwgImZyYW1lIHJhdGUgbnVtZXJhdG9yID0gJWQg ZGVub21pbmF0b3IgPSAlZFxuIiwKPiA+ICsJCXN0YXRlLT5mcmFtZV9pbnRlcnZhbC5udW1lcmF0 b3IsCj4gPiArCQlzdGF0ZS0+ZnJhbWVfaW50ZXJ2YWwuZGVub21pbmF0b3IpOwo+ID4gKwlkZXZf ZGJnKGRldiwgIlN0cmVhbSBjb2RlID0gMHgleFxuIiwgZm9ybWF0LT5jb2RlKTsKPiA+ICsJcmV0 dXJuIDA7Cj4gPiArfQo+ID4gKwo+ID4gKy8qKgo+ID4gKyAqIHhzZGlyeHNzX2lycV9oYW5kbGVy IC0gSW50ZXJydXB0IGhhbmRsZXIgZm9yIFNESSBSeAo+ID4gKyAqIEBpcnE6IElSUSBudW1iZXIK PiA+ICsgKiBAZGV2X2lkOiBQb2ludGVyIHRvIGRldmljZSBzdGF0ZQo+ID4gKyAqCj4gPiArICog VGhlIFNESSBSeCBpbnRlcnJ1cHRzIGFyZSBjbGVhcmVkIGJ5IHdyaXRpbmcgMSB0byBjb3JyZXNw b25kaW5nIGJpdC4KPiA+ICsgKgo+ID4gKyAqIFJldHVybjogSVJRX0hBTkRMRUQgYWZ0ZXIgaGFu ZGxpbmcgaW50ZXJydXB0cwo+ID4gKyAqLwo+ID4gK3N0YXRpYyBpcnFyZXR1cm5fdCB4c2Rpcnhz c19pcnFfaGFuZGxlcihpbnQgaXJxLCB2b2lkICpkZXZfaWQpCj4gPiArewo+ID4gKwlzdHJ1Y3Qg eHNkaXJ4c3Nfc3RhdGUgKnN0YXRlID0gKHN0cnVjdCB4c2Rpcnhzc19zdGF0ZSAqKWRldl9pZDsK PiA+ICsJc3RydWN0IGRldmljZSAqZGV2ID0gc3RhdGUtPmRldjsKPiA+ICsJdTMyIHN0YXR1czsK PiA+ICsKPiA+ICsJc3RhdHVzID0geHNkaXJ4c3NfcmVhZChzdGF0ZSwgWFNESVJYX0lTUl9SRUcp Owo+ID4gKwl4c2Rpcnhzc193cml0ZShzdGF0ZSwgWFNESVJYX0lTUl9SRUcsIHN0YXR1cyk7Cj4g PiArCWRldl9kYmcoZGV2LCAiaW50ZXJydXB0IHN0YXR1cyA9IDB4JTA4eFxuIiwgc3RhdHVzKTsK PiA+ICsKPiA+ICsJaWYgKCFzdGF0dXMpCj4gPiArCQlyZXR1cm4gSVJRX05PTkU7Cj4gPiArCj4g PiArCWlmIChzdGF0dXMgJiBYU0RJUlhfSU5UUl9WSURMT0NLX01BU0sgfHwKPiA+ICsJICAgIHN0 YXR1cyAmIFhTRElSWF9JTlRSX1ZJRFVOTE9DS19NQVNLKSB7Cj4gPiArCQl1MzIgdmFsMSwgdmFs MjsKPiA+ICsJCXN0cnVjdCB2NGwyX2V2ZW50IGV2ZW50ID0geyAwIH07Cj4gPiArCQl1bnNpZ25l ZCBsb25nIGZsYWdzOwo+ID4gKwo+ID4gKwkJZGV2X2RiZyhkZXYsICJ2aWRlbyBsb2NrL3VubG9j ayBpbnRlcnJ1cHRcbiIpOwo+ID4gKwo+ID4gKwkJc3Bpbl9sb2NrX2lycXNhdmUoJnN0YXRlLT5z bG9jaywgZmxhZ3MpOwo+ID4gKwkJeHNkaXJ4X3N0cmVhbWZsb3dfY29udHJvbChzdGF0ZSwgZmFs c2UpOwo+ID4gKwo+ID4gKwkJdmFsMSA9IHhzZGlyeHNzX3JlYWQoc3RhdGUsIFhTRElSWF9NT0RF X0RFVF9TVEFUX1JFRyk7Cj4gPiArCQl2YWwyID0geHNkaXJ4c3NfcmVhZChzdGF0ZSwgWFNESVJY X1RTX0RFVF9TVEFUX1JFRyk7Cj4gPiArCj4gPiArCQlpZiAoKHZhbDEgJiBYU0RJUlhfTU9ERV9E RVRfU1RBVF9NT0RFX0xPQ0tfTUFTSykgJiYKPiA+ICsJCSAgICAodmFsMiAmIFhTRElSWF9UU19E RVRfU1RBVF9MT0NLRURfTUFTSykpIHsKPiA+ICsJCQl1MzIgbWFzayA9IFhTRElSWF9SU1RfQ1RS TF9SU1RfQ1JDX0VSUkNOVF9NQVNLIHwKPiA+ICsJCQkJICAgWFNESVJYX1JTVF9DVFJMX1JTVF9F REhfRVJSQ05UX01BU0s7Cj4gPiArCj4gPiArCQkJZGV2X2RiZyhkZXYsICJ2aWRlbyBsb2NrIGlu dGVycnVwdFxuIik7Cj4gPiArCj4gPiArCQkJeHNkaXJ4c3Nfc2V0KHN0YXRlLCBYU0RJUlhfUlNU X0NUUkxfUkVHLCBtYXNrKTsKPiA+ICsJCQl4c2Rpcnhzc19jbHIoc3RhdGUsIFhTRElSWF9SU1Rf Q1RSTF9SRUcsIG1hc2spOwo+ID4gKwo+ID4gKwkJCXZhbDEgPSB4c2Rpcnhzc19yZWFkKHN0YXRl LCBYU0RJUlhfU1QzNTJfVkFMSURfUkVHKTsKPiA+ICsJCQl2YWwyID0geHNkaXJ4c3NfcmVhZChz dGF0ZSwgWFNESVJYX1NUMzUyX0RTMV9SRUcpOwo+ID4gKwo+ID4gKwkJCWRldl9kYmcoZGV2LCAi dmFsaWQgc3QzNTIgbWFzayA9IDB4JTA4eFxuIiwgdmFsMSk7Cj4gPiArCQkJZGV2X2RiZyhkZXYs ICJzdDM1MiBwYXlsb2FkID0gMHglMDh4XG4iLCB2YWwyKTsKPiA+ICsKPiA+ICsJCQlpZiAoIXhz ZGlyeF9nZXRfc3RyZWFtX3Byb3BlcnRpZXMoc3RhdGUpKSB7Cj4gPiArCQkJCXN0YXRlLT52aWRs b2NrZWQgPSB0cnVlOwo+ID4gKwkJCQl4c2Rpcnhzc19zZXRfZ3RjbGsoc3RhdGUpOwo+ID4gKwkJ CX0gZWxzZSB7Cj4gPiArCQkJCWRldl9lcnIoZGV2LCAiVW5hYmxlIHRvIGdldCBzdHJlYW0gcHJv cGVydGllcyFcbiIpOwo+ID4gKwkJCQlzdGF0ZS0+dmlkbG9ja2VkID0gZmFsc2U7Cj4gPiArCQkJ fQo+ID4gKwkJfSBlbHNlIHsKPiA+ICsJCQlkZXZfZGJnKGRldiwgInZpZGVvIHVubG9jayBpbnRl cnJ1cHRcbiIpOwo+ID4gKwkJCXN0YXRlLT52aWRsb2NrZWQgPSBmYWxzZTsKPiA+ICsJCX0KPiA+ ICsJCXNwaW5fdW5sb2NrX2lycXJlc3RvcmUoJnN0YXRlLT5zbG9jaywgZmxhZ3MpOwo+ID4gKwo+ ID4gKwkJZXZlbnQudHlwZSA9IFY0TDJfRVZFTlRfU09VUkNFX0NIQU5HRTsKPiA+ICsJCWV2ZW50 LnUuc3JjX2NoYW5nZS5jaGFuZ2VzID0gVjRMMl9FVkVOVF9TUkNfQ0hfUkVTT0xVVElPTjsKPiA+ ICsJCXY0bDJfc3ViZGV2X25vdGlmeV9ldmVudCgmc3RhdGUtPnN1YmRldiwgJmV2ZW50KTsKPiA+ ICsJfQo+ID4gKwo+ID4gKwlpZiAoc3RhdHVzICYgKFhTRElSWF9JTlRSX1VOREVSRkxPV19NQVNL IHwgWFNESVJYX0lOVFJfT1ZFUkZMT1dfTUFTSykpIHsKPiA+ICsJCXN0cnVjdCB2NGwyX2V2ZW50 IGV2ZW50ID0geyAwIH07Cj4gPiArCj4gPiArCQlkZXZfZGJnKGRldiwgIlZpZGVvIGluIHRvIEFY STQgU3RyZWFtIGNvcmUgdW5kZXIvb3ZlcmZsb3cgaW50ZXJydXB0XG4iKTsKPiA+ICsKPiA+ICsJ CWV2ZW50LnR5cGUgPSBWNEwyX0VWRU5UX1hJTElOWF9TRElSWF9VTkRfT1ZSX0ZMT1c7Cj4gPiAr CQlpZiAoc3RhdHVzICYgWFNESVJYX0lOVFJfVU5ERVJGTE9XX01BU0spCj4gPiArCQkJZXZlbnQu dS5kYXRhWzBdID0gWElMSU5YX1NESVJYX1VOREVSRkxPV19FVkVOVDsKClNob3VsZCB0aGlzIGJl CgoJCQlldmVudC51LmRhdGFbMF0gfD0gWElMSU5YX1NESVJYX1VOREVSRkxPV19FVkVOVDsKCj4g PiArCQlpZiAoc3RhdHVzICYgWFNESVJYX0lOVFJfT1ZFUkZMT1dfTUFTSykKPiA+ICsJCQlldmVu dC51LmRhdGFbMF0gPSBYSUxJTlhfU0RJUlhfT1ZFUkZMT1dfRVZFTlQ7CgpBbmQgdGhpcwoKCQkJ ZXZlbnQudS5kYXRhWzBdIHw9IFhJTElOWF9TRElSWF9PVkVSRkxPV19FVkVOVDsKCmluIGNhc2Ug Ym90aCB1bmRlcmZsb3cgYW5kIG92ZXJmbG93IG5lZWQgdG8gYmUgcmVwb3J0ZWQgYXQgdGhlIHNh bWUgdGltZQo/IEknbSBub3Qgc3VyZSB0aGF0IGNhbiBoYXBwZW4gaW4gcHJhY3RpY2UgdGhvdWdo LCBidXQgZXZlbiBpZiBpdCBjYW4ndCwKaXQgYWxzbyB3b24ndCBodXJ0IHRvIHRyZWF0IHRoZSBm aWVsZCBhcyBhIGJpdGZsYWcuCgo+ID4gKwo+ID4gKwkJdjRsMl9zdWJkZXZfbm90aWZ5X2V2ZW50 KCZzdGF0ZS0+c3ViZGV2LCAmZXZlbnQpOwo+ID4gKwl9Cj4gPiArCXJldHVybiBJUlFfSEFORExF RDsKPiA+ICt9Cj4gPiArCj4gPiArLyoqCj4gPiArICogeHNkaXJ4c3Nfc3Vic2NyaWJlX2V2ZW50 IC0gU3Vic2NyaWJlIHRvIHZpZGVvIGxvY2sgYW5kIHVubG9jayBldmVudAo+ID4gKyAqIEBzZDog VjRMMiBTdWIgZGV2aWNlCj4gPiArICogQGZoOiBWNEwyIEZpbGUgSGFuZGxlCj4gPiArICogQHN1 YjogU3ViY3JpYmUgZXZlbnQgc3RydWN0dXJlCj4gPiArICoKPiA+ICsgKiBSZXR1cm46IDAgb24g c3VjY2VzcywgZXJyb3JzIG90aGVyd2lzZQo+ID4gKyAqLwo+ID4gK3N0YXRpYyBpbnQgeHNkaXJ4 c3Nfc3Vic2NyaWJlX2V2ZW50KHN0cnVjdCB2NGwyX3N1YmRldiAqc2QsCj4gPiArCQkJCSAgICBz dHJ1Y3QgdjRsMl9maCAqZmgsCj4gPiArCQkJCSAgICBzdHJ1Y3QgdjRsMl9ldmVudF9zdWJzY3Jp cHRpb24gKnN1YikKPiA+ICt7Cj4gPiArCWludCByZXQ7Cj4gPiArCXN0cnVjdCB4c2Rpcnhzc19z dGF0ZSAqeHNkaXJ4c3MgPSB0b194c2Rpcnhzc3N0YXRlKHNkKTsKPiA+ICsKPiA+ICsJZGV2X2Ri Zyh4c2Rpcnhzcy0+ZGV2LCAiRXZlbnQgc3Vic2NyaWJlZCA6IDB4JTA4eFxuIiwgc3ViLT50eXBl KTsKPiA+ICsJc3dpdGNoIChzdWItPnR5cGUpIHsKPiA+ICsJY2FzZSBWNEwyX0VWRU5UX1hJTElO WF9TRElSWF9VTkRfT1ZSX0ZMT1c6Cj4gPiArCQlyZXQgPSB2NGwyX2V2ZW50X3N1YnNjcmliZShm aCwgc3ViLCBYU0RJUlhfTUFYX0VWRU5UUywgTlVMTCk7Cj4gPiArCQlicmVhazsKPiA+ICsJY2Fz ZSBWNEwyX0VWRU5UX1NPVVJDRV9DSEFOR0U6Cj4gPiArCQlyZXQgPSB2NGwyX3NyY19jaGFuZ2Vf ZXZlbnRfc3Vic2NyaWJlKGZoLCBzdWIpOwo+ID4gKwkJYnJlYWs7Cj4gPiArCWRlZmF1bHQ6Cj4g PiArCQlyZXQgPSB2NGwyX2N0cmxfc3Vic2NyaWJlX2V2ZW50KGZoLCBzdWIpOwoKSXQncyBjdXN0 b21hcnkgdG8gaGF2ZSBhIGJyZWFrIGF0IHRoZSBlbmQgb2YgdGhlIGxhc3QgY2FzZS4KCj4gPiAr CX0KPiA+ICsJcmV0dXJuIHJldDsKPiA+ICt9Cj4gPiArCj4gPiArLyoqCj4gPiArICogeHNkaXJ4 c3Nfc19jdHJsIC0gVGhpcyBpcyB1c2VkIHRvIHNldCB0aGUgWGlsaW54IFNESSBSeCBWNEwyIGNv bnRyb2xzCj4gPiArICogQGN0cmw6IFY0TDIgY29udHJvbCB0byBiZSBzZXQKPiA+ICsgKgo+ID4g KyAqIFRoaXMgZnVuY3Rpb24gaXMgdXNlZCB0byBzZXQgdGhlIFY0TDIgY29udHJvbHMgZm9yIHRo ZSBYaWxpbnggU0RJIFJ4Cj4gPiArICogU3Vic3lzdGVtLgo+ID4gKyAqCj4gPiArICogUmV0dXJu OiAwIG9uIHN1Y2Nlc3MsIGVycm9ycyBvdGhlcndpc2UKPiA+ICsgKi8KPiA+ICtzdGF0aWMgaW50 IHhzZGlyeHNzX3NfY3RybChzdHJ1Y3QgdjRsMl9jdHJsICpjdHJsKQo+ID4gK3sKPiA+ICsJaW50 IHJldCA9IDA7Cj4gPiArCXN0cnVjdCB4c2Rpcnhzc19zdGF0ZSAqeHNkaXJ4c3MgPQo+ID4gKwkJ Y29udGFpbmVyX29mKGN0cmwtPmhhbmRsZXIsIHN0cnVjdCB4c2Rpcnhzc19zdGF0ZSwKPiA+ICsJ CQkgICAgIGN0cmxfaGFuZGxlcik7Cj4gPiArCXN0cnVjdCBkZXZpY2UgKmRldiA9IHhzZGlyeHNz LT5kZXY7Cj4gPiArCXVuc2lnbmVkIGxvbmcgZmxhZ3M7Cj4gPiArCj4gPiArCWRldl9kYmcoZGV2 LCAic2V0IGN0cmwgaWQgPSAweCUwOHggdmFsID0gMHglMDh4XG4iLAo+ID4gKwkJY3RybC0+aWQs IGN0cmwtPnZhbCk7Cj4gPiArCj4gPiArCXNwaW5fbG9ja19pcnFzYXZlKCZ4c2Rpcnhzcy0+c2xv Y2ssIGZsYWdzKTsKPiA+ICsKPiA+ICsJaWYgKHhzZGlyeHNzLT5zdHJlYW1pbmcpIHsKPiA+ICsJ CXNwaW5fdW5sb2NrX2lycXJlc3RvcmUoJnhzZGlyeHNzLT5zbG9jaywgZmxhZ3MpOwo+ID4gKwkJ ZGV2X2VycihkZXYsICJDYW5ub3Qgc2V0IGNvbnRyb2xzIHdoaWxlIHN0cmVhbWluZ1xuIik7Cj4g PiArCQlyZXR1cm4gLUVJTlZBTDsKPiA+ICsJfQo+ID4gKwo+ID4gKwlYU0RJUlhfQ09SRV9ESVNB QkxFKHhzZGlyeHNzKTsKPiA+ICsJc3dpdGNoIChjdHJsLT5pZCkgewo+ID4gKwljYXNlIFY0TDJf Q0lEX1hJTElOWF9TRElSWF9GUkFNRVI6Cj4gPiArCQl4c2Rpcnhzcy0+ZnJhbWVyX2VuYWJsZSA9 IGN0cmwtPnZhbDsKPiA+ICsJCWlmICh4c2Rpcnhzcy0+ZnJhbWVyX2VuYWJsZSkgewo+ID4gKwkJ CXhzZGlyeHNzX3NldCh4c2RpcnhzcywgWFNESVJYX01ETF9DVFJMX1JFRywKPiA+ICsJCQkJICAg ICBYU0RJUlhfTURMX0NUUkxfRlJNX0VOX01BU0spOwo+ID4gKwkJfSBlbHNlIHsKPiA+ICsJCQl4 c2Rpcnhzc19jbHIoeHNkaXJ4c3MsIFhTRElSWF9NRExfQ1RSTF9SRUcsCj4gPiArCQkJCSAgICAg WFNESVJYX01ETF9DVFJMX0ZSTV9FTl9NQVNLKTsKPiA+ICsJCX0KPiA+ICsJCWJyZWFrOwo+ID4g KwljYXNlIFY0TDJfQ0lEX1hJTElOWF9TRElSWF9WSURMT0NLX1dJTkRPVzoKPiA+ICsJCS8qCj4g PiArCQkgKiBUaGUgdmlkZW8gbG9jayB3aW5kb3cgaXMgdGhlIGFtb3VudCBvZiB0aW1lIGZvciB3 aGljaCB0aGUKPiA+ICsJCSAqIHRoZSBtb2RlIGFuZCB0cmFuc3BvcnQgc3RyZWFtIHNob3VsZCBi ZSBsb2NrZWQgdG8gZ2V0IHRoZQo+ID4gKwkJICogdmlkZW8gbG9jayBpbnRlcnJ1cHQuCj4gPiAr CQkgKi8KPiA+ICsJCXhzZGlyeHNzLT52aWRsb2Nrd2luID0gY3RybC0+dmFsOwo+ID4gKwkJeHNk aXJ4c3Nfd3JpdGUoeHNkaXJ4c3MsIFhTRElSWF9WSURfTE9DS19XSU5ET1dfUkVHLAo+ID4gKwkJ CSAgICAgICB4c2Rpcnhzcy0+dmlkbG9ja3dpbik7Cj4gPiArCQlicmVhazsKPiA+ICsJY2FzZSBW NEwyX0NJRF9YSUxJTlhfU0RJUlhfRURIX0VSUk9SX1NPVVJDRVM6Cj4gPiArCQl4c2Rpcnhzcy0+ ZWRobWFzayA9IGN0cmwtPnZhbCAmIFhTRElSWF9FREhfQUxMRVJSX01BU0s7Cj4gCj4gVGhlICcm IFhTRElSWF9FREhfQUxMRVJSX01BU0snIGlzIG5vdCBuZWVkZWQgc2luY2UgdGhlIGNvbnRyb2wn cyAnbWF4JyB2YWx1ZQo+IGlzIHNldCB0byBYU0RJUlhfRURIX0FMTEVSUl9NQVNLLCBzbyBjdHJs LT52YWwgY2FuJ3QgY29udGFpbiBhbnkgb3RoZXIgYml0cy4KPiBUaGUgY29udHJvbCBmcmFtZXdv cmsgZW5zdXJlcyB0aGF0Lgo+IAo+ID4gKwkJeHNkaXJ4c3Nfd3JpdGUoeHNkaXJ4c3MsIFhTRElS WF9FREhfRVJSQ05UX0VOX1JFRywKPiA+ICsJCQkgICAgICAgeHNkaXJ4c3MtPmVkaG1hc2spOwo+ ID4gKwkJYnJlYWs7Cj4gPiArCWNhc2UgVjRMMl9DSURfWElMSU5YX1NESVJYX1NFQVJDSF9NT0RF UzoKPiA+ICsJCWlmICghY3RybC0+dmFsKSB7Cj4gCj4gVGhpcyBjaGVjayBzaG91bGQgYmUgZG9u ZSBpbiBhIHRyeV9jdHJsIGZ1bmN0aW9uIGluc3RlYWQgb2Ygc19jdHJsLgo+IAo+IEludGVyZXN0 aW5nLCB0aGlzIGlzIHRoZSBmaXJzdCBiaXRtYXNrIGNvbnRyb2wgd2hlcmUgeW91IGRvbid0IHdh bnQgaXQgdG8KPiBiZSAwLiBJZiB3ZSBnZXQgbW9yZSBvZiB0aGVzZSBpbiB0aGUgZnV0dXJlLCB0 aGVuIGl0IHdvdWxkIG1ha2Ugc2Vuc2UgaWYgdGhpcwo+IGlzIHN1cHBvcnRlZCBpbiB0aGUgY29u dHJvbCBmcmFtZXdvcmsgaXRzZWxmIChlLmcuIGlmIG1pbiBpcyBzZXQgdG8gMSwgdGhlbgo+IHRo YXQgbWVhbnMgdGhhdCB0aGUgdmFsdWUgY2FuJ3QgYmUgMCkuIEJ1dCBmb3Igbm93IGp1c3QgY2hl Y2sgdGhpcyBpbiB0aGUKPiB0cnlfY3RybCgpIGZ1bmN0aW9uLgo+IAo+ID4gKwkJCXNwaW5fdW5s b2NrX2lycXJlc3RvcmUoJnhzZGlyeHNzLT5zbG9jaywgZmxhZ3MpOwo+ID4gKwkJCWRldl9lcnIo ZGV2LCAiU2VsZWN0IGF0IGxlYXN0IG9uZSBtb2RlIVxuIik7Cj4gPiArCQkJcmV0dXJuIC1FSU5W QUw7Cj4gPiArCQl9Cj4gPiArCj4gPiArCQlpZiAoeHNkaXJ4c3MtPm1vZGUgPT0gWFNESV9TVERf M0cpIHsKPiA+ICsJCQlkZXZfZGJnKGRldiwgIlVwdG8gM0cgc3VwcG9ydGVkXG4iKTsKPiA+ICsJ CQljdHJsLT52YWwgJj0gfihCSVQoWFNESVJYX01PREVfNkdfT0ZGU0VUKSB8Cj4gPiArCQkJCSAg ICAgICBCSVQoWFNESVJYX01PREVfMTJHSV9PRkZTRVQpIHwKPiA+ICsJCQkJICAgICAgIEJJVChY U0RJUlhfTU9ERV8xMkdGX09GRlNFVCkpOwo+ID4gKwkJfQo+ID4gKwo+ID4gKwkJaWYgKHhzZGly eHNzLT5tb2RlID09IFhTRElfU1REXzZHKSB7Cj4gPiArCQkJZGV2X2RiZyhkZXYsICJVcHRvIDZH IHN1cHBvcnRlZFxuIik7Cj4gPiArCQkJY3RybC0+dmFsICY9IH4oQklUKFhTRElSWF9NT0RFXzEy R0lfT0ZGU0VUKSB8Cj4gPiArCQkJCSAgICAgICBCSVQoWFNESVJYX01PREVfMTJHRl9PRkZTRVQp KTsKPiA+ICsJCX0KPiAKPiBUaGlzIHNob3VsZG4ndCBiZSBkb25lIGhlcmUuIEluc3RlYWQgdGhl ICdtYXgnIGZpZWxkIG9mIHRoZSBjb250cm9sIG11c3QgYmUKPiBzZXQgY29ycmVjdGx5IGJhc2Vk IG9uIHRoZSBtb2RlLiBZb3UgY2FuIGNhbGwgdjRsMl9jdHJsX21vZGlmeV9yYW5nZSgpIGluCj4g eHNkaXJ4c3NfcHJvYmUoKSB0byB1cGRhdGUgdGhlIG1heCB2YWx1ZS4KCkhhbnMsIEkgd3JvdGUg dGhpcyBjb21tZW50IGluIHYyOgoKIlRoZSB0cmFkaXRpb25hbCBhcHByb2FjaCB0byBzZWxlY3Qg dGltaW5nIHN0YW5kYXJkcyBpcyB0byB1c2UgaW9jdGxzLgpIYW5zLCBkbyB5b3UgdGhpbmsgYSBj dXN0b20gY29udHJvbCBpcyBmaW5lIGhlcmUsIG9yIHNob3VsZCB0aGUgZHYKdGltaW5ncyBpb2N0 bHMgYmUgZXh0ZW5kZWQgKG9yIG5ldyBzZGkgdGltaW5ncyBpb2N0bHMgY3JlYXRlZCkgPwoKSWYg d2UgZ28gZm9yIGEgc2luZ2xlIGNvbnRyb2wsIEknbSBhIGJpdCBjb25jZXJuZWQgdGhhdCB0aGlz IGNvbnRyb2wKd2lsbCByZXN0cmljdCB0aGUgc2VhcmNoIHdoZW4gbXVsdGlwbGUgYml0cyBhcmUg c2V0LCBidXQgZm9yY2UgYQpzcGVjaWZpYyBtb2RlIHdoZW4gYSBzaW5nbGUgYml0IGlzIHNldC4g SSBkb24ndCBoYXZlIGVub3VnaCBleHBlcmllbmNlCndpdGggU0RJIHRvIHRlbGwgd2hldGhlciB0 aGlzIGlzIHRoZSByaWdodCBiZWhhdmlvdXIuIgoKV2hhdCBkbyB5b3UgdGhpbmsgPyBJdCdzIG9m IGNvdXJzZSBoYXJkIHRvIHN0YW5kYXJkaXplIGFuIEFQSSB3aXRoIGEKc2luZ2xlIGRldmljZSBh cyBhbiBleGFtcGxlIChhbHRob3VnaCB0aGVyZSdzIGFsc28gYSBzcGVjIHRvIGhlbHAgaGVyZSks CnNvIEknbSBub3Qgb3Bwb3NlZCB0byB1c2luZyBjb250cm9scyBpbiB0aGlzIGRyaXZlci4KCj4g PiArCj4gPiArCQlyZXQgPSB4c2Rpcnhfc2V0X21vZGVkZXRlY3QoeHNkaXJ4c3MsIGN0cmwtPnZh bCk7Cj4gPiArCQlpZiAoIXJldCkKPiA+ICsJCQl4c2Rpcnhzcy0+c2VhcmNobWFzayA9IGN0cmwt PnZhbDsKPiA+ICsJCWJyZWFrOwo+ID4gKwlkZWZhdWx0Ogo+ID4gKwkJcmV0ID0gLUVJTlZBTDsK PiA+ICsJCWJyZWFrOwo+ID4gKwl9Cj4gPiArCVhTRElSWF9DT1JFX0VOQUJMRSh4c2Rpcnhzcyk7 Cj4gPiArCj4gPiArCXNwaW5fdW5sb2NrX2lycXJlc3RvcmUoJnhzZGlyeHNzLT5zbG9jaywgZmxh Z3MpOwo+ID4gKwlyZXR1cm4gcmV0Owo+ID4gK30KPiA+ICsKPiA+ICsvKioKPiA+ICsgKiB4c2Rp cnhzc19nX3ZvbGF0aWxlX2N0cmwgLSBnZXQgdGhlIFhpbGlueCBTREkgUnggY29udHJvbHMKPiA+ ICsgKiBAY3RybDogUG9pbnRlciB0byBWNEwyIGNvbnRyb2wKPiA+ICsgKgo+ID4gKyAqIFJldHVy bjogMCBvbiBzdWNjZXNzLCBlcnJvcnMgb3RoZXJ3aXNlCj4gPiArICovCj4gPiArc3RhdGljIGlu dCB4c2Rpcnhzc19nX3ZvbGF0aWxlX2N0cmwoc3RydWN0IHY0bDJfY3RybCAqY3RybCkKPiA+ICt7 Cj4gPiArCXUzMiB2YWw7Cj4gPiArCXN0cnVjdCB4c2Rpcnhzc19zdGF0ZSAqeHNkaXJ4c3MgPQo+ ID4gKwkJY29udGFpbmVyX29mKGN0cmwtPmhhbmRsZXIsCj4gPiArCQkJICAgICBzdHJ1Y3QgeHNk aXJ4c3Nfc3RhdGUsIGN0cmxfaGFuZGxlcik7Cj4gPiArCXN0cnVjdCBkZXZpY2UgKmRldiA9IHhz ZGlyeHNzLT5kZXY7Cj4gPiArCXVuc2lnbmVkIGxvbmcgZmxhZ3M7Cj4gPiArCj4gPiArCXNwaW5f bG9ja19pcnFzYXZlKCZ4c2Rpcnhzcy0+c2xvY2ssIGZsYWdzKTsKPiA+ICsJaWYgKCF4c2Rpcnhz cy0+dmlkbG9ja2VkKSB7Cj4gPiArCQlzcGluX3VubG9ja19pcnFyZXN0b3JlKCZ4c2Rpcnhzcy0+ c2xvY2ssIGZsYWdzKTsKPiA+ICsJCWRldl9lcnIoZGV2LCAiQ2FuJ3QgZ2V0IHZhbHVlcyB3aGVu IHZpZGVvIG5vdCBsb2NrZWQhXG4iKTsKPiA+ICsJCXJldHVybiAtRUlOVkFMOwo+ID4gKwl9Cj4g PiArCXN3aXRjaCAoY3RybC0+aWQpIHsKPiA+ICsJY2FzZSBWNEwyX0NJRF9YSUxJTlhfU0RJUlhf TU9ERV9ERVRFQ1Q6Cj4gPiArCQl2YWwgPSB4c2Rpcnhzc19yZWFkKHhzZGlyeHNzLCBYU0RJUlhf TU9ERV9ERVRfU1RBVF9SRUcpOwo+ID4gKwkJdmFsICY9IFhTRElSWF9NT0RFX0RFVF9TVEFUX1JY X01PREVfTUFTSzsKPiA+ICsKPiA+ICsJCXN3aXRjaCAodmFsKSB7Cj4gPiArCQljYXNlIFhTRElS WF9NT0RFX1NEX01BU0s6Cj4gPiArCQkJY3RybC0+dmFsID0gWFNESVJYX01PREVfU0RfT0ZGU0VU Owo+ID4gKwkJCWJyZWFrOwo+ID4gKwkJY2FzZSBYU0RJUlhfTU9ERV9IRF9NQVNLOgo+ID4gKwkJ CWN0cmwtPnZhbCA9IFhTRElSWF9NT0RFX0hEX09GRlNFVDsKPiA+ICsJCQlicmVhazsKPiA+ICsJ CWNhc2UgWFNESVJYX01PREVfM0dfTUFTSzoKPiA+ICsJCQl2YWwgPSB4c2Rpcnhzc19yZWFkKHhz ZGlyeHNzLCBYU0RJUlhfTU9ERV9ERVRfU1RBVF9SRUcpOwo+ID4gKwkJCXZhbCAmPSBYU0RJUlhf TU9ERV9ERVRfU1RBVF9MVkxCXzNHX01BU0s7Cj4gPiArCQkJY3RybC0+dmFsID0gdmFsID8gWFNE SVJYX01PREVfM0dCX09GRlNFVCA6Cj4gPiArCQkJCVhTRElSWF9NT0RFXzNHQV9PRkZTRVQ7Cj4g PiArCQkJYnJlYWs7Cj4gPiArCQljYXNlIFhTRElSWF9NT0RFXzZHX01BU0s6Cj4gPiArCQkJY3Ry bC0+dmFsID0gWFNESVJYX01PREVfNkdfT0ZGU0VUOwo+ID4gKwkJCWJyZWFrOwo+ID4gKwkJY2Fz ZSBYU0RJUlhfTU9ERV8xMkdJX01BU0s6Cj4gPiArCQkJY3RybC0+dmFsID0gWFNESVJYX01PREVf MTJHSV9PRkZTRVQ7Cj4gPiArCQkJYnJlYWs7Cj4gPiArCQljYXNlIFhTRElSWF9NT0RFXzEyR0Zf TUFTSzoKPiA+ICsJCQljdHJsLT52YWwgPSBYU0RJUlhfTU9ERV8xMkdGX09GRlNFVDsKPiA+ICsJ CQlicmVhazsKPiA+ICsJCX0KPiAKPiBUaGVyZSBpcyBubyBpbnRlcnJ1cHQgdGhhdCB3aWxsIHRl bGwgeW91IHdoZW4gdGhlIG1vZGUgY2hhbmdlcz8gSXQncyBtdWNoCj4gbmljZXIgaWYgdXBkYXRp bmcgdGhpcyBjb250cm9sIGlzIGludGVycnVwdCBkcml2ZW4gcmF0aGVyIHRoYW4gcmVxdWlyaW5n Cj4gdXNlcnNwYWNlIHRvIHBvbGwuCj4gCj4gPiArCQlicmVhazsKPiA+ICsJY2FzZSBWNEwyX0NJ RF9YSUxJTlhfU0RJUlhfQ1JDOgo+ID4gKwkJY3RybC0+dmFsID0geHNkaXJ4c3NfcmVhZCh4c2Rp cnhzcywgWFNESVJYX0NSQ19FUlJDTlRfUkVHKTsKPiA+ICsJCXhzZGlyeHNzX3dyaXRlKHhzZGly eHNzLCBYU0RJUlhfQ1JDX0VSUkNOVF9SRUcsIDB4ZmZmZik7Cj4gPiArCQlicmVhazsKPiA+ICsJ Y2FzZSBWNEwyX0NJRF9YSUxJTlhfU0RJUlhfRURIX0VSUkNOVDoKPiA+ICsJCXZhbCA9IHhzZGly eHNzX3JlYWQoeHNkaXJ4c3MsIFhTRElSWF9NT0RFX0RFVF9TVEFUX1JFRyk7Cj4gPiArCQl2YWwg Jj0gWFNESVJYX01PREVfREVUX1NUQVRfUlhfTU9ERV9NQVNLOwo+ID4gKwkJaWYgKHZhbCA9PSBY U0RJUlhfTU9ERV9TRF9NQVNLKSB7Cj4gPiArCQkJY3RybC0+dmFsID0geHNkaXJ4c3NfcmVhZCh4 c2RpcnhzcywKPiA+ICsJCQkJCQkgIFhTRElSWF9FREhfRVJSQ05UX1JFRyk7Cj4gPiArCQl9IGVs c2Ugewo+ID4gKwkJCXNwaW5fdW5sb2NrX2lycXJlc3RvcmUoJnhzZGlyeHNzLT5zbG9jaywgZmxh Z3MpOwo+ID4gKwkJCWRldl9kYmcoZGV2LCAiJWQgLSBub3QgaW4gU0QgbW9kZVxuIiwgY3RybC0+ aWQpOwo+ID4gKwkJCXJldHVybiAtRUlOVkFMOwo+IAo+IEdldHRpbmcgYSBjb250cm9sIHZhbHVl IHNob3VsZG4ndCBmYWlsLiBKdXN0IHNldCBjdHJsLT52YWwgdG8gMCBhbmQKPiByZXR1cm4gMC4g WW91IGNhbiBsZWF2ZSB0aGUgZGV2X2RiZyB0aG91Z2gsIHRoYXQgY2FuIGJlIHVzZWZ1bC4KPiAK PiA+ICsJCX0KPiA+ICsJCWJyZWFrOwo+ID4gKwljYXNlIFY0TDJfQ0lEX1hJTElOWF9TRElSWF9F REhfU1RBVFVTOgo+ID4gKwkJdmFsID0geHNkaXJ4c3NfcmVhZCh4c2RpcnhzcywgWFNESVJYX01P REVfREVUX1NUQVRfUkVHKTsKPiA+ICsJCXZhbCAmPSBYU0RJUlhfTU9ERV9ERVRfU1RBVF9SWF9N T0RFX01BU0s7Cj4gPiArCQlpZiAodmFsID09IFhTRElSWF9NT0RFX1NEX01BU0spIHsKPiA+ICsJ CQljdHJsLT52YWwgPSB4c2Rpcnhzc19yZWFkKHhzZGlyeHNzLAo+ID4gKwkJCQkJCSAgWFNESVJY X0VESF9TVEFUX1JFRyk7Cj4gPiArCQl9IGVsc2Ugewo+ID4gKwkJCXNwaW5fdW5sb2NrX2lycXJl c3RvcmUoJnhzZGlyeHNzLT5zbG9jaywgZmxhZ3MpOwo+ID4gKwkJCWRldl9kYmcoZGV2LCAiJWQg LSBub3QgaW4gU0QgbW9kZVxuIiwgY3RybC0+aWQpOwo+ID4gKwkJCXJldHVybiAtRUlOVkFMOwo+ IAo+IERpdHRvLgo+IAo+ID4gKwkJfQo+ID4gKwkJYnJlYWs7Cj4gPiArCWNhc2UgVjRMMl9DSURf WElMSU5YX1NESVJYX1RTX0lTX0lOVEVSTEFDRUQ6Cj4gPiArCQljdHJsLT52YWwgPSB4c2Rpcnhz cy0+dHNfaXNfaW50ZXJsYWNlZDsKPiA+ICsJCWJyZWFrOwo+IAo+IEkgYXNzdW1lIHRoaXMgY29u dHJvbCB3aWxsIGRpc2FwcGVhciBvbmNlIHlvdSBhZGRlZCBzdXBwb3J0IGZvcgo+IEZJRUxEX0FM VEVSTkFURV9QUk9HPwoKSSdtIG5vdCBzdXJlIEZJRUxEX0FMVEVSTkFURV9QUk9HIGlzIGEgZ29v ZCBpZGVhLiBUaGUgdjRsMl9maWVsZApzcGVjaWZpZXMgdG9kYXkgaG93IGZyYW1lcyBhcmUgc3Bs aXQgaW50byBtdWx0aXBsZSBidWZmZXJzLiBUaGVyZSdzIGFuCmltcGxpY2l0IGFzc3VtcHRpb24g dGhhdCBhIGZyYW1lIHNwbGl0IGludG8gdHdvIGJ1ZmZlcnMgaXMgY2FwdHVyZWQgd2l0aAppbnRl cmxhY2luZy4gSW4gdGhlIFNESSBjYXNlLCB0aGUgdHdvIGNvbmNlcHRzIGdldCBkZWNvdXBsZWQs IGEKcHJvZ3Jlc3NpdmUgZnJhbWUgY2FuIGJlIHRyYW5zbWl0dGVkIChhbmQgY2FwdHVyZWQpIGlu IHR3byBzZXBhcmF0ZQpwYXJ0cy4gSWYgd2UgYWRkIGEgKl9QUk9HIGZpZWxkLCB3ZSdsbCBuZWVk IHRvIGR1cGxpY2F0ZSBtb3N0IG9mIHRoZQp2NGwyX2ZpZWxkIHZhbHVlcyB3aXRoIGEgX1BST0cg c3VmZml4LCBhcyB0aGUgcHJvZ3Jlc3NpdmUgZnJhbWUgY2FuIGJlCmNhcHR1cmVkIGluIGFsdGVy bmF0ZSBidWZmZXJzIG9uIGEgdmlkZW8gbm9kZSwgYnV0IGFsc28gaW4gc2VwYXJhdGUgb2RkCmFu ZCBldmVuIGJ1ZmZlcnMgb24gdHdvIHZpZGVvIG5vZGVzLiBUdCB0aGUgaGFyZHdhcmUgbGV2ZWws IGRhdGEgaXMKdHJhbnNtaXR0ZWQgd2l0aCBvZGQgbGluZXMgb24gb25lIGxpbmssIGFuZCBldmVu IGxpbmVzIG9uIGEgc2Vjb25kIGxpbmsuClRoZXJlIGFyZSB0aGVuIHR3byBpbnN0YW5jZXMgb2Yg dGhpcyBJUCBjb3JlLCBvbmUgZm9yIGVhY2ggbGluay4gT25lCmluc3RhbmNlIHdvdWxkIHJlY2Vp dmUgYW5kIHByb2Nlc3MgdGhlIGV2ZW4gbGluZXMsIHRoZSBvdGhlciBpbnN0YW5jZQp0aGUgb2Rk IGxpbmVzLiBUaGUgb3V0cHV0IG9mIHRoZSB0d28gaW5zdGFuY2VzIGNhbiB0aGVuIGJlIGNvbm5l Y3RlZCB0bwp0d28gc2VwYXJhdGUgRE1BIGVuZ2luZXMsIG9yIGNvbWJpbmVkIGluIHRoZSBGUEdB IGZhYnJpYywgZGVwZW5kaW5nIG9uCmhvdyB0aGUgdXNlciBkZXNpZ25zIHRoZSBzeXN0ZW0uCgo+ ID4gKwlkZWZhdWx0Ogo+ID4gKwkJc3Bpbl91bmxvY2tfaXJxcmVzdG9yZSgmeHNkaXJ4c3MtPnNs b2NrLCBmbGFncyk7Cj4gPiArCQlkZXZfZXJyKGRldiwgIkdldCBJbnZhbGlkIGNvbnRyb2wgaWQg MHglMHhcbiIsIGN0cmwtPmlkKTsKPiA+ICsJCXJldHVybiAtRUlOVkFMOwo+IAo+IFlvdSBjYW4g ZHJvcCB0aGUgZGVmYXVsdCBjYXNlIGFsdG9nZXRoZXI6IHRoaXMgZnVuY3Rpb24gd2lsbCBvbmx5 IGJlIGNhbGxlZAo+IGZvciB2b2xhdGlsZSBjb250cm9scy4KPiAKPiA+ICsJfQo+ID4gKwo+ID4g KwlzcGluX3VubG9ja19pcnFyZXN0b3JlKCZ4c2Rpcnhzcy0+c2xvY2ssIGZsYWdzKTsKPiA+ICsJ cmV0dXJuIDA7Cj4gPiArfQo+ID4gKwo+ID4gKy8qKgo+ID4gKyAqIHhzZGlyeHNzX2xvZ19zdGF0 dXMgLSBMb2dzIHRoZSBzdGF0dXMgb2YgdGhlIFNESSBSeCBTdWJzeXN0ZW0KPiA+ICsgKiBAc2Q6 IFBvaW50ZXIgdG8gVjRMMiBzdWJkZXZpY2Ugc3RydWN0dXJlCj4gPiArICoKPiA+ICsgKiBUaGlz IGZ1bmN0aW9uIHByaW50cyB0aGUgY3VycmVudCBzdGF0dXMgb2YgWGlsaW54IFNESSBSeCBTdWJz eXN0ZW0KPiA+ICsgKgo+ID4gKyAqIFJldHVybjogMCBvbiBzdWNjZXNzCj4gPiArICovCj4gPiAr c3RhdGljIGludCB4c2Rpcnhzc19sb2dfc3RhdHVzKHN0cnVjdCB2NGwyX3N1YmRldiAqc2QpCj4g PiArewo+ID4gKwlzdHJ1Y3QgeHNkaXJ4c3Nfc3RhdGUgKnhzZGlyeHNzID0gdG9feHNkaXJ4c3Nz dGF0ZShzZCk7Cj4gPiArCXUzMiBpOwo+ID4gKwo+ID4gKwl2NGwyX2luZm8oc2QsICIqKioqKiBT REkgUnggc3Vic3lzdGVtIHJlZyBkdW1wIHN0YXJ0ICoqKioqXG4iKTsKPiA+ICsJdjRsMl9pbmZv KHNkLCAiTm8gOiBSZWdpc3RlciBOYW1lIDogVmFsdWVcbiIpOwo+ID4gKwlmb3IgKGkgPSAwOyBp IDwgQVJSQVlfU0laRSh4c2Rpcnhzc19yZWdtYXApOyBpKyspIHsKPiA+ICsJCXY0bDJfaW5mbyhz ZCwgIiUwMmQgOiAlcyByZWdpc3RlciA6IDB4JTA4eFxuIiwgaSwKPiA+ICsJCQkgIHhzZGlyeHNz X3JlZ21hcFtpXS5uYW1lLAo+ID4gKwkJCSAgeHNkaXJ4c3NfcmVhZCh4c2RpcnhzcywgeHNkaXJ4 c3NfcmVnbWFwW2ldLm9mZnNldCkpOwo+ID4gKwl9Cj4gPiArCXY0bDJfaW5mbyhzZCwgIioqKioq IFNESSBSeCBzdWJzeXN0ZW0gcmVnIGR1bXAgZW5kICoqKioqXG4iKTsKPiA+ICsKPiA+ICsJdjRs Ml9jdHJsX3N1YmRldl9sb2dfc3RhdHVzKHNkKTsKPiA+ICsKPiA+ICsJcmV0dXJuIDA7Cj4gPiAr fQo+ID4gKwo+ID4gKy8qKgo+ID4gKyAqIHhzZGlyeHNzX2dfZnJhbWVfaW50ZXJ2YWwgLSBHZXQg dGhlIGZyYW1lIGludGVydmFsCj4gPiArICogQHNkOiBWNEwyIFN1YiBkZXZpY2UKPiA+ICsgKiBA Zmk6IFBvaW50ZXIgdG8gVjRsMiBTdWIgZGV2aWNlIGZyYW1lIGludGVydmFsIHN0cnVjdHVyZQo+ ID4gKyAqCj4gPiArICogVGhpcyBmdW5jdGlvbiBpcyB1c2VkIHRvIGdldCB0aGUgZnJhbWUgaW50 ZXJ2YWwuCj4gPiArICogVGhlIGZyYW1lIHJhdGUgY2FuIGJlIGludGVncmFsIG9yIGZyYWN0aW9u YWwuCj4gPiArICogSW50ZWdyYWwgZnJhbWUgcmF0ZSBlLmcuIG51bWVyYXRvciA9IDEwMDAsIGRl bm9taW5hdG9yID0gMjQwMDAgPT4gMjQgZnBzCj4gPiArICogRnJhY3Rpb25hbCBmcmFtZSByYXRl IGUuZy4gbnVtZXJhdG9yID0gMTAwMSwgZGVub21pbmF0b3IgPSAyNDAwMCA9PiAyMy45NyBmcHMK PiA+ICsgKgo+ID4gKyAqIFJldHVybjogMCBvbiBzdWNjZXNzCj4gPiArICovCj4gPiArc3RhdGlj IGludCB4c2Rpcnhzc19nX2ZyYW1lX2ludGVydmFsKHN0cnVjdCB2NGwyX3N1YmRldiAqc2QsCj4g PiArCQkJCSAgICAgc3RydWN0IHY0bDJfc3ViZGV2X2ZyYW1lX2ludGVydmFsICpmaSkKPiA+ICt7 Cj4gPiArCXN0cnVjdCB4c2Rpcnhzc19zdGF0ZSAqeHNkaXJ4c3MgPSB0b194c2Rpcnhzc3N0YXRl KHNkKTsKPiA+ICsJdW5zaWduZWQgbG9uZyBmbGFnczsKPiA+ICsKPiA+ICsJaWYgKCF4c2Rpcnhz cy0+dmlkbG9ja2VkKSB7Cj4gPiArCQlkZXZfZXJyKHhzZGlyeHNzLT5kZXYsICJWaWRlbyBub3Qg bG9ja2VkIVxuIik7Cj4gPiArCQlyZXR1cm4gLUVJTlZBTDsKPiA+ICsJfQo+ID4gKwo+ID4gKwlz cGluX2xvY2tfaXJxc2F2ZSgmeHNkaXJ4c3MtPnNsb2NrLCBmbGFncyk7Cj4gPiArCWZpLT5pbnRl cnZhbCA9IHhzZGlyeHNzLT5mcmFtZV9pbnRlcnZhbDsKPiA+ICsJc3Bpbl91bmxvY2tfaXJxcmVz dG9yZSgmeHNkaXJ4c3MtPnNsb2NrLCBmbGFncyk7Cj4gPiArCj4gPiArCWRldl9kYmcoeHNkaXJ4 c3MtPmRldiwgImZyYW1lIHJhdGUgbnVtZXJhdG9yID0gJWQgZGVub21pbmF0b3IgPSAlZFxuIiwK PiA+ICsJCXhzZGlyeHNzLT5mcmFtZV9pbnRlcnZhbC5udW1lcmF0b3IsCj4gPiArCQl4c2Rpcnhz cy0+ZnJhbWVfaW50ZXJ2YWwuZGVub21pbmF0b3IpOwoKWW91IHNob3VsZCBwcmludCBmaS0+aW50 ZXJ2YWwsIG5vdCB4c2Rpcnhzcy0+ZnJhbWVfaW50ZXJ2YWwsIGFzIHlvdSdyZQpvdXRzaWRlIG9m IHRoZSBzcGlubG9jay4KCj4gPiArCXJldHVybiAwOwo+ID4gK30KPiA+ICsKPiA+ICsvKioKPiA+ ICsgKiB4c2Rpcnhzc19zX3N0cmVhbSAtIEl0IGlzIHVzZWQgdG8gc3RhcnQvc3RvcCB0aGUgc3Ry ZWFtaW5nLgo+ID4gKyAqIEBzZDogVjRMMiBTdWIgZGV2aWNlCj4gPiArICogQGVuYWJsZTogRmxh ZyAoVHJ1ZSAvIEZhbHNlKQo+ID4gKyAqCj4gPiArICogVGhpcyBmdW5jdGlvbiBjb250cm9scyB0 aGUgc3RhcnQgb3Igc3RvcCBvZiBzdHJlYW1pbmcgZm9yIHRoZQo+ID4gKyAqIFhpbGlueCBTREkg UnggU3Vic3lzdGVtLgo+ID4gKyAqCj4gPiArICogUmV0dXJuOiAwIG9uIHN1Y2Nlc3MsIGVycm9y cyBvdGhlcndpc2UKPiA+ICsgKi8KPiA+ICtzdGF0aWMgaW50IHhzZGlyeHNzX3Nfc3RyZWFtKHN0 cnVjdCB2NGwyX3N1YmRldiAqc2QsIGludCBlbmFibGUpCj4gPiArewo+ID4gKwlzdHJ1Y3QgeHNk aXJ4c3Nfc3RhdGUgKnhzZGlyeHNzID0gdG9feHNkaXJ4c3NzdGF0ZShzZCk7Cj4gPiArCXN0cnVj dCBkZXZpY2UgKmRldiA9IHhzZGlyeHNzLT5kZXY7Cj4gPiArCXVuc2lnbmVkIGxvbmcgZmxhZ3M7 Cj4gPiArCj4gPiArCXNwaW5fbG9ja19pcnFzYXZlKCZ4c2Rpcnhzcy0+c2xvY2ssIGZsYWdzKTsK PiA+ICsJaWYgKGVuYWJsZSA9PSB4c2Rpcnhzcy0+c3RyZWFtaW5nKSB7Cj4gPiArCQlzcGluX3Vu bG9ja19pcnFyZXN0b3JlKCZ4c2Rpcnhzcy0+c2xvY2ssIGZsYWdzKTsKPiA+ICsJCWRldl9kYmco ZGV2LCAiYWxyZWFkeSBpbiBzYW1lIHN0cmVhbWluZyBzdGF0ZSBhcyByZXF1ZXN0ZWRcbiIpOwo+ ID4gKwkJcmV0dXJuIDA7Cj4gPiArCX0KPiA+ICsKPiA+ICsJaWYgKGVuYWJsZSkgewo+ID4gKwkJ aWYgKCF4c2Rpcnhzcy0+dmlkbG9ja2VkKSB7Cj4gPiArCQkJc3Bpbl91bmxvY2tfaXJxcmVzdG9y ZSgmeHNkaXJ4c3MtPnNsb2NrLCBmbGFncyk7Cj4gPiArCQkJZGV2X2VycihkZXYsICJWaWRlbyBp cyBub3QgbG9ja2VkXG4iKTsKPiA+ICsJCQlyZXR1cm4gLUVJTlZBTDsKPiA+ICsJCX0KPiA+ICsJ CXhzZGlyeF9zdHJlYW1mbG93X2NvbnRyb2woeHNkaXJ4c3MsIHRydWUpOwo+ID4gKwl9IGVsc2Ug ewo+ID4gKwkJeHNkaXJ4X3N0cmVhbWZsb3dfY29udHJvbCh4c2RpcnhzcywgZmFsc2UpOwo+ID4g Kwl9Cj4gPiArCXNwaW5fdW5sb2NrX2lycXJlc3RvcmUoJnhzZGlyeHNzLT5zbG9jaywgZmxhZ3Mp Owo+ID4gKwlkZXZfZGJnKGRldiwgIlN0cmVhbWluZyAlc1xuIiwgZW5hYmxlID8gInN0YXJ0ZWQi IDogInN0b3BwZWQiKTsKPiA+ICsJcmV0dXJuIDA7Cj4gPiArfQo+ID4gKwo+ID4gKy8qKgo+ID4g KyAqIHhzZGlyeHNzX2dfaW5wdXRfc3RhdHVzIC0gSXQgaXMgdXNlZCB0byBkZXRlcm1pbmUgaWYg dGhlIHZpZGVvIHNpZ25hbAo+ID4gKyAqIGlzIHByZXNlbnQgLyBsb2NrZWQgb250byBvciBub3Qu Cj4gPiArICoKPiA+ICsgKiBAc2Q6IFY0TDIgU3ViIGRldmljZQo+ID4gKyAqIEBzdGF0dXM6IHN0 YXR1cyBvZiBzaWduYWwgbG9ja2VkCj4gPiArICoKPiA+ICsgKiBUaGlzIGlzIHVzZWQgdG8gZGV0 ZXJtaW5lIGlmIHRoZSB2aWRlbyBzaWduYWwgaXMgcHJlc2VudCBhbmQgbG9ja2VkIG9udG8KPiA+ ICsgKiBieSB0aGUgU0RJIFJ4IGNvcmUgb3Igbm90IGJhc2VkIG9uIHZpZGxvY2tlZCBmbGFnLgo+ ID4gKyAqCj4gPiArICogUmV0dXJuOiB6ZXJvIG9uIHN1Y2Nlc3MKPiA+ICsgKi8KPiA+ICtzdGF0 aWMgaW50IHhzZGlyeHNzX2dfaW5wdXRfc3RhdHVzKHN0cnVjdCB2NGwyX3N1YmRldiAqc2QsIHUz MiAqc3RhdHVzKQo+ID4gK3sKPiA+ICsJc3RydWN0IHhzZGlyeHNzX3N0YXRlICp4c2RpcnhzcyA9 IHRvX3hzZGlyeHNzc3RhdGUoc2QpOwo+ID4gKwl1bnNpZ25lZCBsb25nIGZsYWdzOwo+ID4gKwo+ ID4gKwlzcGluX2xvY2tfaXJxc2F2ZSgmeHNkaXJ4c3MtPnNsb2NrLCBmbGFncyk7Cj4gPiArCWlm ICgheHNkaXJ4c3MtPnZpZGxvY2tlZCkKPiA+ICsJCSpzdGF0dXMgPSBWNEwyX0lOX1NUX05PX1NZ TkMgfCBWNEwyX0lOX1NUX05PX1NJR05BTDsKPiA+ICsJZWxzZQo+ID4gKwkJKnN0YXR1cyA9IDA7 Cj4gPiArCj4gPiArCXNwaW5fdW5sb2NrX2lycXJlc3RvcmUoJnhzZGlyeHNzLT5zbG9jaywgZmxh Z3MpOwo+ID4gKwlyZXR1cm4gMDsKPiA+ICt9Cj4gPiArCj4gPiArc3RhdGljIHN0cnVjdCB2NGwy X21idXNfZnJhbWVmbXQgKgo+ID4gK19feHNkaXJ4c3NfZ2V0X3BhZF9mb3JtYXQoc3RydWN0IHhz ZGlyeHNzX3N0YXRlICp4c2RpcnhzcywKPiA+ICsJCQkgIHN0cnVjdCB2NGwyX3N1YmRldl9wYWRf Y29uZmlnICpjZmcsCj4gPiArCQkJICB1bnNpZ25lZCBpbnQgcGFkLCB1MzIgd2hpY2gpCj4gPiAr ewo+ID4gKwlzd2l0Y2ggKHdoaWNoKSB7Cj4gPiArCWNhc2UgVjRMMl9TVUJERVZfRk9STUFUX1RS WToKPiA+ICsJCXJldHVybiB2NGwyX3N1YmRldl9nZXRfdHJ5X2Zvcm1hdCgmeHNkaXJ4c3MtPnN1 YmRldiwgY2ZnLCBwYWQpOwo+ID4gKwljYXNlIFY0TDJfU1VCREVWX0ZPUk1BVF9BQ1RJVkU6Cj4g PiArCQlyZXR1cm4gJnhzZGlyeHNzLT5zcmNfZm9ybWF0Owo+ID4gKwlkZWZhdWx0Ogo+ID4gKwkJ cmV0dXJuIE5VTEw7Cj4gPiArCX0KPiA+ICt9Cj4gPiArCj4gPiArLyoqCj4gPiArICogeHNkaXJ4 c3NfaW5pdF9jZmcgLSBJbml0aWFsaXNlIHRoZSBwYWQgZm9ybWF0IGNvbmZpZyB0byBkZWZhdWx0 Cj4gPiArICogQHNkOiBQb2ludGVyIHRvIFY0TDIgU3ViIGRldmljZSBzdHJ1Y3R1cmUKPiA+ICsg KiBAY2ZnOiBQb2ludGVyIHRvIHN1YiBkZXZpY2UgcGFkIGluZm9ybWF0aW9uIHN0cnVjdHVyZQo+ ID4gKyAqCj4gPiArICogVGhpcyBmdW5jdGlvbiBpcyB1c2VkIHRvIGluaXRpYWxpemUgdGhlIHBh ZCBmb3JtYXQgd2l0aCB0aGUgZGVmYXVsdAo+ID4gKyAqIHZhbHVlcy4KPiA+ICsgKgo+ID4gKyAq IFJldHVybjogMCBvbiBzdWNjZXNzCj4gPiArICovCj4gPiArc3RhdGljIGludCB4c2Rpcnhzc19p bml0X2NmZyhzdHJ1Y3QgdjRsMl9zdWJkZXYgKnNkLAo+ID4gKwkJCSAgICAgc3RydWN0IHY0bDJf c3ViZGV2X3BhZF9jb25maWcgKmNmZykKPiA+ICt7Cj4gPiArCXN0cnVjdCB4c2Rpcnhzc19zdGF0 ZSAqeHNkaXJ4c3MgPSB0b194c2Rpcnhzc3N0YXRlKHNkKTsKPiA+ICsJc3RydWN0IHY0bDJfbWJ1 c19mcmFtZWZtdCAqZm9ybWF0Owo+ID4gKwo+ID4gKwlmb3JtYXQgPSB2NGwyX3N1YmRldl9nZXRf dHJ5X2Zvcm1hdChzZCwgY2ZnLCAwKTsKPiA+ICsJKmZvcm1hdCA9IHhzZGlyeHNzLT5kZWZhdWx0 X2Zvcm1hdDsKPiA+ICsKPiA+ICsJcmV0dXJuIDA7Cj4gPiArfQo+ID4gKwo+ID4gKy8qKgo+ID4g KyAqIHhzZGlyeHNzX2dldF9zZXRfZm9ybWF0IC0gVGhpcyBpcyB1c2VkIHRvIGdldC9zZXQgdGhl IHBhZCBmb3JtYXQKPiA+ICsgKiBAc2Q6IFBvaW50ZXIgdG8gVjRMMiBTdWIgZGV2aWNlIHN0cnVj dHVyZQo+ID4gKyAqIEBjZmc6IFBvaW50ZXIgdG8gc3ViIGRldmljZSBwYWQgaW5mb3JtYXRpb24g c3RydWN0dXJlCj4gPiArICogQGZtdDogUG9pbnRlciB0byBwYWQgbGV2ZWwgbWVkaWEgYnVzIGZv cm1hdAo+ID4gKyAqCj4gPiArICogVGhpcyBmdW5jdGlvbiBpcyB1c2VkIHRvIGdldCBhbmQgc2V0 IHRoZSBwYWQgZm9ybWF0Lgo+ID4gKyAqIFNpbmNlIHRoZSBwYWQgZm9ybWF0IGlzIGZpeGVkIGlu IGhhcmR3YXJlLCBpdCBjYW4ndCBiZQo+ID4gKyAqIG1vZGlmaWVkIG9uIHJ1biB0aW1lLiBTbyBz ZXQgYW5kIGdldCBhcmUgc2FtZS4KPiA+ICsgKgo+ID4gKyAqIFJldHVybjogMCBvbiBzdWNjZXNz Cj4gPiArICovCj4gPiArc3RhdGljIGludCB4c2Rpcnhzc19nZXRfc2V0X2Zvcm1hdChzdHJ1Y3Qg djRsMl9zdWJkZXYgKnNkLAo+ID4gKwkJCQkgICBzdHJ1Y3QgdjRsMl9zdWJkZXZfcGFkX2NvbmZp ZyAqY2ZnLAo+ID4gKwkJCQkgICBzdHJ1Y3QgdjRsMl9zdWJkZXZfZm9ybWF0ICpmbXQpCj4gPiAr ewo+ID4gKwlzdHJ1Y3QgeHNkaXJ4c3Nfc3RhdGUgKnhzZGlyeHNzID0gdG9feHNkaXJ4c3NzdGF0 ZShzZCk7Cj4gPiArCXVuc2lnbmVkIGxvbmcgZmxhZ3M7Cj4gPiArCj4gPiArCXNwaW5fbG9ja19p cnFzYXZlKCZ4c2Rpcnhzcy0+c2xvY2ssIGZsYWdzKTsKPiA+ICsJaWYgKCF4c2Rpcnhzcy0+dmlk bG9ja2VkKSB7Cj4gPiArCQlzcGluX3VubG9ja19pcnFyZXN0b3JlKCZ4c2Rpcnhzcy0+c2xvY2ss IGZsYWdzKTsKPiA+ICsJCWRldl9lcnIoeHNkaXJ4c3MtPmRldiwgIlZpZGVvIG5vdCBsb2NrZWQh XG4iKTsKPiA+ICsJCXJldHVybiAtRUlOVkFMOwo+ID4gKwl9Cj4gPiArCj4gPiArCWZtdC0+Zm9y bWF0ID0gKl9feHNkaXJ4c3NfZ2V0X3BhZF9mb3JtYXQoeHNkaXJ4c3MsIGNmZywKPiA+ICsJCQkJ CQkgZm10LT5wYWQsIGZtdC0+d2hpY2gpOwo+ID4gKwo+ID4gKwlzcGluX3VubG9ja19pcnFyZXN0 b3JlKCZ4c2Rpcnhzcy0+c2xvY2ssIGZsYWdzKTsKPiA+ICsJZGV2X2RiZyh4c2Rpcnhzcy0+ZGV2 LAo+ID4gKwkJInN0cmVhbSB3aWR0aCAlZCBoZWlnaHQgJWQgY29kZSAlZCBmaWVsZCAlZCBjb2xv cnNwYWNlICVkIHhmZXJfZnVuYyAlZCBxdWFudGl6YXRpb24gJWRcbiIsCj4gPiArCQlmbXQtPmZv cm1hdC53aWR0aCwgZm10LT5mb3JtYXQuaGVpZ2h0LAo+ID4gKwkJZm10LT5mb3JtYXQuY29kZSwg Zm10LT5mb3JtYXQuZmllbGQsCj4gPiArCQlmbXQtPmZvcm1hdC5jb2xvcnNwYWNlLCBmbXQtPmZv cm1hdC54ZmVyX2Z1bmMsCj4gPiArCQlmbXQtPmZvcm1hdC5xdWFudGl6YXRpb24pOwo+ID4gKwly ZXR1cm4gMDsKPiA+ICt9Cj4gPiArCj4gPiArLyoqCj4gPiArICogeHNkaXJ4c3NfZW51bV9tYnVz X2NvZGUgLSBIYW5kbGUgcGl4ZWwgZm9ybWF0IGVudW1lcmF0aW9uCj4gPiArICogQHNkOiBwb2lu dGVyIHRvIHY0bDIgc3ViZGV2IHN0cnVjdHVyZQo+ID4gKyAqIEBjZmc6IFY0TDIgc3ViZGV2IHBh ZCBjb25maWd1cmF0aW9uCj4gPiArICogQGNvZGU6IHBvaW50ZXIgdG8gdjRsMl9zdWJkZXZfbWJ1 c19jb2RlX2VudW0gc3RydWN0dXJlCj4gPiArICoKPiA+ICsgKiBSZXR1cm46IC1FSU5WQUwgb3Ig emVybyBvbiBzdWNjZXNzCj4gPiArICovCj4gPiArc3RhdGljIGludCB4c2Rpcnhzc19lbnVtX21i dXNfY29kZShzdHJ1Y3QgdjRsMl9zdWJkZXYgKnNkLAo+ID4gKwkJCQkgICBzdHJ1Y3QgdjRsMl9z dWJkZXZfcGFkX2NvbmZpZyAqY2ZnLAo+ID4gKwkJCQkgICBzdHJ1Y3QgdjRsMl9zdWJkZXZfbWJ1 c19jb2RlX2VudW0gKmNvZGUpCj4gPiArewo+ID4gKwlzdHJ1Y3QgeHNkaXJ4c3Nfc3RhdGUgKnhz ZGlyeHNzID0gdG9feHNkaXJ4c3NzdGF0ZShzZCk7Cj4gPiArCXUzMiBpbmRleCA9IGNvZGUtPmlu ZGV4Owo+ID4gKwl1MzIgbWF4aW5kZXg7Cj4gPiArCj4gPiArCWlmICh4c2Rpcnhzcy0+YnBjID09 IDEwKQo+ID4gKwkJbWF4aW5kZXggPSBBUlJBWV9TSVpFKHhzZGlyeHNzXzEwYnBjX21idXNfZm10 cyk7Cj4gPiArCWVsc2UKPiA+ICsJCW1heGluZGV4ID0gQVJSQVlfU0laRSh4c2Rpcnhzc18xMmJw Y19tYnVzX2ZtdHMpOwo+ID4gKwo+ID4gKwlpZiAoY29kZS0+cGFkIHx8IGluZGV4ID49IG1heGlu ZGV4KQo+ID4gKwkJcmV0dXJuIC1FSU5WQUw7Cj4gPiArCj4gPiArCWlmICh4c2Rpcnhzcy0+YnBj ID09IDEwKQo+ID4gKwkJY29kZS0+Y29kZSA9IHhzZGlyeHNzXzEwYnBjX21idXNfZm10c1tpbmRl eF07Cj4gPiArCWVsc2UKPiA+ICsJCWNvZGUtPmNvZGUgPSB4c2Rpcnhzc18xMmJwY19tYnVzX2Zt dHNbaW5kZXhdOwo+ID4gKwo+ID4gKwlyZXR1cm4gMDsKPiA+ICt9Cj4gPiArCj4gPiArLyoqCj4g PiArICogeHNkaXJ4c3NfZW51bV9kdl90aW1pbmdzIC0gRW51bWVyYXRlIGFsbCB0aGUgc3VwcG9y dGVkIERWIHRpbWluZ3MKPiA+ICsgKiBAc2Q6IHBvaW50ZXIgdG8gdjRsMiBzdWJkZXYgc3RydWN0 dXJlCj4gPiArICogQHRpbWluZ3M6IERWIHRpbWluZ3Mgc3RydWN0dXJlIHRvIGJlIHJldHVybmVk Lgo+ID4gKyAqCj4gPiArICogUmV0dXJuOiAtRUlOVkFMIGluY2FzZSBvZiBpbnZhbGlkIGluZGV4 IGFuZCBwYWQgb3IgemVybyBvbiBzdWNjZXNzCj4gPiArICovCj4gPiArc3RhdGljIGludCB4c2Rp cnhzc19lbnVtX2R2X3RpbWluZ3Moc3RydWN0IHY0bDJfc3ViZGV2ICpzZCwKPiA+ICsJCQkJICAg IHN0cnVjdCB2NGwyX2VudW1fZHZfdGltaW5ncyAqdGltaW5ncykKPiA+ICt7Cj4gPiArCWlmICh0 aW1pbmdzLT5pbmRleCA+PSBBUlJBWV9TSVpFKGZtdF9jYXApKQo+ID4gKwkJcmV0dXJuIC1FSU5W QUw7Cj4gPiArCj4gPiArCWlmICh0aW1pbmdzLT5wYWQgIT0gMCkKPiA+ICsJCXJldHVybiAtRUlO VkFMOwo+ID4gKwo+ID4gKwl0aW1pbmdzLT50aW1pbmdzID0gZm10X2NhcFt0aW1pbmdzLT5pbmRl eF07Cj4gPiArCXJldHVybiAwOwo+ID4gK30KPiA+ICsKPiA+ICsvKioKPiA+ICsgKiB4c2Rpcnhz c19xdWVyeV9kdl90aW1pbmdzIC0gUXVlcnkgZm9yIHRoZSBjdXJyZW50IERWIHRpbWluZ3MKPiA+ ICsgKiBAc2Q6IHBvaW50ZXIgdG8gdjRsMiBzdWJkZXYgc3RydWN0dXJlCj4gPiArICogQHRpbWlu Z3M6IERWIHRpbWluZ3Mgc3RydWN0dXJlIHRvIGJlIHJldHVybmVkLgo+ID4gKyAqCj4gPiArICog UmV0dXJuOiAtRU5PTENLIHdoZW4gdmlkZW8gaXMgbm90IGxvY2tlZCwgLUVSQU5HRSB3aGVuIGNv cnJlc3BvbmRpbmcgdGltaW5nCj4gPiArICogZW50cnkgaXMgbm90IGZvdW5kIG9yIHplcm8gb24g c3VjY2Vzcy4KPiA+ICsgKi8KPiA+ICtzdGF0aWMgaW50IHhzZGlyeHNzX3F1ZXJ5X2R2X3RpbWlu Z3Moc3RydWN0IHY0bDJfc3ViZGV2ICpzZCwKPiA+ICsJCQkJICAgICBzdHJ1Y3QgdjRsMl9kdl90 aW1pbmdzICp0aW1pbmdzKQo+ID4gK3sKPiA+ICsJc3RydWN0IHhzZGlyeHNzX3N0YXRlICpzdGF0 ZSA9IHRvX3hzZGlyeHNzc3RhdGUoc2QpOwo+ID4gKwl1bnNpZ25lZCBpbnQgaTsKPiA+ICsJdW5z aWduZWQgbG9uZyBmbGFnczsKPiA+ICsKPiA+ICsJc3Bpbl9sb2NrX2lycXNhdmUoJnN0YXRlLT5z bG9jaywgZmxhZ3MpOwo+ID4gKwlpZiAoIXN0YXRlLT52aWRsb2NrZWQpIHsKPiA+ICsJCXNwaW5f dW5sb2NrX2lycXJlc3RvcmUoJnN0YXRlLT5zbG9jaywgZmxhZ3MpOwo+ID4gKwkJcmV0dXJuIC1F Tk9MQ0s7Cj4gPiArCX0KPiA+ICsKPiA+ICsJZm9yIChpID0gMDsgaSA8IEFSUkFZX1NJWkUoeHNk aXJ4c3NfZHZfdGltaW5ncyk7IGkrKykgewo+ID4gKwkJaWYgKHN0YXRlLT5mb3JtYXQud2lkdGgg PT0geHNkaXJ4c3NfZHZfdGltaW5nc1tpXS53aWR0aCAmJgo+ID4gKwkJICAgIHN0YXRlLT5mb3Jt YXQuaGVpZ2h0ID09IHhzZGlyeHNzX2R2X3RpbWluZ3NbaV0uaGVpZ2h0ICYmCj4gPiArCQkgICAg c3RhdGUtPmZyYW1lX2ludGVydmFsLmRlbm9taW5hdG9yID09Cj4gPiArCQkgICAgKHhzZGlyeHNz X2R2X3RpbWluZ3NbaV0uZnBzICogMTAwMCkpIHsKPiA+ICsJCQkqdGltaW5ncyA9IHhzZGlyeHNz X2R2X3RpbWluZ3NbaV0udGltaW5nOwo+ID4gKwkJCXN0YXRlLT5kZXRlY3RlZF90aW1pbmdzX2lu ZGV4ID0gaTsKPiA+ICsJCQlzcGluX3VubG9ja19pcnFyZXN0b3JlKCZzdGF0ZS0+c2xvY2ssIGZs YWdzKTsKPiA+ICsJCQlyZXR1cm4gMDsKPiA+ICsJCX0KPiA+ICsJfQo+IAo+IFRoaXMgbGltaXRz IHRoZSBhdmFpbGFibGUgdGltaW5ncyB0byB0aG9zZSBleHBsaWNpdGx5IHN1cHBvcnRlZCBieSB0 aGlzCj4gZHJpdmVyLiBJcyB0aGF0IGludGVuZGVkPyBXaGF0IGl0IHlvdSByZWNlaXZlIHNvbWV0 aGluZyB0aGF0J3Mgbm90IGluIHRoaXMKPiBsaXN0PyBEbyB5b3Ugc3RpbGwgd2FudCB0byBiZSBh YmxlIHRvIHJlY2VpdmUgaXQ/Cj4gCj4gPiArCXNwaW5fdW5sb2NrX2lycXJlc3RvcmUoJnN0YXRl LT5zbG9jaywgZmxhZ3MpOwo+ID4gKwo+ID4gKwlyZXR1cm4gLUVSQU5HRTsKPiA+ICt9Cj4gPiAr Cj4gPiArc3RhdGljIGludCB4c2Rpcnhzc19zX2R2X3RpbWluZ3Moc3RydWN0IHY0bDJfc3ViZGV2 ICpzZCwKPiA+ICsJCQkJIHN0cnVjdCB2NGwyX2R2X3RpbWluZ3MgKnRpbWluZ3MpCj4gPiArewo+ ID4gKwlzdHJ1Y3QgeHNkaXJ4c3Nfc3RhdGUgKnN0YXRlID0gdG9feHNkaXJ4c3NzdGF0ZShzZCk7 Cj4gPiArCXUzMiBpID0gc3RhdGUtPmRldGVjdGVkX3RpbWluZ3NfaW5kZXg7Cj4gPiArCXVuc2ln bmVkIGxvbmcgZmxhZ3M7Cj4gPiArCj4gPiArCXNwaW5fbG9ja19pcnFzYXZlKCZzdGF0ZS0+c2xv Y2ssIGZsYWdzKTsKPiA+ICsJaWYgKCFzdGF0ZS0+dmlkbG9ja2VkKSB7Cj4gPiArCQlzcGluX3Vu bG9ja19pcnFyZXN0b3JlKCZzdGF0ZS0+c2xvY2ssIGZsYWdzKTsKPiA+ICsJCXJldHVybiAtRUlO VkFMOwo+ID4gKwl9Cj4gPiArCj4gPiArCS8qIGlucHV0IHRpbWluZyBzaG91bGQgbWF0Y2ggcXVl cnkgZHZfdGltaW5nICovCj4gPiArCWlmICghdjRsMl9tYXRjaF9kdl90aW1pbmdzKHRpbWluZ3Ms Cj4gPiArCQkJCSAgICZ4c2Rpcnhzc19kdl90aW1pbmdzW2ldLnRpbWluZywKPiA+ICsJCQkJICAg MCwgZmFsc2UpKSB7Cj4gPiArCQlzcGluX3VubG9ja19pcnFyZXN0b3JlKCZzdGF0ZS0+c2xvY2ss IGZsYWdzKTsKPiA+ICsJCXJldHVybiAtRUlOVkFMOwo+ID4gKwl9Cj4gPiArCj4gPiArCXN0YXRl LT5jdXJyZW50X3RpbWluZ3MgPSAqdGltaW5nczsKPiA+ICsKPiA+ICsJLyogVXBkYXRlIHRoZSBt ZWRpYSBidXMgZm9ybWF0ICovCj4gPiArCXN0YXRlLT5zcmNfZm9ybWF0ID0gc3RhdGUtPmZvcm1h dDsKPiA+ICsJc3Bpbl91bmxvY2tfaXJxcmVzdG9yZSgmc3RhdGUtPnNsb2NrLCBmbGFncyk7Cj4g PiArCj4gPiArCXJldHVybiAwOwo+ID4gK30KPiA+ICsKPiA+ICtzdGF0aWMgaW50IHhzZGlyeHNz X2dfZHZfdGltaW5ncyhzdHJ1Y3QgdjRsMl9zdWJkZXYgKnNkLAo+ID4gKwkJCQkgc3RydWN0IHY0 bDJfZHZfdGltaW5ncyAqdGltaW5ncykKPiA+ICt7Cj4gPiArCXN0cnVjdCB4c2Rpcnhzc19zdGF0 ZSAqc3RhdGUgPSB0b194c2Rpcnhzc3N0YXRlKHNkKTsKPiA+ICsKPiA+ICsJKnRpbWluZ3MgPSBz dGF0ZS0+Y3VycmVudF90aW1pbmdzOwo+ID4gKwlyZXR1cm4gMDsKPiA+ICt9Cj4gPiArCj4gPiAr c3RhdGljIGludCB4c2Rpcnhzc19kdl90aW1pbmdzX2NhcChzdHJ1Y3QgdjRsMl9zdWJkZXYgKnNk LAo+ID4gKwkJCQkgICBzdHJ1Y3QgdjRsMl9kdl90aW1pbmdzX2NhcCAqY2FwKQo+ID4gK3sKPiA+ ICsJaWYgKGNhcC0+cGFkICE9IDApCj4gPiArCQlyZXR1cm4gLUVJTlZBTDsKPiA+ICsKPiA+ICsJ KmNhcCA9IHhzZGlyeHNzX3RpbWluZ3NfY2FwOwo+ID4gKwlyZXR1cm4gMDsKPiA+ICt9Cj4gPiAr Cj4gPiArLyogLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0t LS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0KPiA+ICsgKiBNZWRpYSBPcGVyYXRpb25zCj4g PiArICovCj4gPiArCj4gPiArc3RhdGljIGNvbnN0IHN0cnVjdCBtZWRpYV9lbnRpdHlfb3BlcmF0 aW9ucyB4c2Rpcnhzc19tZWRpYV9vcHMgPSB7Cj4gPiArCS5saW5rX3ZhbGlkYXRlID0gdjRsMl9z dWJkZXZfbGlua192YWxpZGF0ZQo+ID4gK307Cj4gPiArCj4gPiArc3RhdGljIGNvbnN0IHN0cnVj dCB2NGwyX2N0cmxfb3BzIHhzZGlyeHNzX2N0cmxfb3BzID0gewo+ID4gKwkuZ192b2xhdGlsZV9j dHJsID0geHNkaXJ4c3NfZ192b2xhdGlsZV9jdHJsLAo+ID4gKwkuc19jdHJsCT0geHNkaXJ4c3Nf c19jdHJsCj4gPiArfTsKPiA+ICsKPiA+ICtzdGF0aWMgY29uc3Qgc3RydWN0IHY0bDJfY3RybF9j b25maWcgeHNkaXJ4c3NfZWRoX2N0cmxzW10gPSB7Cj4gPiArCXsKPiA+ICsJCS5vcHMJPSAmeHNk aXJ4c3NfY3RybF9vcHMsCj4gPiArCQkuaWQJPSBWNEwyX0NJRF9YSUxJTlhfU0RJUlhfRURIX0VS Uk9SX1NPVVJDRVMsCj4gPiArCQkubmFtZQk9ICJTREkgUnggOiBFREggRXJyb3IgQ291bnQgRW5h YmxlIiwKPiAKPiBObyBzcGFjZSBiZWZvcmUgJzonLgo+IAo+ID4gKwkJLnR5cGUJPSBWNEwyX0NU UkxfVFlQRV9CSVRNQVNLLAo+ID4gKwkJLm1pbgk9IDAsCj4gPiArCQkubWF4CT0gWFNESVJYX0VE SF9BTExFUlJfTUFTSywKPiA+ICsJCS5kZWYJPSAwLAo+ID4gKwl9LCB7Cj4gPiArCQkub3BzCT0g JnhzZGlyeHNzX2N0cmxfb3BzLAo+ID4gKwkJLmlkCT0gVjRMMl9DSURfWElMSU5YX1NESVJYX0VE SF9FUlJDTlQsCj4gPiArCQkubmFtZQk9ICJTREkgUnggOiBFREggRXJyb3IgQ291bnQiLAo+ID4g KwkJLnR5cGUJPSBWNEwyX0NUUkxfVFlQRV9JTlRFR0VSLAo+ID4gKwkJLm1pbgk9IDAsCj4gPiAr CQkubWF4CT0gMHhmZmZmLAo+ID4gKwkJLnN0ZXAJPSAxLAo+ID4gKwkJLmRlZgk9IDAsCj4gPiAr CQkuZmxhZ3MgID0gVjRMMl9DVFJMX0ZMQUdfVk9MQVRJTEUgfCBWNEwyX0NUUkxfRkxBR19SRUFE X09OTFksCj4gPiArCX0sIHsKPiA+ICsJCS5vcHMJPSAmeHNkaXJ4c3NfY3RybF9vcHMsCj4gPiAr CQkuaWQJPSBWNEwyX0NJRF9YSUxJTlhfU0RJUlhfRURIX1NUQVRVUywKPiA+ICsJCS5uYW1lCT0g IlNESSBSeCA6IEVESCBTdGF0dXMiLAo+ID4gKwkJLnR5cGUJPSBWNEwyX0NUUkxfVFlQRV9JTlRF R0VSLAo+IAo+IFRoaXMgc2hvdWxkIGJlIGEgYml0bWFzayB0eXBlLiBTaG91bGQgdGhpcyBiZSBh IGNvbnRyb2wgYXQgYWxsPyBJc24ndCB0aGlzIG1vcmUKPiBzb21ldGhpbmcgdG8gbG9nIHdpdGgg bG9nX3N0YXR1cz8gSXMgdGhpcyBzb21ldGhpbmcgdGhhdCBhbiBhcHBsaWNhdGlvbiBuZWVkcyB0 bwo+IHVzZSwgb3IgaXMgaXQganVzdCBhIGRlYnVnZ2luZyBhaWQ/IEl0IGZlZWxzIGxpa2UgdGhl IGxhdHRlci4KPiAKPiA+ICsJCS5taW4JPSAwLAo+ID4gKwkJLm1heAk9IDB4ZmZmZmZmZmYsCj4g PiArCQkuc3RlcAk9IDEsCj4gPiArCQkuZGVmCT0gMCwKPiA+ICsJCS5mbGFncyAgPSBWNEwyX0NU UkxfRkxBR19WT0xBVElMRSB8IFY0TDJfQ1RSTF9GTEFHX1JFQURfT05MWSwKPiA+ICsJfQo+ID4g K307Cj4gPiArCj4gPiArc3RhdGljIGNvbnN0IHN0cnVjdCB2NGwyX2N0cmxfY29uZmlnIHhzZGly eHNzX2N0cmxzW10gPSB7Cj4gPiArCXsKPiA+ICsJCS5vcHMJPSAmeHNkaXJ4c3NfY3RybF9vcHMs Cj4gPiArCQkuaWQJPSBWNEwyX0NJRF9YSUxJTlhfU0RJUlhfRlJBTUVSLAo+ID4gKwkJLm5hbWUJ PSAiU0RJIFJ4IDogRW5hYmxlIEZyYW1lciIsCj4gPiArCQkudHlwZQk9IFY0TDJfQ1RSTF9UWVBF X0JPT0xFQU4sCj4gPiArCQkubWluCT0gZmFsc2UsCj4gPiArCQkubWF4CT0gdHJ1ZSwKPiA+ICsJ CS5zdGVwCT0gMSwKPiA+ICsJCS5kZWYJPSB0cnVlLAo+ID4gKwl9LCB7Cj4gPiArCQkub3BzCT0g JnhzZGlyeHNzX2N0cmxfb3BzLAo+ID4gKwkJLmlkCT0gVjRMMl9DSURfWElMSU5YX1NESVJYX1ZJ RExPQ0tfV0lORE9XLAo+ID4gKwkJLm5hbWUJPSAiU0RJIFJ4IDogVmlkZW8gTG9jayBXaW5kb3ci LAo+ID4gKwkJLnR5cGUJPSBWNEwyX0NUUkxfVFlQRV9JTlRFR0VSLAo+ID4gKwkJLm1pbgk9IDAs Cj4gPiArCQkubWF4CT0gMHhmZmZmZmZmZiwKPiAKPiBtYXggc2hvdWxkIGJlIDB4N2ZmZmZmZmYg c2luY2UgdGhpcyBpcyBhIHMzMi4KPiAKPiA+ICsJCS5zdGVwCT0gMSwKPiA+ICsJCS5kZWYJPSBY U0RJUlhfREVGQVVMVF9WSURFT19MT0NLX1dJTkRPVywKPiA+ICsJfSwgewo+ID4gKwkJLm9wcwk9 ICZ4c2Rpcnhzc19jdHJsX29wcywKPiA+ICsJCS5pZAk9IFY0TDJfQ0lEX1hJTElOWF9TRElSWF9T RUFSQ0hfTU9ERVMsCj4gPiArCQkubmFtZQk9ICJTREkgUnggOiBNb2RlcyBzZWFyY2ggTWFzayIs Cj4gCj4gc2VhcmNoIC0+IFNlYXJjaAo+IAo+ID4gKwkJLnR5cGUJPSBWNEwyX0NUUkxfVFlQRV9C SVRNQVNLLAo+ID4gKwkJLm1pbgk9IDAsCj4gPiArCQkubWF4CT0gWFNESVJYX0RFVEVDVF9BTExf TU9ERVMsCj4gPiArCQkuZGVmCT0gWFNESVJYX0RFVEVDVF9BTExfTU9ERVMsCj4gPiArCX0sIHsK PiA+ICsJCS5vcHMJPSAmeHNkaXJ4c3NfY3RybF9vcHMsCj4gPiArCQkuaWQJPSBWNEwyX0NJRF9Y SUxJTlhfU0RJUlhfTU9ERV9ERVRFQ1QsCj4gPiArCQkubmFtZQk9ICJTREkgUnggOiBNb2RlIERl dGVjdCBTdGF0dXMiLAo+IAo+IE1vZGUgRGV0ZWN0IFN0YXR1cyAtPiAgRGV0ZWN0ZWQgTW9kZQo+ IAo+ID4gKwkJLnR5cGUJPSBWNEwyX0NUUkxfVFlQRV9JTlRFR0VSLAo+IAo+IFRoaXMgaXMgcmVh bGx5IGEgbWVudSBjb250cm9sLgo+IAo+ID4gKwkJLm1pbgk9IFhTRElSWF9NT0RFX1NEX09GRlNF VCwKPiA+ICsJCS5tYXgJPSBYU0RJUlhfTU9ERV8xMkdGX09GRlNFVCwKPiA+ICsJCS5zdGVwCT0g MSwKPiA+ICsJCS5mbGFncyAgPSBWNEwyX0NUUkxfRkxBR19WT0xBVElMRSB8IFY0TDJfQ1RSTF9G TEFHX1JFQURfT05MWSwKPiA+ICsJfSwgewo+ID4gKwkJLm9wcwk9ICZ4c2Rpcnhzc19jdHJsX29w cywKPiA+ICsJCS5pZAk9IFY0TDJfQ0lEX1hJTElOWF9TRElSWF9DUkMsCj4gPiArCQkubmFtZQk9 ICJTREkgUnggOiBDUkMgRXJyb3Igc3RhdHVzIiwKPiA+ICsJCS50eXBlCT0gVjRMMl9DVFJMX1RZ UEVfSU5URUdFUiwKPiAKPiBUaGlzIGlzIHJlYWxseSB0d28gY29udHJvbHMgYmFzZWQgb24gdGhl IGRlc2NyaXB0aW9uIGluIHRoZSBoZWFkZXI6Cj4gCj4gT25lIGJpdG1hc2sgZm9yIHRoZSAxNiBk YXRhIHN0cmVhbXMgYW5kIG9uZSBhY2N1bXVsYXRlZCBlcnJvciBjb3VudC4KCkhhbnMsIGFzIHRo aXMgaXMgaGlnaGx5IGRldmljZS1zcGVjaWZpYywgYW5kIHRoZSB0d28gdmFsdWVzIG5lZWQgdG8g YmUKcmVhZCB0b2dldGhlciwgZG8gd2UgcmVhbGx5IHdhbnQgdG8gbWFuZGF0ZSBhbGwgdGhlIGNv bXBsZXhpdHkgb2YKY3JlYXRpbmcgdHdvIGNvbnRyb2xzIGluIGEgY2x1c3RlciA/IEl0IHNlZW1z IG92ZXJraWxsIHRvIG1lLgoKPiA+ICsJCS5taW4JPSAwLAo+ID4gKwkJLm1heAk9IDB4ZmZmZmZm ZmYsCj4gPiArCQkuc3RlcAk9IDEsCj4gPiArCQkuZGVmCT0gMCwKPiA+ICsJCS5mbGFncyAgPSBW NEwyX0NUUkxfRkxBR19WT0xBVElMRSB8IFY0TDJfQ1RSTF9GTEFHX1JFQURfT05MWSwKPiA+ICsJ fSwgewo+ID4gKwkJLm9wcwk9ICZ4c2Rpcnhzc19jdHJsX29wcywKPiA+ICsJCS5pZAk9IFY0TDJf Q0lEX1hJTElOWF9TRElSWF9UU19JU19JTlRFUkxBQ0VELAo+ID4gKwkJLm5hbWUJPSAiU0RJIFJ4 IDogVFMgaXMgSW50ZXJsYWNlZCIsCj4gPiArCQkudHlwZQk9IFY0TDJfQ1RSTF9UWVBFX0JPT0xF QU4sCj4gPiArCQkubWluCT0gZmFsc2UsCj4gPiArCQkubWF4CT0gdHJ1ZSwKPiA+ICsJCS5kZWYJ PSBmYWxzZSwKPiA+ICsJCS5zdGVwCT0gMSwKPiA+ICsJCS5mbGFncyAgPSBWNEwyX0NUUkxfRkxB R19WT0xBVElMRSB8IFY0TDJfQ1RSTF9GTEFHX1JFQURfT05MWSwKPiA+ICsJfSwKPiA+ICt9Owo+ ID4gKwo+ID4gK3N0YXRpYyBjb25zdCBzdHJ1Y3QgdjRsMl9zdWJkZXZfY29yZV9vcHMgeHNkaXJ4 c3NfY29yZV9vcHMgPSB7Cj4gPiArCS5sb2dfc3RhdHVzID0geHNkaXJ4c3NfbG9nX3N0YXR1cywK PiA+ICsJLnN1YnNjcmliZV9ldmVudCA9IHhzZGlyeHNzX3N1YnNjcmliZV9ldmVudCwKPiA+ICsJ LnVuc3Vic2NyaWJlX2V2ZW50ID0gdjRsMl9ldmVudF9zdWJkZXZfdW5zdWJzY3JpYmUsCj4gPiAr fTsKPiA+ICsKPiA+ICtzdGF0aWMgY29uc3Qgc3RydWN0IHY0bDJfc3ViZGV2X3ZpZGVvX29wcyB4 c2Rpcnhzc192aWRlb19vcHMgPSB7Cj4gPiArCS5nX2ZyYW1lX2ludGVydmFsID0geHNkaXJ4c3Nf Z19mcmFtZV9pbnRlcnZhbCwKPiA+ICsJLnNfc3RyZWFtID0geHNkaXJ4c3Nfc19zdHJlYW0sCj4g PiArCS5nX2lucHV0X3N0YXR1cyA9IHhzZGlyeHNzX2dfaW5wdXRfc3RhdHVzLAo+ID4gKwkucXVl cnlfZHZfdGltaW5ncyA9IHhzZGlyeHNzX3F1ZXJ5X2R2X3RpbWluZ3MsCj4gPiArCS5nX2R2X3Rp bWluZ3MgPSB4c2Rpcnhzc19nX2R2X3RpbWluZ3MsCj4gPiArCS5zX2R2X3RpbWluZ3MgPSB4c2Rp cnhzc19zX2R2X3RpbWluZ3MsCj4gPiArfTsKPiA+ICsKPiA+ICtzdGF0aWMgY29uc3Qgc3RydWN0 IHY0bDJfc3ViZGV2X3BhZF9vcHMgeHNkaXJ4c3NfcGFkX29wcyA9IHsKPiA+ICsJLmluaXRfY2Zn ID0geHNkaXJ4c3NfaW5pdF9jZmcsCj4gPiArCS5nZXRfZm10ID0geHNkaXJ4c3NfZ2V0X3NldF9m b3JtYXQsCj4gPiArCS5zZXRfZm10ID0geHNkaXJ4c3NfZ2V0X3NldF9mb3JtYXQsCj4gPiArCS5l bnVtX21idXNfY29kZSA9IHhzZGlyeHNzX2VudW1fbWJ1c19jb2RlLAo+ID4gKwkuZW51bV9kdl90 aW1pbmdzID0geHNkaXJ4c3NfZW51bV9kdl90aW1pbmdzLAo+ID4gKwkuZHZfdGltaW5nc19jYXAg PSB4c2Rpcnhzc19kdl90aW1pbmdzX2NhcCwKPiA+ICt9Owo+ID4gKwo+ID4gK3N0YXRpYyBjb25z dCBzdHJ1Y3QgdjRsMl9zdWJkZXZfb3BzIHhzZGlyeHNzX29wcyA9IHsKPiA+ICsJLmNvcmUgPSAm eHNkaXJ4c3NfY29yZV9vcHMsCj4gPiArCS52aWRlbyA9ICZ4c2Rpcnhzc192aWRlb19vcHMsCj4g PiArCS5wYWQgPSAmeHNkaXJ4c3NfcGFkX29wcwo+ID4gK307Cj4gPiArCj4gPiArLyogLS0tLS0t LS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0t LS0tLS0tLS0tLS0tLS0KPiA+ICsgKiBQbGF0Zm9ybSBEZXZpY2UgRHJpdmVyCj4gPiArICovCj4g PiArCj4gPiArc3RhdGljIGludCB4c2Rpcnhzc19wYXJzZV9vZihzdHJ1Y3QgeHNkaXJ4c3Nfc3Rh dGUgKnhzZGlyeHNzKQo+ID4gK3sKPiA+ICsJc3RydWN0IGRldmljZV9ub2RlICpub2RlID0geHNk aXJ4c3MtPmRldi0+b2Zfbm9kZTsKPiA+ICsJc3RydWN0IGRldmljZSAqZGV2ID0geHNkaXJ4c3Mt PmRldjsKPiA+ICsJaW50IHJldDsKPiA+ICsKPiA+ICsJeHNkaXJ4c3MtPmluY2x1ZGVfZWRoID0g b2ZfcHJvcGVydHlfcmVhZF9ib29sKG5vZGUsICJ4bG54LGluY2x1ZGUtZWRoIik7Cj4gPiArCWRl dl9kYmcoZGV2LCAiRURIIHByb3BlcnR5ID0gJXNcbiIsCj4gPiArCQl4c2Rpcnhzcy0+aW5jbHVk ZV9lZGggPyAiUHJlc2VudCIgOiAiQWJzZW50Iik7Cj4gPiArCj4gPiArCXJldCA9IG9mX3Byb3Bl cnR5X3JlYWRfdTMyKG5vZGUsICJ4bG54LGxpbmUtcmF0ZSIsICZ4c2Rpcnhzcy0+bW9kZSk7Cj4g PiArCWlmIChyZXQgPCAwKSB7Cj4gPiArCQlkZXZfZXJyKGRldiwgInhsbngsbGluZS1yYXRlIHBy b3BlcnR5IG5vdCBmb3VuZFxuIik7Cj4gPiArCQlyZXR1cm4gcmV0Owo+ID4gKwl9Cj4gPiArCj4g PiArCWlmICh4c2Rpcnhzcy0+bW9kZSAhPSBYU0RJX1NURF8zRyAmJiB4c2Rpcnhzcy0+bW9kZSAh PSBYU0RJX1NURF82RyAmJgo+ID4gKwkgICAgeHNkaXJ4c3MtPm1vZGUgIT0gWFNESV9TVERfMTJH XzhEUykgewo+ID4gKwkJZGV2X2VycihkZXYsICJJbnZhbGlkIExpbmUgUmF0ZVxuIik7Cj4gPiAr CQlyZXR1cm4gLUVJTlZBTDsKPiA+ICsJfQo+ID4gKwo+ID4gKwlkZXZfZGJnKGRldiwgIlNESSBS eCBMaW5lIFJhdGUgLyBtb2RlID0gJWRcbiIsIHhzZGlyeHNzLT5tb2RlKTsKPiA+ICsKPiA+ICsJ cmV0ID0gb2ZfcHJvcGVydHlfcmVhZF91MzIobm9kZSwgInhsbngsYnBjIiwgJnhzZGlyeHNzLT5i cGMpOwo+ID4gKwlpZiAocmV0ID09IC1FSU5WQUwpIHsKPiA+ICsJCXhzZGlyeHNzLT5icGMgPSAx MDsKPiA+ICsJCWRldl9kYmcoZGV2LCAic2V0IGRlZmF1bHQgYnBjIGFzIDEwXG4iKTsKPiA+ICsJ fSBlbHNlIGlmIChyZXQgPCAwKSB7Cj4gPiArCQlkZXZfZXJyKGRldiwgImZhaWxlZCB0byBnZXQg eGxueCxicGNcbiIpOwo+ID4gKwkJcmV0dXJuIHJldDsKPiA+ICsJfQo+ID4gKwo+ID4gKwlpZiAo eHNkaXJ4c3MtPmJwYyAhPSAxMCAmJiB4c2Rpcnhzcy0+YnBjICE9IDEyKSB7Cj4gPiArCQlkZXZf ZXJyKGRldiwgImJpdHMgcGVyIGNvbXBvbmVudD0ldS4gQ2FuIGJlIDEwIG9yIDEyIG9ubHlcbiIs Cj4gPiArCQkJeHNkaXJ4c3MtPmJwYyk7Cj4gPiArCQlyZXR1cm4gLUVJTlZBTDsKPiA+ICsJfQo+ ID4gKwo+ID4gKwlyZXR1cm4gcmV0Owo+ID4gK30KPiA+ICsKPiA+ICtzdGF0aWMgaW50IHhzZGly eHNzX3Byb2JlKHN0cnVjdCBwbGF0Zm9ybV9kZXZpY2UgKnBkZXYpCj4gPiArewo+ID4gKwlzdHJ1 Y3QgdjRsMl9zdWJkZXYgKnN1YmRldjsKPiA+ICsJc3RydWN0IHhzZGlyeHNzX3N0YXRlICp4c2Rp cnhzczsKPiA+ICsJc3RydWN0IGRldmljZSAqZGV2Owo+ID4gKwlpbnQgcmV0LCBpcnE7Cj4gPiAr CXVuc2lnbmVkIGludCBudW1fY3RybHMsIGk7Cj4gPiArCj4gPiArCXhzZGlyeHNzID0gZGV2bV9r emFsbG9jKCZwZGV2LT5kZXYsIHNpemVvZigqeHNkaXJ4c3MpLCBHRlBfS0VSTkVMKTsKPiA+ICsJ aWYgKCF4c2RpcnhzcykKPiA+ICsJCXJldHVybiAtRU5PTUVNOwo+ID4gKwo+ID4gKwl4c2Rpcnhz cy0+ZGV2ID0gJnBkZXYtPmRldjsKPiA+ICsJZGV2ID0geHNkaXJ4c3MtPmRldjsKPiA+ICsKPiA+ ICsJc3Bpbl9sb2NrX2luaXQoJnhzZGlyeHNzLT5zbG9jayk7Cj4gPiArCXJldCA9IHhzZGlyeHNz X3BhcnNlX29mKHhzZGlyeHNzKTsKPiA+ICsJaWYgKHJldCA8IDApCj4gPiArCQlyZXR1cm4gcmV0 Owo+ID4gKwo+ID4gKwl4c2Rpcnhzcy0+aW9tZW0gPSBkZXZtX3BsYXRmb3JtX2lvcmVtYXBfcmVz b3VyY2UocGRldiwgMCk7Cj4gPiArCWlmIChJU19FUlIoeHNkaXJ4c3MtPmlvbWVtKSkKPiA+ICsJ CXJldHVybiBQVFJfRVJSKHhzZGlyeHNzLT5pb21lbSk7Cj4gPiArCj4gPiArCXhzZGlyeHNzLT5u dW1fY2xrcyA9IEFSUkFZX1NJWkUoeHNkaXJ4c3NfY2xrcyk7Cj4gPiArCXhzZGlyeHNzLT5jbGtz ID0gZGV2bV9rY2FsbG9jKGRldiwgeHNkaXJ4c3MtPm51bV9jbGtzLAo+ID4gKwkJCQkgICAgICBz aXplb2YoKnhzZGlyeHNzLT5jbGtzKSwgR0ZQX0tFUk5FTCk7Cj4gPiArCWlmICgheHNkaXJ4c3Mt PmNsa3MpCj4gPiArCQlyZXR1cm4gLUVOT01FTTsKPiA+ICsKPiA+ICsJZm9yIChpID0gMDsgaSA8 IHhzZGlyeHNzLT5udW1fY2xrczsgaSsrKQo+ID4gKwkJeHNkaXJ4c3MtPmNsa3NbaV0uaWQgPSB4 c2Rpcnhzc19jbGtzW2ldOwo+ID4gKwo+ID4gKwlyZXQgPSBkZXZtX2Nsa19idWxrX2dldChkZXYs IHhzZGlyeHNzLT5udW1fY2xrcywgeHNkaXJ4c3MtPmNsa3MpOwo+ID4gKwlpZiAocmV0KQo+ID4g KwkJcmV0dXJuIHJldDsKPiA+ICsKPiA+ICsJcmV0ID0gY2xrX2J1bGtfcHJlcGFyZV9lbmFibGUo eHNkaXJ4c3MtPm51bV9jbGtzLCB4c2Rpcnhzcy0+Y2xrcyk7Cj4gPiArCWlmIChyZXQpCj4gPiAr CQlyZXR1cm4gcmV0Owo+ID4gKwo+ID4gKwkvKiBSZXNldCB0aGUgY29yZSAqLwo+ID4gKwl4c2Rp cnhfc3RyZWFtZmxvd19jb250cm9sKHhzZGlyeHNzLCBmYWxzZSk7Cj4gPiArCVhTRElSWF9DT1JF X0RJU0FCTEUoeHNkaXJ4c3MpOwo+ID4gKwkvKiBDbGVhciBhbGwgaW50ZXJydXB0cyAqLwo+ID4g Kwl4c2Rpcnhzc19zZXQoeHNkaXJ4c3MsIFhTRElSWF9JU1JfUkVHLCBYU0RJUlhfSU5UUl9BTExf TUFTSyk7Cj4gPiArCXhzZGlyeHNzX2Nscih4c2RpcnhzcywgWFNESVJYX0lFUl9SRUcsIFhTRElS WF9JTlRSX0FMTF9NQVNLKTsKPiA+ICsJeHNkaXJ4c3Nfc2V0KHhzZGlyeHNzLCBYU0RJUlhfSUVS X1JFRywgWFNESVJYX0lOVFJfQUxMX01BU0spOwo+ID4gKwlYU0RJUlhfR0xPQkFMX0lOVFJfRU5B QkxFKHhzZGlyeHNzKTsKPiA+ICsJeHNkaXJ4c3Nfd3JpdGUoeHNkaXJ4c3MsIFhTRElSWF9DUkNf RVJSQ05UX1JFRywgMHhmZmZmKTsKPiA+ICsKPiA+ICsJLyogUmVnaXN0ZXIgaW50ZXJydXB0IGhh bmRsZXIgKi8KPiA+ICsJaXJxID0gcGxhdGZvcm1fZ2V0X2lycShwZGV2LCAwKTsKPiA+ICsJcmV0 ID0gZGV2bV9yZXF1ZXN0X3RocmVhZGVkX2lycShkZXYsIGlycSwgTlVMTCwgeHNkaXJ4c3NfaXJx X2hhbmRsZXIsCj4gPiArCQkJCQlJUlFGX09ORVNIT1QsIGRldl9uYW1lKGRldiksIHhzZGlyeHNz KTsKPiA+ICsJaWYgKHJldCkgewo+ID4gKwkJZGV2X2VycihkZXYsICJFcnIgPSAlZCBJbnRlcnJ1 cHQgaGFuZGxlciByZWcgZmFpbGVkIVxuIiwKPiA+ICsJCQlyZXQpOwo+ID4gKwkJZ290byBjbGtf ZXJyOwo+ID4gKwl9Cj4gPiArCj4gPiArCS8qIEluaXRpYWxpemUgVjRMMiBzdWJkZXZpY2UgYW5k IG1lZGlhIGVudGl0eSAqLwo+ID4gKwl4c2Rpcnhzcy0+cGFkLmZsYWdzID0gTUVESUFfUEFEX0ZM X1NPVVJDRTsKPiA+ICsKPiA+ICsJLyogSW5pdGlhbGl6ZSB0aGUgZGVmYXVsdCBmb3JtYXQgKi8K PiA+ICsJaWYgKHhzZGlyeHNzLT5icGMgPT0gMTApCj4gPiArCQl4c2Rpcnhzcy0+ZGVmYXVsdF9m b3JtYXQuY29kZSA9IE1FRElBX0JVU19GTVRfVVlWWTEwXzFYMjA7Cj4gPiArCWVsc2UKPiA+ICsJ CXhzZGlyeHNzLT5kZWZhdWx0X2Zvcm1hdC5jb2RlID0gTUVESUFfQlVTX0ZNVF9VWVZZMTJfMVgy NDsKPiA+ICsJeHNkaXJ4c3MtPmRlZmF1bHRfZm9ybWF0LmZpZWxkID0gVjRMMl9GSUVMRF9OT05F Owo+ID4gKwl4c2Rpcnhzcy0+ZGVmYXVsdF9mb3JtYXQuY29sb3JzcGFjZSA9IFY0TDJfQ09MT1JT UEFDRV9SRUM3MDk7Cj4gPiArCXhzZGlyeHNzLT5kZWZhdWx0X2Zvcm1hdC53aWR0aCA9IFhTRElS WF9ERUZBVUxUX1dJRFRIOwo+ID4gKwl4c2Rpcnhzcy0+ZGVmYXVsdF9mb3JtYXQuaGVpZ2h0ID0g WFNESVJYX0RFRkFVTFRfSEVJR0hUOwo+ID4gKwl4c2Rpcnhzcy0+ZGVmYXVsdF9mb3JtYXQueGZl cl9mdW5jID0gVjRMMl9YRkVSX0ZVTkNfNzA5Owo+ID4gKwl4c2Rpcnhzcy0+ZGVmYXVsdF9mb3Jt YXQucXVhbnRpemF0aW9uID0gVjRMMl9RVUFOVElaQVRJT05fTElNX1JBTkdFOwo+ID4gKwo+ID4g Kwl4c2Rpcnhzcy0+Zm9ybWF0ID0geHNkaXJ4c3MtPmRlZmF1bHRfZm9ybWF0Owo+ID4gKwo+ID4g KwkvKiBJbml0aWFsaXplIFY0TDIgc3ViZGV2aWNlIGFuZCBtZWRpYSBlbnRpdHkgKi8KPiA+ICsJ c3ViZGV2ID0gJnhzZGlyeHNzLT5zdWJkZXY7Cj4gPiArCXY0bDJfc3ViZGV2X2luaXQoc3ViZGV2 LCAmeHNkaXJ4c3Nfb3BzKTsKPiA+ICsKPiA+ICsJc3ViZGV2LT5kZXYgPSAmcGRldi0+ZGV2Owo+ ID4gKwlzdHJzY3B5KHN1YmRldi0+bmFtZSwgZGV2X25hbWUoZGV2KSwgc2l6ZW9mKHN1YmRldi0+ bmFtZSkpOwo+ID4gKwo+ID4gKwlzdWJkZXYtPmZsYWdzID0gVjRMMl9TVUJERVZfRkxfSEFTX0VW RU5UUyB8IFY0TDJfU1VCREVWX0ZMX0hBU19ERVZOT0RFOwo+ID4gKwo+ID4gKwlzdWJkZXYtPmVu dGl0eS5vcHMgPSAmeHNkaXJ4c3NfbWVkaWFfb3BzOwo+ID4gKwo+ID4gKwl2NGwyX3NldF9zdWJk ZXZkYXRhKHN1YmRldiwgeHNkaXJ4c3MpOwo+ID4gKwo+ID4gKwlyZXQgPSBtZWRpYV9lbnRpdHlf cGFkc19pbml0KCZzdWJkZXYtPmVudGl0eSwgMSwgJnhzZGlyeHNzLT5wYWQpOwo+ID4gKwlpZiAo cmV0IDwgMCkKPiA+ICsJCWdvdG8gZXJyb3I7Cj4gPiArCj4gPiArCS8qIEluaXRpYWxpc2UgYW5k IHJlZ2lzdGVyIHRoZSBjb250cm9scyAqLwo+ID4gKwludW1fY3RybHMgPSBBUlJBWV9TSVpFKHhz ZGlyeHNzX2N0cmxzKTsKPiA+ICsKPiA+ICsJaWYgKHhzZGlyeHNzLT5pbmNsdWRlX2VkaCkKPiA+ ICsJCW51bV9jdHJscyArPSBBUlJBWV9TSVpFKHhzZGlyeHNzX2VkaF9jdHJscyk7Cj4gPiArCj4g PiArCXY0bDJfY3RybF9oYW5kbGVyX2luaXQoJnhzZGlyeHNzLT5jdHJsX2hhbmRsZXIsIG51bV9j dHJscyk7Cj4gPiArCj4gPiArCWZvciAoaSA9IDA7IGkgPCBBUlJBWV9TSVpFKHhzZGlyeHNzX2N0 cmxzKTsgaSsrKSB7Cj4gPiArCQlzdHJ1Y3QgdjRsMl9jdHJsICpjdHJsOwo+ID4gKwo+ID4gKwkJ ZGV2X2RiZyhkZXYsICIlZCAlcyBjdHJsID0gMHgleFxuIiwgaSwgeHNkaXJ4c3NfY3RybHNbaV0u bmFtZSwKPiA+ICsJCQl4c2Rpcnhzc19jdHJsc1tpXS5pZCk7Cj4gPiArCj4gPiArCQljdHJsID0g djRsMl9jdHJsX25ld19jdXN0b20oJnhzZGlyeHNzLT5jdHJsX2hhbmRsZXIsCj4gPiArCQkJCQkg ICAgJnhzZGlyeHNzX2N0cmxzW2ldLCBOVUxMKTsKCllvdSBjYW4gZHJvcCB0aGUgY3RybCB2YXJp YWJsZSwgaXQncyBub3QgdXNlZC4gU2FtZSBiZWxvdy4KCj4gPiArCX0KPiA+ICsKPiA+ICsJaWYg KHhzZGlyeHNzLT5pbmNsdWRlX2VkaCkgewo+ID4gKwkJZm9yIChpID0gMDsgaSA8IEFSUkFZX1NJ WkUoeHNkaXJ4c3NfZWRoX2N0cmxzKTsgaSsrKSB7Cj4gPiArCQkJc3RydWN0IHY0bDJfY3RybCAq Y3RybDsKPiA+ICsKPiA+ICsJCQlkZXZfZGJnKGRldiwgIiVkICVzIGN0cmwgPSAweCV4XG4iLCBp LAo+ID4gKwkJCQl4c2Rpcnhzc19lZGhfY3RybHNbaV0ubmFtZSwKPiA+ICsJCQkJeHNkaXJ4c3Nf ZWRoX2N0cmxzW2ldLmlkKTsKPiA+ICsKPiA+ICsJCQljdHJsID0gdjRsMl9jdHJsX25ld19jdXN0 b20oJnhzZGlyeHNzLT5jdHJsX2hhbmRsZXIsCj4gPiArCQkJCQkJICAgICZ4c2Rpcnhzc19lZGhf Y3RybHNbaV0sCj4gPiArCQkJCQkJICAgIE5VTEwpOwo+ID4gKwkJfQo+ID4gKwl9Cj4gPiArCj4g PiArCWlmICh4c2Rpcnhzcy0+Y3RybF9oYW5kbGVyLmVycm9yKSB7Cj4gPiArCQlkZXZfZXJyKGRl diwgImZhaWxlZCB0byBhZGQgY29udHJvbHNcbiIpOwo+ID4gKwkJcmV0ID0geHNkaXJ4c3MtPmN0 cmxfaGFuZGxlci5lcnJvcjsKPiA+ICsJCWdvdG8gZXJyb3I7Cj4gPiArCX0KPiA+ICsKPiA+ICsJ c3ViZGV2LT5jdHJsX2hhbmRsZXIgPSAmeHNkaXJ4c3MtPmN0cmxfaGFuZGxlcjsKPiA+ICsKPiA+ ICsJcmV0ID0gdjRsMl9jdHJsX2hhbmRsZXJfc2V0dXAoJnhzZGlyeHNzLT5jdHJsX2hhbmRsZXIp Owo+ID4gKwlpZiAocmV0IDwgMCkgewo+ID4gKwkJZGV2X2VycihkZXYsICJmYWlsZWQgdG8gc2V0 IGNvbnRyb2xzXG4iKTsKPiA+ICsJCWdvdG8gZXJyb3I7Cj4gPiArCX0KPiA+ICsKPiA+ICsJcGxh dGZvcm1fc2V0X2RydmRhdGEocGRldiwgeHNkaXJ4c3MpOwo+ID4gKwo+ID4gKwlyZXQgPSB2NGwy X2FzeW5jX3JlZ2lzdGVyX3N1YmRldihzdWJkZXYpOwo+ID4gKwlpZiAocmV0IDwgMCkgewo+ID4g KwkJZGV2X2VycihkZXYsICJmYWlsZWQgdG8gcmVnaXN0ZXIgc3ViZGV2XG4iKTsKPiA+ICsJCWdv dG8gZXJyb3I7Cj4gPiArCX0KPiA+ICsKPiA+ICsJeHNkaXJ4c3MtPnByZXZfaXNfZnJhYyA9IC0x Owo+ID4gKwo+ID4gKwlYU0RJUlhfQ09SRV9FTkFCTEUoeHNkaXJ4c3MpOwo+ID4gKwo+ID4gKwly ZXR1cm4gMDsKPiA+ICtlcnJvcjoKPiA+ICsJdjRsMl9jdHJsX2hhbmRsZXJfZnJlZSgmeHNkaXJ4 c3MtPmN0cmxfaGFuZGxlcik7Cj4gPiArCW1lZGlhX2VudGl0eV9jbGVhbnVwKCZzdWJkZXYtPmVu dGl0eSk7Cj4gPiArCVhTRElSWF9HTE9CQUxfSU5UUl9ESVNBQkxFKHhzZGlyeHNzKTsKPiA+ICsJ eHNkaXJ4c3NfY2xyKHhzZGlyeHNzLCBYU0RJUlhfSUVSX1JFRywgWFNESVJYX0lOVFJfQUxMX01B U0spOwo+ID4gK2Nsa19lcnI6Cj4gPiArCWNsa19idWxrX2Rpc2FibGVfdW5wcmVwYXJlKHhzZGly eHNzLT5udW1fY2xrcywgeHNkaXJ4c3MtPmNsa3MpOwo+ID4gKwlyZXR1cm4gcmV0Owo+ID4gK30K PiA+ICsKPiA+ICtzdGF0aWMgaW50IHhzZGlyeHNzX3JlbW92ZShzdHJ1Y3QgcGxhdGZvcm1fZGV2 aWNlICpwZGV2KQo+ID4gK3sKPiA+ICsJc3RydWN0IHhzZGlyeHNzX3N0YXRlICp4c2RpcnhzcyA9 IHBsYXRmb3JtX2dldF9kcnZkYXRhKHBkZXYpOwo+ID4gKwlzdHJ1Y3QgdjRsMl9zdWJkZXYgKnN1 YmRldiA9ICZ4c2Rpcnhzcy0+c3ViZGV2Owo+ID4gKwo+ID4gKwlYU0RJUlhfQ09SRV9ESVNBQkxF KHhzZGlyeHNzKTsKPiA+ICsJWFNESVJYX0dMT0JBTF9JTlRSX0RJU0FCTEUoeHNkaXJ4c3MpOwo+ ID4gKwl4c2Rpcnhzc19jbHIoeHNkaXJ4c3MsIFhTRElSWF9JRVJfUkVHLCBYU0RJUlhfSU5UUl9B TExfTUFTSyk7Cj4gPiArCXhzZGlyeF9zdHJlYW1mbG93X2NvbnRyb2woeHNkaXJ4c3MsIGZhbHNl KTsKPiA+ICsKPiA+ICsJdjRsMl9hc3luY191bnJlZ2lzdGVyX3N1YmRldihzdWJkZXYpOwo+ID4g Kwl2NGwyX2N0cmxfaGFuZGxlcl9mcmVlKCZ4c2Rpcnhzcy0+Y3RybF9oYW5kbGVyKTsKPiA+ICsJ bWVkaWFfZW50aXR5X2NsZWFudXAoJnN1YmRldi0+ZW50aXR5KTsKPiA+ICsKPiA+ICsJY2xrX2J1 bGtfZGlzYWJsZV91bnByZXBhcmUoeHNkaXJ4c3MtPm51bV9jbGtzLCB4c2Rpcnhzcy0+Y2xrcyk7 Cj4gPiArCj4gPiArCXJldHVybiAwOwo+ID4gK30KPiA+ICsKPiA+ICtzdGF0aWMgY29uc3Qgc3Ry dWN0IG9mX2RldmljZV9pZCB4c2Rpcnhzc19vZl9pZF90YWJsZVtdID0gewo+ID4gKwl7IC5jb21w YXRpYmxlID0gInhsbngsdi1zbXB0ZS11aGRzZGktcngtc3MtMi4wIiB9LAo+ID4gKwl7IH0KPiA+ ICt9Owo+ID4gK01PRFVMRV9ERVZJQ0VfVEFCTEUob2YsIHhzZGlyeHNzX29mX2lkX3RhYmxlKTsK PiA+ICsKPiA+ICtzdGF0aWMgc3RydWN0IHBsYXRmb3JtX2RyaXZlciB4c2Rpcnhzc19kcml2ZXIg PSB7Cj4gPiArCS5kcml2ZXIgPSB7Cj4gPiArCQkubmFtZQkJPSAieGlsaW54LXNkaXJ4c3MiLAo+ ID4gKwkJLm9mX21hdGNoX3RhYmxlCT0geHNkaXJ4c3Nfb2ZfaWRfdGFibGUsCj4gPiArCX0sCj4g PiArCS5wcm9iZQkJCT0geHNkaXJ4c3NfcHJvYmUsCj4gPiArCS5yZW1vdmUJCQk9IHhzZGlyeHNz X3JlbW92ZSwKPiA+ICt9Owo+ID4gKwo+ID4gK21vZHVsZV9wbGF0Zm9ybV9kcml2ZXIoeHNkaXJ4 c3NfZHJpdmVyKTsKPiA+ICsKPiA+ICtNT0RVTEVfQVVUSE9SKCJWaXNoYWwgU2FnYXIgPHZzYWdh ckB4aWxpbnguY29tPiIpOwo+ID4gK01PRFVMRV9ERVNDUklQVElPTigiWGlsaW54IFNESSBSeCBT dWJzeXN0ZW0gRHJpdmVyIik7Cj4gPiArTU9EVUxFX0xJQ0VOU0UoIkdQTCB2MiIpOwo+ID4gZGlm ZiAtLWdpdCBhL2luY2x1ZGUvdWFwaS9saW51eC92NGwyLWNvbnRyb2xzLmggYi9pbmNsdWRlL3Vh cGkvbGludXgvdjRsMi1jb250cm9scy5oCj4gPiBpbmRleCA2MjI3MTQxOGMxYmUuLjk1MjZhNmFj YzZmNCAxMDA2NDQKPiA+IC0tLSBhL2luY2x1ZGUvdWFwaS9saW51eC92NGwyLWNvbnRyb2xzLmgK PiA+ICsrKyBiL2luY2x1ZGUvdWFwaS9saW51eC92NGwyLWNvbnRyb2xzLmgKPiA+IEBAIC0xOTgs NiArMTk4LDEyIEBAIGVudW0gdjRsMl9jb2xvcmZ4IHsKPiA+ICAgKi8KPiA+ICAjZGVmaW5lIFY0 TDJfQ0lEX1VTRVJfQVRNRUxfSVNDX0JBU0UJCShWNEwyX0NJRF9VU0VSX0JBU0UgKyAweDEwYzAp Cj4gPiAgCj4gPiArLyoKPiA+ICsgKiBUaGUgYmFzZSBmb3IgdGhlIFhpbGlueCBTREkgUnggZHJp dmVyIGNvbnRyb2xzLgo+ID4gKyAqIFdlIHJlc2VydmUgMTYgY29udHJvbHMgZm9yIHRoaXMgZHJp dmVyLgo+ID4gKyAqLwo+ID4gKyNkZWZpbmUgVjRMMl9DSURfVVNFUl9YSUxJTlhfU0RJUlhfQkFT RQkJKFY0TDJfQ0lEX1VTRVJfQkFTRSArIDB4MTBlMCkKPiA+ICsKPiA+ICAvKiBNUEVHLWNsYXNz IGNvbnRyb2wgSURzICovCj4gPiAgLyogVGhlIE1QRUcgY29udHJvbHMgYXJlIGFwcGxpY2FibGUg dG8gYWxsIGNvZGVjIGNvbnRyb2xzCj4gPiAgICogYW5kIHRoZSAnTVBFRycgcGFydCBvZiB0aGUg ZGVmaW5lIGlzIGhpc3RvcmljYWwgKi8KPiA+IGRpZmYgLS1naXQgYS9pbmNsdWRlL3VhcGkvbGlu dXgveGlsaW54LXNkaXJ4c3MuaCBiL2luY2x1ZGUvdWFwaS9saW51eC94aWxpbngtc2Rpcnhzcy5o Cj4gPiBuZXcgZmlsZSBtb2RlIDEwMDY0NAo+ID4gaW5kZXggMDAwMDAwMDAwMDAwLi4xYmNiZjU4 NTJiMjIKPiA+IC0tLSAvZGV2L251bGwKPiA+ICsrKyBiL2luY2x1ZGUvdWFwaS9saW51eC94aWxp bngtc2Rpcnhzcy5oCj4gPiBAQCAtMCwwICsxLDI4MyBAQAo+ID4gKy8qIFNQRFgtTGljZW5zZS1J ZGVudGlmaWVyOiBHUEwtMi4wIFdJVEggTGludXgtc3lzY2FsbC1ub3RlICovCj4gPiArLyoKPiA+ ICsgKiBYaWxpbnggU0RJIFJ4IFN1YnN5c3RlbSBtb2RlLCBldmVudCwgY3VzdG9tIHRpbWluZ3Mg YW5kCj4gPiArICogZmxhZyBkZWZpbml0aW9ucy4KPiA+ICsgKgo+ID4gKyAqIENvcHlyaWdodCAo QykgMjAxOSAtIDIwMjAgWGlsaW54LCBJbmMuCj4gPiArICoKPiA+ICsgKiBDb250YWN0czogVmlz aGFsIFNhZ2FyIDx2aXNoYWwuc2FnYXJAeGlsaW54LmNvbT4KPiA+ICsgKi8KPiA+ICsKPiA+ICsj aWZuZGVmIF9fVUFQSV9YSUxJTlhfU0RJUlhTU19IX18KPiA+ICsjZGVmaW5lIF9fVUFQSV9YSUxJ TlhfU0RJUlhTU19IX18KPiA+ICsKPiA+ICsjaW5jbHVkZSA8bGludXgvdHlwZXMuaD4KPiA+ICsj aW5jbHVkZSA8bGludXgvdjRsMi1jb250cm9scy5oPgo+ID4gKyNpbmNsdWRlIDxsaW51eC92NGwy LWR2LXRpbWluZ3MuaD4KPiA+ICsjaW5jbHVkZSA8bGludXgvdmlkZW9kZXYyLmg+Cj4gPiArCj4g PiArLyoKPiA+ICsgKiBFdmVudHMKPiA+ICsgKgo+ID4gKyAqIFY0TDJfRVZFTlRfWElMSU5YX1NE SVJYX1VORF9PVlJfRkxPVzogVmlkZW8gaW4gdG8gQVhJNCBTdHJlYW0gY29yZQo+ID4gKyAqIHVu ZGVyL292ZXJmbG93ZWQgZHVyaW5nIGEgcmVzb2x1dGlvbiBvciBmcmFtZSByYXRlIGNoYW5nZS4K PiA+ICsgKi8KPiA+ICsjZGVmaW5lIFY0TDJfRVZFTlRfWElMSU5YX1NESVJYX0NMQVNTICAgICAg KFY0TDJfRVZFTlRfUFJJVkFURV9TVEFSVCB8IDB4MjAwKQo+ID4gKyNkZWZpbmUgVjRMMl9FVkVO VF9YSUxJTlhfU0RJUlhfVU5EX09WUl9GTE9XCVwKPiA+ICsJCQkJCShWNEwyX0VWRU5UX1hJTElO WF9TRElSWF9DTEFTUyB8IDB4MSkKPiA+ICsKPiA+ICsjZGVmaW5lIFhJTElOWF9TRElSWF9VTkRF UkZMT1dfRVZFTlQJQklUKDEpCj4gPiArI2RlZmluZSBYSUxJTlhfU0RJUlhfT1ZFUkZMT1dfRVZF TlQJQklUKDIpCj4gPiArLyoKPiA+ICsgKiBUaGlzIGVudW0gaXMgdXNlZCB0byBwcmVwYXJlIHRo ZSBiaXRtYXNrIG9mIG1vZGVzIHRvIGJlIGRldGVjdGVkCj4gPiArICovCj4gPiArZW51bSB7Cj4g PiArCVhTRElSWF9NT0RFX1NEX09GRlNFVCA9IDAsCj4gPiArCVhTRElSWF9NT0RFX0hEX09GRlNF VCwKPiA+ICsJWFNESVJYX01PREVfM0dBX09GRlNFVCwKPiA+ICsJWFNESVJYX01PREVfM0dCX09G RlNFVCwKPiA+ICsJWFNESVJYX01PREVfNkdfT0ZGU0VULAo+ID4gKwlYU0RJUlhfTU9ERV8xMkdJ X09GRlNFVCwKPiA+ICsJWFNESVJYX01PREVfMTJHRl9PRkZTRVQsCj4gPiArCVhTRElSWF9NT0RF X05VTV9TVVBQT1JURUQsCj4gPiArfTsKPiAKPiBUaGVzZSBhcmUgYWxsIHN0YW5kYXJkIFNESSBt b2RlcywgcmlnaHQ/Cj4gCj4gPiArCj4gPiArI2RlZmluZSBYU0RJUlhfREVURUNUX0FMTF9NT0RF UwkJKEJJVChYU0RJUlhfTU9ERV9TRF9PRkZTRVQpIHwgXAo+ID4gKwkJCQkJQklUKFhTRElSWF9N T0RFX0hEX09GRlNFVCkgfCBcCj4gPiArCQkJCQlCSVQoWFNESVJYX01PREVfM0dBX09GRlNFVCkg fCBcCj4gPiArCQkJCQlCSVQoWFNESVJYX01PREVfM0dCX09GRlNFVCkgfCBcCj4gPiArCQkJCQlC SVQoWFNESVJYX01PREVfNkdfT0ZGU0VUKSB8IFwKPiA+ICsJCQkJCUJJVChYU0RJUlhfTU9ERV8x MkdJX09GRlNFVCkgfCBcCj4gPiArCQkJCQlCSVQoWFNESVJYX01PREVfMTJHRl9PRkZTRVQpKQo+ ID4gKwo+ID4gKy8qCj4gPiArICogRURIIC0gRXJyb3IgRGV0ZWN0aW9uIGFuZCBIYW5kbGluZy4K PiA+ICsgKiBJbiB0aGUgU0QtU0RJIG1vZGUsIHRoZSBVSEQtU0RJIGNvcmUgZnVsbHkgc3VwcG9y dHMgUlAgMTY1Lgo+ID4gKyAqIFRoZSBiaXRtYXNrIGlzIG5hbWVkIGFzIFhTRElSWF9FREhfRVJS Q05UX1hYX1lZX0VSUiBleGNlcHQKPiA+ICsgKiBmb3IgcGFja2V0IGNoZWNrc3VtIGVycm9yLgo+ ID4gKyAqCj4gPiArICogWFggLSBFREggRXJyb3IgVHlwZXMKPiA+ICsgKiBBTkMgLSBBbmNpbGxh cnkgRGF0YSBQYWNrZXQgRXJyb3JzCj4gPiArICogRkYgLSBGdWxsIEZpZWxkIEVycm9ycwo+ID4g KyAqIEFQIC0gQWN0aXZlIFBvcnRpb24gRXJyb3JzCj4gPiArICoKPiA+ICsgKiBZWSAtIEVycm9y IEZsYWdzCj4gPiArICogRURIIC0gZXJyb3IgZGV0ZWN0ZWQgaGVyZQo+ID4gKyAqIEVEQSAtIGVy cm9yIERldGVjdGVkIGFscmVhZHkKPiA+ICsgKiBJREggLSBpbnRlcm5hbCBlcnJvciBkZXRlY3Rl ZCBoZXJlCj4gPiArICogSURBIC0gaW50ZXJuYWwgZXJyb3IgZGV0ZWN0ZWQgYWxyZWFkeQo+ID4g KyAqIFVFUyAtIHVua25vd24gZXJyb3Igc3RhdHVzCj4gPiArICoKPiA+ICsgKiBSZWZlciB0byBT ZWMgNC4zIEVycm9yIEZsYWdzIGluIFJQIDE2NS0xOTk0IGZvciBkZXRhaWxzCj4gPiArICovCj4g PiArCj4gPiArI2RlZmluZSBYU0RJUlhfRURIX0VSUkNOVF9BTkNfRURIX0VSUgkJQklUKDApCj4g PiArI2RlZmluZSBYU0RJUlhfRURIX0VSUkNOVF9BTkNfRURBX0VSUgkJQklUKDEpCj4gPiArI2Rl ZmluZSBYU0RJUlhfRURIX0VSUkNOVF9BTkNfSURIX0VSUgkJQklUKDIpCj4gPiArI2RlZmluZSBY U0RJUlhfRURIX0VSUkNOVF9BTkNfSURBX0VSUgkJQklUKDMpCj4gPiArI2RlZmluZSBYU0RJUlhf RURIX0VSUkNOVF9BTkNfVUVTX0VSUgkJQklUKDQpCj4gPiArI2RlZmluZSBYU0RJUlhfRURIX0VS UkNOVF9GRl9FREhfRVJSCQlCSVQoNSkKPiA+ICsjZGVmaW5lIFhTRElSWF9FREhfRVJSQ05UX0ZG X0VEQV9FUlIJCUJJVCg2KQo+ID4gKyNkZWZpbmUgWFNESVJYX0VESF9FUlJDTlRfRkZfSURIX0VS UgkJQklUKDcpCj4gPiArI2RlZmluZSBYU0RJUlhfRURIX0VSUkNOVF9GRl9JREFfRVJSCQlCSVQo OCkKPiA+ICsjZGVmaW5lIFhTRElSWF9FREhfRVJSQ05UX0ZGX1VFU19FUlIJCUJJVCg5KQo+ID4g KyNkZWZpbmUgWFNESVJYX0VESF9FUlJDTlRfQVBfRURIX0VSUgkJQklUKDEwKQo+ID4gKyNkZWZp bmUgWFNESVJYX0VESF9FUlJDTlRfQVBfRURBX0VSUgkJQklUKDExKQo+ID4gKyNkZWZpbmUgWFNE SVJYX0VESF9FUlJDTlRfQVBfSURIX0VSUgkJQklUKDEyKQo+ID4gKyNkZWZpbmUgWFNESVJYX0VE SF9FUlJDTlRfQVBfSURBX0VSUgkJQklUKDEzKQo+ID4gKyNkZWZpbmUgWFNESVJYX0VESF9FUlJD TlRfQVBfVUVTX0VSUgkJQklUKDE0KQo+ID4gKyNkZWZpbmUgWFNESVJYX0VESF9FUlJDTlRfUEtU X0NIS1NVTV9FUlIJQklUKDE1KQo+ID4gKwo+ID4gKyNkZWZpbmUgWFNESVJYX0VESF9BTExFUlJf TUFTSwkJMHhGRkZGCj4gCj4gTG93ZXJjYXNlIDB4ZmZmZi4KPiAKPiBBbmQgdGhlc2UgZXJyb3Ig Y29uZGl0aW9ucyBhcmUgYWxzbyBzdGFuZGFyZGl6ZWQ/Cj4gCj4gSWYgc28sIHRoZW4gSSB0aGlu ayB0aGVzZSBkZWZpbmVzL2VudW1zIGNhbiBiZSBwYXJ0IG9mIFY0TDIgaXRzZWxmIHJhdGhlcgo+ IHRoYW4gWGlsaW54IHNwZWNpZmljLgo+IAo+ID4gKwo+ID4gKy8qCj4gPiArICogVjRMMiBDb250 cm9scyAtIFdlIHJlc2VydmVkIDE2IGNvbnRyb2xzIGZvciB0aGlzIGRyaXZlci4KPiAKPiBJJ2Qg aW5jcmVhc2UgdGhhdCB0byAzMi4KPiAKPiA+ICsgKgo+ID4gKyAqIFRoZSBWNEwyX0NJRF9YSUxJ TlhfU0RJUlhfRURIXyogY29udHJvbHMgYXJlIHByZXNlbnQgb25seSBpZgo+ID4gKyAqIEVESCBp cyBlbmFibGVkLgo+ID4gKyAqIFRoZSBjb250cm9scyB3aGljaCBjYW4gYmUgc2V0IHNob3VsZCBv bmx5IGJlIHNldCBiZWZvcmUgZW5hYmxpbmcKPiA+ICsgKiBzdHJlYW1pbmcuIFRoZSBjb250cm9s cyB3aGljaCBjYW4gYmUgZ290IHNob3VsZCBiZSBjYWxsZWQgd2hpbGUKPiA+ICsgKiBzdHJlYW1p bmcgdG8gZ2V0IGNvcnJlY3QgdmFsdWVzLgo+ID4gKyAqIFRoZSBWNEwyX0NJRF9YSUxJTlhfU0RJ UlhfTU9ERV9ERVRFQ1QgY2FuIGJlIGNhbGxlZCB3aGVuIHF1ZXJ5IGR2IHRpbWluZwo+IAo+IHF1 ZXJ5IGR2IHRpbWluZyAtPiBxdWVyeV9kdl90aW1pbmdzCj4gCj4gPiArICogcmV0dXJucyBhIHZh bGlkIHRpbWluZy4KPiA+ICsgKi8KPiA+ICsKPiA+ICsvKgo+ID4gKyAqIEZyYW1lciBDb250cm9s IHRvIGVuYWJsZSBvciBkaXNhYmxlIHRoZSBmcmFtZXIuIFdoZW4gdGhpcyBpcyBzZXQsIHRoZSBm cmFtZXIKPiA+ICsgKiBhdXRvbWF0aWNhbGx5IHJlYWRqdXN0cyB0aGUgb3V0cHV0IHdvcmQgYWxp Z25tZW50IHRvIG1hdGNoIHRoZSBhbGlnbm1lbnQgb2YKPiA+ICsgKiBlYWNoIHRpbWluZyByZWZl cmVuY2Ugc2lnbmFsKFRSUykuIE5vcm1hbGx5IHRoaXMgc2hvdWxkIGJlIHNldC4gQnV0IHVzZXIg bWF5Cj4gPiArICogY29udHJvbCB0aGlzIGlucHV0IHRvIGltcGxlbWVudCBUUlMgZmlsdGVyaW5n IHRvIHByZXZlbnQgYSBzaWduYWwgbWlzYWxpZ25lZAo+ID4gKyAqIFRSUyBmcm9tIGNhdXNpbmcg ZXJyb25lb3VzIGFsaWdubWVudCBjaGFuZ2VzLgo+ID4gKyAqIFJlZmVyIHRvIFBHMjA1IHJ4X2Zy YW1lX2VuIGZvciBtb3JlIGRldGFpbHMuCj4gPiArICovCj4gPiArI2RlZmluZSBWNEwyX0NJRF9Y SUxJTlhfU0RJUlhfRlJBTUVSCQkoVjRMMl9DSURfVVNFUl9YSUxJTlhfU0RJUlhfQkFTRSArIDEp Cj4gPiArCj4gPiArLyoKPiA+ICsgKiBWaWRlbyBMb2NrIFdpbmRvdyBDb250cm9sIHRvIHNldCB0 aGUgdmlkZW8gbG9jayB3aW5kb3cgdmFsdWUKPiA+ICsgKiBUaGlzIGlzIHRoZSBhbW91bnQgb2Yg dGltZSB0aGUgbW9kZSBhbmQgdHJhbnNwb3J0IHN0cmVhbSBuZWVkCj4gPiArICogdG8gYmUgbG9j a2VkIGJlZm9yZSBhIHZpZGVvIGxvY2sgaW50ZXJydXB0IG9jY3Vycy4KPiA+ICsgKi8KPiA+ICsj ZGVmaW5lIFY0TDJfQ0lEX1hJTElOWF9TRElSWF9WSURMT0NLX1dJTkRPVwkoVjRMMl9DSURfVVNF Ul9YSUxJTlhfU0RJUlhfQkFTRSArIDIpCj4gPiArCj4gPiArLyoKPiA+ICsgKiBFREggRXJyb3Ig TWFzayBDb250cm9sIHRvIGVuYWJsZSBFREggZXJyb3IgY291bnQKPiA+ICsgKiBUaGlzIGNvbnRy b2wgdGFrZXMgaW4gdGhlIGJpdG1hc2sgb2YgWFNESVJYX0VESF9FUlJDTlRfKl9FUlIgdG8gZW5h YmxlIGNvdW50aW5nCj4gPiArICogc3VjaCBlcnJvcnMuCj4gPiArICovCj4gPiArI2RlZmluZSBW NEwyX0NJRF9YSUxJTlhfU0RJUlhfRURIX0VSUk9SX1NPVVJDRVMJKFY0TDJfQ0lEX1VTRVJfWElM SU5YX1NESVJYX0JBU0UgKyAzKQo+IAo+IElmIHRoZXNlIEVESCBlcnJvciBzb3VyY2VzIGFyZSBm cm9tIHRoZSBTREkgc3RhbmRhcmQsIHRoZW4gdGhpcyBjYW4gYmVjb21lIGEgc3RhbmRhcmQKPiBj b250cm9sIGFzIHdlbGwuCj4gCj4gPiArCj4gPiArLyoKPiA+ICsgKiBNb2RlIHNlYXJjaCBDb250 cm9sIHRvIHBhc3MgdGhlIGJpdCBtYXNrIG9mIG1vZGVzIHRvIGRldGVjdC4KPiA+ICsgKiBJZiBv bmx5IDEgYml0IGlzIHNldCwgdGhlIGRyaXZlciBwcm9ncmFtcyBJUCB0byBiZSBpbiBmaXhlZCBt b2RlIGVsc2UKPiA+ICsgKiBpbiBtdWx0aSBkZXRlY3Rpb24gbW9kZS4KPiA+ICsgKgo+ID4gKyAq IFNldCB0aGlzIHdoZW4gbm90IHN0cmVhbWluZy4KPiA+ICsgKgo+ID4gKyAqIGJpdCAwIHNldCB0 byBkZXRlY3QgU0QgIG1vZGUsCj4gPiArICogYml0IDEgc2V0IHRvIGRldGVjdCBIRCAgbW9kZSwK PiA+ICsgKiBiaXQgMiBzZXQgdG8gZGV0ZWN0IDNHQSBtb2RlLAo+ID4gKyAqIGJpdCAzIHNldCB0 byBkZXRlY3QgM0dCIG1vZGUsCj4gPiArICogYml0IDQgc2V0IHRvIGRldGVjdCA2RyAgbW9kZSwK PiA+ICsgKiBiaXQgNSBzZXQgdG8gZGV0ZWN0IDEyRyBpbnRlZ2VyIGZyYW1lIHJhdGUgbW9kZSwK PiA+ICsgKiBiaXQgNiBzZXQgdG8gZGV0ZWN0IDEyRyBmcmFjdGlvbmFsIGZyYW1lIHJhdGUgbW9k ZSwKPiA+ICsgKi8KPiA+ICsjZGVmaW5lIFY0TDJfQ0lEX1hJTElOWF9TRElSWF9TRUFSQ0hfTU9E RVMJKFY0TDJfQ0lEX1VTRVJfWElMSU5YX1NESVJYX0JBU0UgKyA0KQo+IAo+IFNhbWUgaGVyZSBp ZiB0aGVzZSBtb2RlcyBhcmUgc3RhbmRhcmRpemVkLgo+IAo+ID4gKwo+ID4gKy8qCj4gPiArICog R2V0IERldGVjdGVkIFNESSBNb2RlIGNvbnRyb2wgKHJlYWQgb25seSkKPiA+ICsgKgo+ID4gKyAq IENvbnRyb2wgVmFsdWUgLSBNb2RlIGRldGVjdGVkCj4gPiArICogICAgICAgIDAgICAgICAtICAg ICBTRAo+ID4gKyAqICAgICAgICAxICAgICAgLSAgICAgSEQKPiA+ICsgKiAgICAgICAgMiAgICAg IC0gICAgIDNHQQo+ID4gKyAqICAgICAgICAzICAgICAgLSAgICAgM0dCCj4gPiArICogICAgICAg IDQgICAgICAtICAgICA2Rwo+ID4gKyAqICAgICAgICA1ICAgICAgLSAgICAgMTJHIGludGVnZXIg ZnJhbWUgcmF0ZQo+ID4gKyAqICAgICAgICA2ICAgICAgLSAgICAgMTJHIGZyYWN0aW9uYWwgZnJh bWUgcmF0ZQo+ID4gKyAqLwo+ID4gKyNkZWZpbmUgVjRMMl9DSURfWElMSU5YX1NESVJYX01PREVf REVURUNUCShWNEwyX0NJRF9VU0VSX1hJTElOWF9TRElSWF9CQVNFICsgNSkKPiAKPiBEaXR0by4K PiAKPiA+ICsKPiA+ICsvKiBHZXQgbnVtYmVyIG9mIENSQyBlcnJvcnMgc3RhdHVzIGNvbnRyb2wK PiA+ICsgKgo+ID4gKyAqIFdoZW4gYSBDUkMgaXMgZGV0ZWN0ZWQgb24gYSBsaW5lLCB0aGUgQ1JD IGVycm9yIHNpZ25hbCBvZiB0aGF0IGRhdGEgc3RyZWFtCj4gPiArICogYmVjb21lcyBhc3NlcnRl ZCBzdGFydGluZyBhIGZldyBjbG9jayBjeWNsZXMgYWZ0ZXIgdGhlIGxhc3QgQ1JDIHdvcmQgaXMK PiA+ICsgKiBvdXRwdXQgb24gdGhlIGRhdGEgc3RyZWFtIHBvcnRzIGZvbGxvd2luZyB0aGUgRUFW IHRoYXQgZW5kcyB0aGUgbGluZQo+ID4gKyAqIGNvbnRhaW5pbmcgdGhlIGVycm9yLiBUaGUgQ1JD IHNpZ25hbCByZW1haW5zIGFzc2VydGVkIGZvciBvbmUgbGluZSB0aW1lLgo+ID4gKyAqCj4gPiAr ICogVGhlIExTQiAxNiBiaXRzIG9mIHZhbHVlIHJldHVybmVkIGJ5IHRoc2kgY29udHJvbCByZXBy ZXNlbnQgdGhlIGVycm9yCj4gPiArICogc2lnbmFsIG9uIGVhY2ggb2YgMTYgZGF0YSBzdHJlYW1z LiBUaGUgTVNCIDE2IGJpdHMgY29udGFpbnMgdGhlIGFjY3VtdWxhdGVkCj4gPiArICogZXJyb3Ig Y291bnQuCj4gPiArICoKPiA+ICsgKiBSZWZlciB0byBQRzIwNSByeF9jcmNfZXJyX2RzWCAoWCA9 IDEgdG8gMTYpIGRlc2NyaXB0aW9uIGZvciBkZXRhaWxzLgo+ID4gKyAqLwo+ID4gKyNkZWZpbmUg VjRMMl9DSURfWElMSU5YX1NESVJYX0NSQwkJKFY0TDJfQ0lEX1VTRVJfWElMSU5YX1NESVJYX0JB U0UgKyA2KQo+IAo+IEFzIHN1Z2dlc3RlZCBlYXJsaWVyLCBJIHRoaW5rIHRoaXMgc2hvdWxkIGJl IHNwbGl0IGludG8gdHdvIGNvbnRyb2xzLgo+IAo+ID4gKwo+ID4gKy8qCj4gPiArICogR2V0IEVE SCBlcnJvciBjb3VudCBjb250cm9sCj4gPiArICoKPiA+ICsgKiBSZWFkaW5nIHRoaXMgY29udHJv bCB3aWxsIGdpdmUgdGhlIG51bWJlciBvZiBFREggZXJyb3JzIG9jY3VycmVkIGJhc2VkCj4gPiAr ICogb24gdGhlIGJpdG1hc2sgcGFzc2VkIGluIFY0TDJfQ0lEX1hJTElOWF9TRElSWF9FREhfRVJS T1JfU09VUkNFUy4KPiA+ICsgKgo+ID4gKyAqIEl0IGluY3JlbWVudHMgb25jZSBwZXIgZmllbGQg d2hlbiBhbnkgb2YgdGhlIGVycm9yIGNvbmRpdGlvbnMgZW5hYmxlZCBieQo+ID4gKyAqIHRoZSBS WF9FREhfRVJSQ05UX0VOIHJlZ2lzdGVyIGJpdChzKSBvY2N1ciBkdXJpbmcgdGhhdCBmaWVsZC4K PiA+ICsgKgo+ID4gKyAqIFJlZmVyIHRvIFBHMjA1IHJ4X2VkaF9lcnJjbnQKPiA+ICsgKi8KPiA+ ICsjZGVmaW5lIFY0TDJfQ0lEX1hJTElOWF9TRElSWF9FREhfRVJSQ05UCShWNEwyX0NJRF9VU0VS X1hJTElOWF9TRElSWF9CQVNFICsgNykKPiAKPiBFdmVuIHRob3VnaCB0aGUgRURIIGVycm9ycyBh cHBlYXIgdG8gYmUgc3RhbmRhcmQsIEknbSBub3Qgc3VyZSBpZiB0aGlzIHNwZWNpZmljIGNvbnRy b2wKPiBjYW4gYmUgc3RhbmRhcmRpemVkLiBUaGUgcHJlY2lzZSBiZWhhdmlvciBvZiBhIGNvdW50 ZXIgbGlrZSB0aGlzIG1pZ2h0IGRpZmZlciBiZXR3ZWVuCj4gSFcgaW1wbGVtZW50YXRpb25zLgo+ IAo+ID4gKwo+ID4gKy8qCj4gPiArICogR2V0IEVESCBzdGF0dXMgY29udHJvbAo+ID4gKyAqCj4g PiArICogVGhpcyBjb250cm9sIHJldHVybnMgdGhlIFJYX0VESF9TVFMgcmVnaXN0ZXIgY29udGVu dHMuCj4gPiArICogUmVmZXIgdG8gUEcyOTAgcmVnaXN0ZXIgc3BhY2Ugc2VjdGlvbiBmb3IgbW9y ZSBkZXRhaWxzLgo+ID4gKyAqLwo+ID4gKyNkZWZpbmUgVjRMMl9DSURfWElMSU5YX1NESVJYX0VE SF9TVEFUVVMJKFY0TDJfQ0lEX1VTRVJfWElMSU5YX1NESVJYX0JBU0UgKyA4KQo+IAo+IEFzIG1l bnRpb25lZCBhYm92ZTogdGhpcyBpcyBhIGR1YmlvdXMgY29udHJvbCwgcmVwb3J0aW5nIGl0IGlu IGxvZ19zdGF0dXMgc2VlbXMKPiBhIG1vcmUgbG9naWNhbCBhcHByb2FjaC4KPiAKPiA+ICsKPiA+ ICsvKiBHZXQgVHJhbnNwb3J0IEludGVybGFjZWQgc3RhdHVzIHdoZXRoZXIgaXQgaXMgaW50ZXJs YWNlZCBvciBub3QgKi8KPiA+ICsjZGVmaW5lIFY0TDJfQ0lEX1hJTElOWF9TRElSWF9UU19JU19J TlRFUkxBQ0VECShWNEwyX0NJRF9VU0VSX1hJTElOWF9TRElSWF9CQVNFICsgOSkKPiAKPiBBbmQg YXMgYWxzbyBtZW50aW9uZWQgYWJvdmUsIHRoaXMgd2lsbCBiZSByZXBsYWNlZCBieSBhIG5ldyBG SUVMRF9BTFRFUk5BVEVfUFJPRz8KPiAKPiA+ICsKPiA+ICsvKgo+ID4gKyAqIFhpbGlueCBEViB0 aW1pbmdzCj4gPiArICogVE9ETyAtIFJlbW92ZSB0aGVzZSBvbmNlIHRoZXkgYXJlIGluIHY0bDIt ZHYtdGltaW5ncy5oCj4gPiArICovCj4gPiArI2RlZmluZSBYTE5YX1Y0TDJfRFZfQlRfMjA0OFgx MDgwUDI0IHsgXAo+ID4gKwkudHlwZSA9IFY0TDJfRFZfQlRfNjU2XzExMjAsIFwKPiA+ICsJVjRM Ml9JTklUX0JUX1RJTUlOR1MoMjA0OCwgMTA4MCwgMCwgXAo+ID4gKwkJVjRMMl9EVl9IU1lOQ19Q T1NfUE9MIHwgVjRMMl9EVl9WU1lOQ19QT1NfUE9MLCBcCj4gPiArCQk3NDI1MDAwMCwgNTEwLCA0 NCwgMTQ4LCA0LCA1LCAzNiwgMCwgMCwgMCwgXAo+ID4gKwkJVjRMMl9EVl9CVF9TVERfU0RJKSBc Cj4gPiArfQo+ID4gKwo+ID4gKyNkZWZpbmUgWExOWF9WNEwyX0RWX0JUXzIwNDhYMTA4MFAyNSB7 IFwKPiA+ICsJLnR5cGUgPSBWNEwyX0RWX0JUXzY1Nl8xMTIwLCBcCj4gPiArCVY0TDJfSU5JVF9C VF9USU1JTkdTKDIwNDgsIDEwODAsIDAsIFwKPiA+ICsJCVY0TDJfRFZfSFNZTkNfUE9TX1BPTCB8 IFY0TDJfRFZfVlNZTkNfUE9TX1BPTCwgXAo+ID4gKwkJNzQyNTAwMDAsIDQwMCwgNDQsIDE0OCwg NCwgNSwgMzYsIDAsIDAsIDAsIFwKPiA+ICsJCVY0TDJfRFZfQlRfU1REX1NESSkgXAo+ID4gK30K PiA+ICsKPiA+ICsjZGVmaW5lIFhMTlhfVjRMMl9EVl9CVF8yMDQ4WDEwODBQMzAgeyBcCj4gPiAr CS50eXBlID0gVjRMMl9EVl9CVF82NTZfMTEyMCwgXAo+ID4gKwlWNEwyX0lOSVRfQlRfVElNSU5H UygyMDQ4LCAxMDgwLCAwLCBcCj4gPiArCQlWNEwyX0RWX0hTWU5DX1BPU19QT0wgfCBWNEwyX0RW X1ZTWU5DX1BPU19QT0wsIFwKPiA+ICsJCTc0MjUwMDAwLCA2NiwgMjAsIDY2LCA0LCA1LCAzNiwg MCwgMCwgMCwgXAo+ID4gKwkJVjRMMl9EVl9CVF9TVERfU0RJKSBcCj4gPiArfQo+ID4gKwo+ID4g KyNkZWZpbmUgWExOWF9WNEwyX0RWX0JUXzIwNDhYMTA4MEk0OCB7IFwKPiA+ICsJLnR5cGUgPSBW NEwyX0RWX0JUXzY1Nl8xMTIwLCBcCj4gPiArCVY0TDJfSU5JVF9CVF9USU1JTkdTKDIwNDgsIDEw ODAsIDEsIFwKPiA+ICsJCVY0TDJfRFZfSFNZTkNfUE9TX1BPTCB8IFY0TDJfRFZfVlNZTkNfUE9T X1BPTCwgXAo+ID4gKwkJNzQyNTAwMDAsIDMyOSwgNDQsIDMyOSwgMiwgNSwgMTUsIDMsIDUsIDE1 LCBcCj4gPiArCQlWNEwyX0RWX0JUX1NURF9TREkpIFwKPiA+ICt9Cj4gPiArCj4gPiArI2RlZmlu ZSBYTE5YX1Y0TDJfRFZfQlRfMjA0OFgxMDgwSTUwIHsgXAo+ID4gKwkudHlwZSA9IFY0TDJfRFZf QlRfNjU2XzExMjAsIFwKPiA+ICsJVjRMMl9JTklUX0JUX1RJTUlOR1MoMjA0OCwgMTA4MCwgMSwg XAo+ID4gKwkJVjRMMl9EVl9IU1lOQ19QT1NfUE9MIHwgVjRMMl9EVl9WU1lOQ19QT1NfUE9MLCBc Cj4gPiArCQk3NDI1MDAwMCwgMjc0LCA0NCwgMjc0LCAyLCA1LCAxNSwgMywgNSwgMTUsIFwKPiA+ ICsJCVY0TDJfRFZfQlRfU1REX1NESSkgXAo+ID4gK30KPiA+ICsKPiA+ICsjZGVmaW5lIFhMTlhf VjRMMl9EVl9CVF8yMDQ4WDEwODBJNjAgeyBcCj4gPiArCS50eXBlID0gVjRMMl9EVl9CVF82NTZf MTEyMCwgXAo+ID4gKwlWNEwyX0lOSVRfQlRfVElNSU5HUygyMDQ4LCAxMDgwLCAxLCBcCj4gPiAr CQlWNEwyX0RWX0hTWU5DX1BPU19QT0wgfCBWNEwyX0RWX1ZTWU5DX1BPU19QT0wsIFwKPiA+ICsJ CTc0MjUwMDAwLCA2NiwgMjAsIDY2LCAyLCA1LCAxNSwgMywgNSwgMTUsIFwKPiA+ICsJCVY0TDJf RFZfQlRfU1REX1NESSkgXAo+ID4gK30KPiA+ICsKPiA+ICsjZGVmaW5lIFhMTlhfVjRMMl9EVl9C VF8yMDQ4WDEwODBQNDggeyBcCj4gPiArCS50eXBlID0gVjRMMl9EVl9CVF82NTZfMTEyMCwgXAo+ ID4gKwlWNEwyX0lOSVRfQlRfVElNSU5HUygyMDQ4LCAxMDgwLCAwLCBcCj4gPiArCQlWNEwyX0RW X0hTWU5DX1BPU19QT0wgfCBWNEwyX0RWX1ZTWU5DX1BPU19QT0wsIFwKPiA+ICsJCTE0ODUwMDAw MCwgNTEwLCA0NCwgMTQ4LCA0LCA1LCAzNiwgMCwgMCwgMCwgXAo+ID4gKwkJVjRMMl9EVl9CVF9T VERfU0RJKSBcCj4gPiArfQo+ID4gKwo+ID4gKyNkZWZpbmUgWExOWF9WNEwyX0RWX0JUXzIwNDhY MTA4MFA1MCB7IFwKPiA+ICsJLnR5cGUgPSBWNEwyX0RWX0JUXzY1Nl8xMTIwLCBcCj4gPiArCVY0 TDJfSU5JVF9CVF9USU1JTkdTKDIwNDgsIDEwODAsIDAsIFwKPiA+ICsJCVY0TDJfRFZfSFNZTkNf UE9TX1BPTCB8IFY0TDJfRFZfVlNZTkNfUE9TX1BPTCwgXAo+ID4gKwkJMTQ4NTAwMDAwLCA0MDAs IDQ0LCAxNDgsIDQsIDUsIDM2LCAwLCAwLCAwLCBcCj4gPiArCQlWNEwyX0RWX0JUX1NURF9TREkp IFwKPiA+ICt9Cj4gPiArCj4gPiArI2RlZmluZSBYTE5YX1Y0TDJfRFZfQlRfMjA0OFgxMDgwUDYw IHsgXAo+ID4gKwkudHlwZSA9IFY0TDJfRFZfQlRfNjU2XzExMjAsIFwKPiA+ICsJVjRMMl9JTklU X0JUX1RJTUlOR1MoMjA0OCwgMTA4MCwgMCwgXAo+ID4gKwkJVjRMMl9EVl9IU1lOQ19QT1NfUE9M IHwgVjRMMl9EVl9WU1lOQ19QT1NfUE9MLCBcCj4gPiArCQkxNDg1MDAwMDAsIDg4LCA0NCwgMjAs IDQsIDUsIDM2LCAwLCAwLCAwLCBcCj4gPiArCQlWNEwyX0RWX0JUX1NURF9TREkpIFwKPiA+ICt9 Cj4gPiArCj4gPiArI2RlZmluZSBYTE5YX1Y0TDJfRFZfQlRfMTkyMFgxMDgwSTQ4IHsgXAo+ID4g KwkudHlwZSA9IFY0TDJfRFZfQlRfNjU2XzExMjAsIFwKPiA+ICsJVjRMMl9JTklUX0JUX1RJTUlO R1MoMTkyMCwgMTA4MCwgMSwgXAo+ID4gKwkJVjRMMl9EVl9IU1lOQ19QT1NfUE9MIHwgVjRMMl9E Vl9WU1lOQ19QT1NfUE9MLCBcCj4gPiArCQkxNDg1MDAwMDAsIDM3MSwgODgsIDM3MSwgMiwgNSwg MTUsIDMsIDUsIDE1LCBcCj4gPiArCQlWNEwyX0RWX0JUX1NURF9TREkpIFwKPiA+ICt9Cj4gPiAr Cj4gPiArI2VuZGlmIC8qIF9fVUFQSV9YSUxJTlhfU0RJUlhTU19IX18gKi8KCi0tIApSZWdhcmRz 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21:33:27 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ideasonboard.com header.i=@ideasonboard.com header.b="S0hYaAWq" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726765AbgGOVd1 (ORCPT ); Wed, 15 Jul 2020 17:33:27 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60460 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726670AbgGOVd0 (ORCPT ); Wed, 15 Jul 2020 17:33:26 -0400 Received: from perceval.ideasonboard.com (perceval.ideasonboard.com [IPv6:2001:4b98:dc2:55:216:3eff:fef7:d647]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 624F2C061755; Wed, 15 Jul 2020 14:33:25 -0700 (PDT) Received: from pendragon.ideasonboard.com (81-175-216-236.bb.dnainternet.fi [81.175.216.236]) by perceval.ideasonboard.com (Postfix) with ESMTPSA id AC343564; Wed, 15 Jul 2020 23:33:22 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ideasonboard.com; s=mail; t=1594848803; bh=uhwx1ZrzzumUYxJ8EEJ1c7hBgtoqxkgDljA2p0ocD9s=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=S0hYaAWqoh8B3sqAAbKHei9ISfySdfxwDZsIzhkawLad4ZaNgbKlKXDiyJTW3ITYv DMJmcyvat+g5fPFE70dMdgvXgDaKVksB5nqZbFzxaitUaviUtkkfBd6uQTL+ko1Vqw L3a3AYQO0SWIsBMstJVxUOecDXZQ9y1MPfW2m48c= Date: Thu, 16 Jul 2020 00:33:15 +0300 From: Laurent Pinchart To: Vishal Sagar Cc: Hans Verkuil , hyunk@xilinx.com, mchehab@kernel.org, robh+dt@kernel.org, mark.rutland@arm.com, michals@xilinx.com, linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, joe@perches.com, sandipk@xilinx.com, dineshk@xilinx.com Subject: Re: [PATCH v3 3/3] media: v4l: xilinx: Add Xilinx UHD-SDI Rx Subsystem driver Message-ID: <20200715213315.GF6144@pendragon.ideasonboard.com> References: <20200618053304.14551-1-vishal.sagar@xilinx.com> <20200618053304.14551-4-vishal.sagar@xilinx.com> <50cc4f4b-e788-c5ad-cd6a-b428b96d5377@xs4all.nl> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <50cc4f4b-e788-c5ad-cd6a-b428b96d5377@xs4all.nl> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Hi Vishal, Thank you for the patch. Hans, there are a few questions for you below. On Thu, Jun 25, 2020 at 11:43:01AM +0200, Hans Verkuil wrote: > On 18/06/2020 07:33, Vishal Sagar wrote: > > The Xilinx UHD-SDI Rx subsystem soft IP is used to capture native SDI > > streams from SDI sources like SDI broadcast equipment like cameras and > > mixers. This block outputs either native SDI, native video or > > AXI4-Stream compliant data stream for further processing. Please refer > > to PG290 for details. > > > > The driver is used to configure the IP to add framer, search for > > specific modes, get the detected mode, stream parameters, errors, etc. > > It also generates events for video lock/unlock, bridge over/under flow. > > > > The driver supports 10/12 bpc YUV 422 media bus format currently. It > > also decodes the stream parameters based on the ST352 packet embedded in the > > stream. In case the ST352 packet isn't present in the stream, the core's > > detected properties are used to set stream properties. > > > > The driver currently supports only the AXI4-Stream IP configuration. > > > > Signed-off-by: Vishal Sagar > > --- > > v3 > > - fixed KConfig with better description > > - removed unnecessary header files > > - converted uppercase to lowercase for all hex values > > - merged core struct to state struct > > - removed most one line functions and replaced with direct reg > > read/write or macros > > - dt property bpp to bpc. default 10. not mandatory. > > - fixed subscribe events, log_status, s_stream > > - merged overflow/underflow to one event > > - moved all controls to xilinx-sdirxss.h > > - max events from 128 to 8 > > - used FIELD_GET() instead of custom macro > > - updated the controls documentation > > - added spinlock > > - removed 3GB control and added mode to detect bitmask > > - fixed format for (width, height, colorspace, xfer func, etc) > > - added dv_timings_cap, s/g_dv_timings > > - fixed set/get_format > > - fix v4l control registrations > > - fix order of registration / deregistration in probe() remove() > > - fixed other comments from Hyun, Laurent and Hans > > - things yet to close > > - adding source port for connector (Laurent's suggestion) > > - adding new FIELD type for Transport Stream V4L2_FIELD_ALTERNATE_PROG (Han's suggestion) > > - Update / remove EDH or CRC related controls > > > > v2 > > - Added DV timing support based on Hans Verkuilś feedback > > - More documentation to custom v4l controls and events > > - Fixed Hyunś comments > > - Added macro for masking and shifting as per Joe Perches comments > > - Updated to latest as per Xilinx github repo driver like > > adding new DV timings not in mainline yet uptill 03/21/20 > > > > drivers/media/platform/xilinx/Kconfig | 11 + > > drivers/media/platform/xilinx/Makefile | 1 + > > .../media/platform/xilinx/xilinx-sdirxss.c | 2121 +++++++++++++++++ > > include/uapi/linux/v4l2-controls.h | 6 + > > include/uapi/linux/xilinx-sdirxss.h | 283 +++ > > 5 files changed, 2422 insertions(+) > > create mode 100644 drivers/media/platform/xilinx/xilinx-sdirxss.c > > create mode 100644 include/uapi/linux/xilinx-sdirxss.h > > > > diff --git a/drivers/media/platform/xilinx/Kconfig b/drivers/media/platform/xilinx/Kconfig > > index 01c96fb66414..578cdcc1036e 100644 > > --- a/drivers/media/platform/xilinx/Kconfig > > +++ b/drivers/media/platform/xilinx/Kconfig > > @@ -12,6 +12,17 @@ config VIDEO_XILINX > > > > if VIDEO_XILINX > > > > +config VIDEO_XILINX_SDIRXSS > > + tristate "Xilinx UHD SDI Rx Subsystem" > > + help > > + Driver for Xilinx UHD-SDI Rx Subsystem. This is a V4L sub-device > > + based driver that takes input from a SDI source like SDI camera and > > + converts it into an AXI4-Stream. The subsystem comprises a SMPTE > > + UHD-SDI Rx core, a SDI Rx to Native Video bridge and a Video In to > > + AXI4-Stream bridge. The driver is used to set different stream > > + detection modes and identify stream properties to properly configure > > + downstream. > > + > > config VIDEO_XILINX_TPG > > tristate "Xilinx Video Test Pattern Generator" > > depends on VIDEO_XILINX > > diff --git a/drivers/media/platform/xilinx/Makefile b/drivers/media/platform/xilinx/Makefile > > index 4cdc0b1ec7a5..3beaf24d832c 100644 > > --- a/drivers/media/platform/xilinx/Makefile > > +++ b/drivers/media/platform/xilinx/Makefile > > @@ -3,5 +3,6 @@ > > xilinx-video-objs += xilinx-dma.o xilinx-vip.o xilinx-vipp.o > > > > obj-$(CONFIG_VIDEO_XILINX) += xilinx-video.o > > +obj-$(CONFIG_VIDEO_XILINX_SDIRXSS) += xilinx-sdirxss.o > > obj-$(CONFIG_VIDEO_XILINX_TPG) += xilinx-tpg.o > > obj-$(CONFIG_VIDEO_XILINX_VTC) += xilinx-vtc.o > > diff --git a/drivers/media/platform/xilinx/xilinx-sdirxss.c b/drivers/media/platform/xilinx/xilinx-sdirxss.c > > new file mode 100644 > > index 000000000000..e39aab7c656a > > --- /dev/null > > +++ b/drivers/media/platform/xilinx/xilinx-sdirxss.c > > @@ -0,0 +1,2121 @@ > > +// SPDX-License-Identifier: GPL-2.0 > > +/* > > + * Driver for Xilinx SDI Rx Subsystem > > + * > > + * Copyright (C) 2017 - 2020 Xilinx, Inc. > > + * > > + * Contacts: Vishal Sagar > > + */ > > + > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include That's an impressive trim down of headers, but I think it may have gone a bit too far :-S I've pointed out to headers that are not needed in v2, but you've removed all headers that are implicitly included through other headers. This makes the driver more fragile, as if headers are refactored, there's a large risk of compilation breakages. > > +#include > > +#include > > +#include > > +#include > > +#include > > + > > +/* > > + * SDI Rx register map, bitmask and offsets > > + */ > > +#define XSDIRX_RST_CTRL_REG 0x00 > > +#define XSDIRX_MDL_CTRL_REG 0x04 > > +#define XSDIRX_GLBL_IER_REG 0x0c > > +#define XSDIRX_ISR_REG 0x10 > > +#define XSDIRX_IER_REG 0x14 > > +#define XSDIRX_ST352_VALID_REG 0x18 > > +#define XSDIRX_ST352_DS1_REG 0x1c > > +#define XSDIRX_ST352_DS3_REG 0x20 > > +#define XSDIRX_ST352_DS5_REG 0x24 > > +#define XSDIRX_ST352_DS7_REG 0x28 > > +#define XSDIRX_ST352_DS9_REG 0x2c > > +#define XSDIRX_ST352_DS11_REG 0x30 > > +#define XSDIRX_ST352_DS13_REG 0x34 > > +#define XSDIRX_ST352_DS15_REG 0x38 > > +#define XSDIRX_VERSION_REG 0x3c > > +#define XSDIRX_SS_CONFIG_REG 0x40 > > +#define XSDIRX_MODE_DET_STAT_REG 0x44 > > +#define XSDIRX_TS_DET_STAT_REG 0x48 > > +#define XSDIRX_EDH_STAT_REG 0x4c > > +#define XSDIRX_EDH_ERRCNT_EN_REG 0x50 > > +#define XSDIRX_EDH_ERRCNT_REG 0x54 > > +#define XSDIRX_CRC_ERRCNT_REG 0x58 > > +#define XSDIRX_VID_LOCK_WINDOW_REG 0x5c > > +#define XSDIRX_ST352_DS2_REG 0x70 > > +#define XSDIRX_ST352_DS4_REG 0x74 > > +#define XSDIRX_ST352_DS6_REG 0x78 > > +#define XSDIRX_ST352_DS8_REG 0x7c > > +#define XSDIRX_ST352_DS10_REG 0x80 > > +#define XSDIRX_ST352_DS12_REG 0x84 > > +#define XSDIRX_ST352_DS14_REG 0x88 > > +#define XSDIRX_ST352_DS16_REG 0x8c > > + > > +#define XSDIRX_RST_CTRL_SS_EN_MASK BIT(0) > > +#define XSDIRX_RST_CTRL_SRST_MASK BIT(1) > > +#define XSDIRX_RST_CTRL_RST_CRC_ERRCNT_MASK BIT(2) > > +#define XSDIRX_RST_CTRL_RST_EDH_ERRCNT_MASK BIT(3) > > +#define XSDIRX_RST_CTRL_SDIRX_BRIDGE_ENB_MASK BIT(8) > > +#define XSDIRX_RST_CTRL_VIDIN_AXI4S_MOD_ENB_MASK BIT(9) > > +#define XSDIRX_RST_CTRL_BRIDGE_CH_FMT_OFFSET 10 > > +#define XSDIRX_RST_CTRL_BRIDGE_CH_FMT_MASK GENMASK(12, 10) > > +#define XSDIRX_RST_CTRL_BRIDGE_CH_FMT_YUV444 1 > > + > > +#define XSDIRX_MDL_CTRL_FRM_EN_MASK BIT(4) > > +#define XSDIRX_MDL_CTRL_MODE_DET_EN_MASK BIT(5) > > +#define XSDIRX_MDL_CTRL_MODE_HD_EN_MASK BIT(8) > > +#define XSDIRX_MDL_CTRL_MODE_SD_EN_MASK BIT(9) > > +#define XSDIRX_MDL_CTRL_MODE_3G_EN_MASK BIT(10) > > +#define XSDIRX_MDL_CTRL_MODE_6G_EN_MASK BIT(11) > > +#define XSDIRX_MDL_CTRL_MODE_12GI_EN_MASK BIT(12) > > +#define XSDIRX_MDL_CTRL_MODE_12GF_EN_MASK BIT(13) > > +#define XSDIRX_MDL_CTRL_MODE_AUTO_DET_MASK GENMASK(13, 8) > > + > > +#define XSDIRX_MDL_CTRL_FORCED_MODE_OFFSET 16 > > +#define XSDIRX_MDL_CTRL_FORCED_MODE_MASK GENMASK(18, 16) > > + > > +#define XSDIRX_GLBL_INTR_EN_MASK BIT(0) > > + > > +#define XSDIRX_INTR_VIDLOCK_MASK BIT(0) > > +#define XSDIRX_INTR_VIDUNLOCK_MASK BIT(1) > > +#define XSDIRX_INTR_OVERFLOW_MASK BIT(9) > > +#define XSDIRX_INTR_UNDERFLOW_MASK BIT(10) > > + > > +#define XSDIRX_INTR_ALL_MASK (XSDIRX_INTR_VIDLOCK_MASK |\ > > + XSDIRX_INTR_VIDUNLOCK_MASK |\ > > + XSDIRX_INTR_OVERFLOW_MASK |\ > > + XSDIRX_INTR_UNDERFLOW_MASK) > > + > > +#define XSDIRX_ST352_VALID_DS1_MASK BIT(0) > > +#define XSDIRX_ST352_VALID_DS3_MASK BIT(1) > > +#define XSDIRX_ST352_VALID_DS5_MASK BIT(2) > > +#define XSDIRX_ST352_VALID_DS7_MASK BIT(3) > > +#define XSDIRX_ST352_VALID_DS9_MASK BIT(4) > > +#define XSDIRX_ST352_VALID_DS11_MASK BIT(5) > > +#define XSDIRX_ST352_VALID_DS13_MASK BIT(6) > > +#define XSDIRX_ST352_VALID_DS15_MASK BIT(7) > > + > > +#define XSDIRX_MODE_DET_STAT_RX_MODE_MASK GENMASK(2, 0) > > +#define XSDIRX_MODE_DET_STAT_MODE_LOCK_MASK BIT(3) > > +#define XSDIRX_MODE_DET_STAT_ACT_STREAM_MASK GENMASK(6, 4) > > +#define XSDIRX_MODE_DET_STAT_ACT_STREAM_OFFSET 4 > > +#define XSDIRX_MODE_DET_STAT_LVLB_3G_MASK BIT(7) > > + > > +#define XSDIRX_TS_DET_STAT_LOCKED_MASK BIT(0) > > +#define XSDIRX_TS_DET_STAT_SCAN_MASK BIT(1) > > +#define XSDIRX_TS_DET_STAT_FAMILY_MASK GENMASK(7, 4) > > +#define XSDIRX_TS_DET_STAT_RATE_MASK GENMASK(11, 8) > > + > > +#define XSDIRX_TS_DET_STAT_RATE_NONE 0x0 > > +#define XSDIRX_TS_DET_STAT_RATE_23_98HZ 0x2 > > +#define XSDIRX_TS_DET_STAT_RATE_24HZ 0x3 > > +#define XSDIRX_TS_DET_STAT_RATE_47_95HZ 0x4 > > +#define XSDIRX_TS_DET_STAT_RATE_25HZ 0x5 > > +#define XSDIRX_TS_DET_STAT_RATE_29_97HZ 0x6 > > +#define XSDIRX_TS_DET_STAT_RATE_30HZ 0x7 > > +#define XSDIRX_TS_DET_STAT_RATE_48HZ 0x8 > > +#define XSDIRX_TS_DET_STAT_RATE_50HZ 0x9 > > +#define XSDIRX_TS_DET_STAT_RATE_59_94HZ 0xa > > +#define XSDIRX_TS_DET_STAT_RATE_60HZ 0xb > > + > > +#define XSDIRX_EDH_STAT_EDH_AP_MASK BIT(0) > > +#define XSDIRX_EDH_STAT_EDH_FF_MASK BIT(1) > > +#define XSDIRX_EDH_STAT_EDH_ANC_MASK BIT(2) > > +#define XSDIRX_EDH_STAT_AP_FLAG_MASK GENMASK(8, 4) > > +#define XSDIRX_EDH_STAT_FF_FLAG_MASK GENMASK(13, 9) > > +#define XSDIRX_EDH_STAT_ANC_FLAG_MASK GENMASK(18, 14) > > +#define XSDIRX_EDH_STAT_PKT_FLAG_MASK GENMASK(22, 19) > > + > > +#define XSDIRX_EDH_ERRCNT_COUNT_MASK GENMASK(15, 0) > > + > > +#define XSDIRX_CRC_ERRCNT_COUNT_MASK GENMASK(31, 16) > > +#define XSDIRX_CRC_ERRCNT_DS_CRC_MASK GENMASK(15, 0) > > + > > +#define XSDIRX_VERSION_REV_MASK GENMASK(7, 0) > > +#define XSDIRX_VERSION_PATCHID_MASK GENMASK(11, 8) > > +#define XSDIRX_VERSION_VER_REV_MASK GENMASK(15, 12) > > +#define XSDIRX_VERSION_VER_MIN_MASK GENMASK(23, 16) > > +#define XSDIRX_VERSION_VER_MAJ_MASK GENMASK(31, 24) > > + > > +#define XSDIRX_SS_CONFIG_EDH_INCLUDED_MASK BIT(1) > > + > > +#define XSDIRX_STAT_SB_RX_TDATA_CHANGE_DONE_MASK BIT(0) > > +#define XSDIRX_STAT_SB_RX_TDATA_CHANGE_FAIL_MASK BIT(1) > > +#define XSDIRX_STAT_SB_RX_TDATA_GT_RESETDONE_MASK BIT(2) > > +#define XSDIRX_STAT_SB_RX_TDATA_GT_BITRATE_MASK BIT(3) > > + > > +#define XSDIRX_DEFAULT_WIDTH 1920 > > +#define XSDIRX_DEFAULT_HEIGHT 1080 > > + > > +#define XSDIRX_MAX_STR_LENGTH 16 > > + > > +#define XSDIRX_DEFAULT_VIDEO_LOCK_WINDOW 0x3000 > > + > > +#define XSDIRX_MODE_HD_MASK 0x0 > > +#define XSDIRX_MODE_SD_MASK 0x1 > > +#define XSDIRX_MODE_3G_MASK 0x2 > > +#define XSDIRX_MODE_6G_MASK 0x4 > > +#define XSDIRX_MODE_12GI_MASK 0x5 > > +#define XSDIRX_MODE_12GF_MASK 0x6 > > + > > +/* Maximum number of events per file handle. */ > > +#define XSDIRX_MAX_EVENTS 8 > > + > > +/* ST352 related macros */ > > +#define XST352_PAYLOAD_BYTE1_MASK GENMASK(7, 0) > > +#define XST352_PAYLOAD_BYTE2_OFFSET 8 > > +#define XST352_PAYLOAD_BYTE3_OFFSET 16 > > +#define XST352_PAYLOAD_BYTE4_OFFSET 24 > > + > > +#define XST352_BYTE1_ST292_1x720L_1_5G 0x84 > > +#define XST352_BYTE1_ST292_1x1080L_1_5G 0x85 > > +#define XST352_BYTE1_ST425_2008_750L_3GB 0x88 > > +#define XST352_BYTE1_ST425_2008_1125L_3GA 0x89 > > +#define XST352_BYTE1_ST372_DL_3GB 0x8a > > +#define XST352_BYTE1_ST372_2x720L_3GB 0x8b > > +#define XST352_BYTE1_ST372_2x1080L_3GB 0x8c > > +#define XST352_BYTE1_ST2081_10_2160L_6G 0xc0 > > +#define XST352_BYTE1_ST2081_10_2_1080L_6G 0xc1 > > +#define XST352_BYTE1_ST2081_10_DL_2160L_6G 0xc2 > > +#define XST352_BYTE1_ST2082_10_2160L_12G 0xce > > + > > +#define XST352_BYTE2_TS_TYPE_MASK BIT(15) > > +#define XST352_BYTE2_PIC_TYPE_MASK BIT(14) > > +#define XST352_BYTE2_TS_PIC_TYPE_INTERLACED 0 > > +#define XST352_BYTE2_TS_PIC_TYPE_PROGRESSIVE 1 > > + > > +#define XST352_BYTE2_FPS_MASK GENMASK(11, 8) > > +#define XST352_BYTE2_FPS_24F 0x2 > > +#define XST352_BYTE2_FPS_24 0x3 > > +#define XST352_BYTE2_FPS_48F 0x4 > > +#define XST352_BYTE2_FPS_25 0x5 > > +#define XST352_BYTE2_FPS_30F 0x6 > > +#define XST352_BYTE2_FPS_30 0x7 > > +#define XST352_BYTE2_FPS_48 0x8 > > +#define XST352_BYTE2_FPS_50 0x9 > > +#define XST352_BYTE2_FPS_60F 0xa > > +#define XST352_BYTE2_FPS_60 0xb > > +/* Table 4 ST 2081-10:2015 */ > > +#define XST352_BYTE2_FPS_96 0xc > > +#define XST352_BYTE2_FPS_100 0xd > > +#define XST352_BYTE2_FPS_120 0xe > > +#define XST352_BYTE2_FPS_120F 0xf > > + > > +#define XST352_BYTE3_ACT_LUMA_COUNT_MASK BIT(22) > > + > > +#define XST352_BYTE3_COLOR_FORMAT_MASK GENMASK(19, 16) > > +#define XST352_BYTE3_COLOR_FORMAT_422 0x0 > > +#define XST352_BYTE3_COLOR_FORMAT_YUV444 0x1 > > +#define XST352_BYTE3_COLOR_FORMAT_420 0x3 > > +#define XST352_BYTE3_COLOR_FORMAT_GBR 0x2 > > + > > +#define XST352_BYTE3_COLORIMETRY_MASK GENMASK(21, 20) > > +#define XST352_BYTE3_COLORIMETRY_BT709 0 > > +#define XST352_BYTE3_COLORIMETRY_COLOR_VANC 1 > > +#define XST352_BYTE3_COLORIMETRY_UHDTV 2 > > +#define XST352_BYTE3_COLORIMETRY_UNKNOWN 3 > > + > > +#define XST352_BYTE4_BIT_DEPTH_MASK GENMASK(25, 24) > > +#define XST352_BYTE4_BIT_DEPTH_10 0x1 > > +#define XST352_BYTE4_BIT_DEPTH_12 0x2 > > + > > +/* GT input clock for sdi_rx_clk */ > > +#define CLK_INT 148500000UL > > + > > +#define XSDIRXSS_WIDTH_MIN 720 > > +#define XSDIRXSS_WIDTH_MAX 4096 > > +#define XSDIRXSS_HEIGHT_MIN 243 > > +#define XSDIRXSS_HEIGHT_MAX 2160 > > +#define XSDIRXSS_PIXELCLOCK_MIN 13500000 > > +#define XSDIRXSS_PIXELCLOCK_MAX 594000000 > > + > > +/** > > + * enum sdi_family_enc - SDI Transport Video Format Detected with Active Pixels > > + * @XSDIRX_SMPTE_ST_274: SMPTE ST 274 detected with AP 1920x1080 > > + * @XSDIRX_SMPTE_ST_296: SMPTE ST 296 detected with AP 1280x720 > > + * @XSDIRX_SMPTE_ST_2048_2: SMPTE ST 2048-2 detected with AP 2048x1080 > > + * @XSDIRX_SMPTE_ST_295: SMPTE ST 295 detected with AP 1920x1080 > > + * @XSDIRX_NTSC: NTSC encoding detected with AP 720x486 > > + * @XSDIRX_PAL: PAL encoding detected with AP 720x576 > > + * @XSDIRX_TS_UNKNOWN: Unknown SMPTE Transport family type > > + */ > > +enum sdi_family_enc { > > + XSDIRX_SMPTE_ST_274 = 0, > > + XSDIRX_SMPTE_ST_296 = 1, > > + XSDIRX_SMPTE_ST_2048_2 = 2, > > + XSDIRX_SMPTE_ST_295 = 3, > > + XSDIRX_NTSC = 8, > > + XSDIRX_PAL = 9, > > + XSDIRX_TS_UNKNOWN = 15 > > +}; > > + > > +/** > > + * struct xsdirxss_state - SDI Rx Subsystem device structure > > + * @subdev: The v4l2 subdev structure > > + * @ctrl_handler: control handler > > + * @default_format: default V4L2 media bus format > > + * @pad: source media pad > > + * @dev: Platform structure > > + * @iomem: Base address of subsystem > > + * @clks: array of clocks > > + * @prev_is_frac: Previous clock is fractional or not flag > > + * @bpc: Bits per component, can be 10 or 12 > > + * @mode: 3G/6G/12G mode > > + * @num_clks: number of clocks > > + * @include_edh: EDH processor presence > > + * @slock: spinlock to protect below members > > + * @format: Active V4L2 format detected > > + * @src_format: Active V4L2 format on source pad > > + * @frame_interval: Captures the frame rate > > + * @current_timings: DV timings from application > > + * @detected_timings_index: index of DV timings detected on incoming stream > > + * @vidlockwin: Video lock window value set by control > > + * @edhmask: EDH mask set by control > > + * @searchmask: Search mask set by control > > + * @streaming: Flag for storing streaming state > > + * @vidlocked: Flag indicating SDI Rx has locked onto video stream > > + * @ts_is_interlaced: Flag indicating Transport Stream is interlaced. > > + * @framer_enable: Flag for framer enabled or not set by control > > + * > > + * This structure contains the device driver related parameters > > + */ > > +struct xsdirxss_state { > > + struct v4l2_subdev subdev; > > + struct v4l2_ctrl_handler ctrl_handler; > > + struct v4l2_mbus_framefmt default_format; > > + struct media_pad pad; > > + struct device *dev; > > + void __iomem *iomem; > > + struct clk_bulk_data *clks; > > + int prev_is_frac; If I understand the code correctly, this field doesn't store the previous value but the current value programmed to the hardware. It could be named clk_is_frac or something similar. > > + u32 bpc; > > + u32 mode; > > + unsigned int num_clks; > > + bool include_edh; > > + > > + /* > > + * This spinlock is used to protect the below members > > + * format, src_format, frame_interval, current_timings, > > + * detected_timings_index, vidlockwin, edhmask, searchmask, > > + * streaming, vidlocked, ts_is_interlaced, framer_enable > > + */ > > + spinlock_t slock; > > + struct v4l2_mbus_framefmt format; > > + struct v4l2_mbus_framefmt src_format; > > + struct v4l2_fract frame_interval; > > + struct v4l2_dv_timings current_timings; > > + u32 detected_timings_index; > > + u32 vidlockwin; > > + u32 edhmask; > > + u16 searchmask; > > + bool streaming; > > + bool vidlocked; > > + bool ts_is_interlaced; > > + bool framer_enable; > > +}; > > + > > +/* List of clocks required by UHD-SDI Rx subsystem */ > > +static const char * const xsdirxss_clks[] = { > > + "s_axi_aclk", "sdi_rx_clk", "video_out_clk", > > +}; > > + > > +/* TODO - Add YUV 444/420 and RBG 10/12 bpc mbus formats here */ > > +static const u32 xsdirxss_10bpc_mbus_fmts[] = { > > + MEDIA_BUS_FMT_UYVY10_1X20, > > +}; > > + > > +static const u32 xsdirxss_12bpc_mbus_fmts[] = { > > + MEDIA_BUS_FMT_UYVY12_1X24, > > +}; > > + > > +static const struct v4l2_dv_timings fmt_cap[] = { > > + V4L2_DV_BT_SDI_720X487I60, > > + V4L2_DV_BT_CEA_720X576I50, > > + V4L2_DV_BT_CEA_1280X720P24, > > + V4L2_DV_BT_CEA_1280X720P25, > > + V4L2_DV_BT_CEA_1280X720P30, > > + V4L2_DV_BT_CEA_1280X720P50, > > + V4L2_DV_BT_CEA_1280X720P60, > > + V4L2_DV_BT_CEA_1920X1080P24, > > + V4L2_DV_BT_CEA_1920X1080P30, > > + V4L2_DV_BT_CEA_1920X1080I50, > > + V4L2_DV_BT_CEA_1920X1080I60, > > + V4L2_DV_BT_CEA_1920X1080P48, > > + V4L2_DV_BT_CEA_1920X1080P50, > > + V4L2_DV_BT_CEA_1920X1080P60, > > + V4L2_DV_BT_CEA_3840X2160P24, > > + V4L2_DV_BT_CEA_3840X2160P30, > > + V4L2_DV_BT_CEA_3840X2160P48, > > + V4L2_DV_BT_CEA_3840X2160P50, > > + V4L2_DV_BT_CEA_3840X2160P60, > > + V4L2_DV_BT_CEA_4096X2160P24, > > + V4L2_DV_BT_CEA_4096X2160P25, > > + V4L2_DV_BT_CEA_4096X2160P30, > > + V4L2_DV_BT_CEA_4096X2160P48, > > + V4L2_DV_BT_CEA_4096X2160P50, > > + V4L2_DV_BT_CEA_4096X2160P60, > > + > > + XLNX_V4L2_DV_BT_2048X1080P24, > > + XLNX_V4L2_DV_BT_2048X1080P25, > > + XLNX_V4L2_DV_BT_2048X1080P30, > > + XLNX_V4L2_DV_BT_2048X1080I48, > > + XLNX_V4L2_DV_BT_2048X1080I50, > > + XLNX_V4L2_DV_BT_2048X1080I60, > > + XLNX_V4L2_DV_BT_2048X1080P48, > > + XLNX_V4L2_DV_BT_2048X1080P50, > > + XLNX_V4L2_DV_BT_2048X1080P60, > > + XLNX_V4L2_DV_BT_1920X1080I48, > > Looking at this: > > https://www.smpte.org/sites/default/files/images/SMPTE%20wallchart%232.6_20_17-JULY%202017.pdf > > I would think that these formats are defined in one of the smpte standards, > probably ST 2048-2. > > Can you take a look if you have this standard? > > > +}; > > + > > +struct xsdirxss_dv_map { > > + u32 width; > > + u32 height; > > + u32 fps; > > + struct v4l2_dv_timings timing; > > +}; > > + > > +static const struct xsdirxss_dv_map xsdirxss_dv_timings[] = { > > + /* SD - 720x487i60 */ > > + { 720, 243, 30, V4L2_DV_BT_SDI_720X487I60 }, > > + /* SD - 720x576i50 */ > > + { 720, 288, 25, V4L2_DV_BT_CEA_720X576I50 }, > > + /* HD - 1280x720p23.98 */ > > + /* HD - 1280x720p24 */ > > + { 1280, 720, 24, V4L2_DV_BT_CEA_1280X720P24 }, > > + /* HD - 1280x720p25 */ > > + { 1280, 720, 25, V4L2_DV_BT_CEA_1280X720P25 }, > > + /* HD - 1280x720p29.97 */ > > + /* HD - 1280x720p30 */ > > + { 1280, 720, 30, V4L2_DV_BT_CEA_1280X720P30 }, > > + /* HD - 1280x720p50 */ > > + { 1280, 720, 50, V4L2_DV_BT_CEA_1280X720P50 }, > > + /* HD - 1280x720p59.94 */ > > + /* HD - 1280x720p60 */ > > + { 1280, 720, 60, V4L2_DV_BT_CEA_1280X720P60 }, > > + /* HD - 1920x1080p23.98 */ > > + /* HD - 1920x1080p24 */ > > + { 1920, 1080, 24, V4L2_DV_BT_CEA_1920X1080P24 }, > > + /* HD - 1920x1080p25 */ > > + { 1920, 1080, 25, V4L2_DV_BT_CEA_1920X1080P25 }, > > + /* HD - 1920x1080p29.97 */ > > + /* HD - 1920x1080p30 */ > > + { 1920, 1080, 30, V4L2_DV_BT_CEA_1920X1080P30 }, > > + > > + /* HD - 2048x1080p23.98 */ > > + /* HD - 2048x1080p24 */ > > + { 2048, 1080, 24, XLNX_V4L2_DV_BT_2048X1080P24 }, > > + /* HD - 2048x1080p25 */ > > + { 2048, 1080, 24, XLNX_V4L2_DV_BT_2048X1080P25 }, > > + /* HD - 2048x1080p29.97 */ > > + /* HD - 2048x1080p30 */ > > + { 2048, 1080, 24, XLNX_V4L2_DV_BT_2048X1080P30 }, > > + /* HD - 1920x1080i47.95 */ > > + /* HD - 1920x1080i48 */ > > + { 1920, 540, 24, XLNX_V4L2_DV_BT_1920X1080I48 }, > > + > > + /* HD - 1920x1080i50 */ > > + { 1920, 540, 25, V4L2_DV_BT_CEA_1920X1080I50 }, > > + /* HD - 1920x1080i59.94 */ > > + /* HD - 1920x1080i60 */ > > + { 1920, 540, 30, V4L2_DV_BT_CEA_1920X1080I60 }, > > + > > + /* HD - 2048x1080i47.95 */ > > + /* HD - 2048x1080i48 */ > > + { 2048, 540, 24, XLNX_V4L2_DV_BT_2048X1080I48 }, > > + /* HD - 2048x1080i50 */ > > + { 2048, 540, 25, XLNX_V4L2_DV_BT_2048X1080I50 }, > > + /* HD - 2048x1080i59.94 */ > > + /* HD - 2048x1080i60 */ > > + { 2048, 540, 30, XLNX_V4L2_DV_BT_2048X1080I60 }, > > + /* 3G - 1920x1080p47.95 */ > > + /* 3G - 1920x1080p48 */ > > + { 1920, 1080, 48, V4L2_DV_BT_CEA_1920X1080P48 }, > > + > > + /* 3G - 1920x1080p50 148.5 */ > > + { 1920, 1080, 50, V4L2_DV_BT_CEA_1920X1080P50 }, > > + /* 3G - 1920x1080p59.94 148.5/1.001 */ > > + /* 3G - 1920x1080p60 148.5 */ > > + { 1920, 1080, 60, V4L2_DV_BT_CEA_1920X1080P60 }, > > + > > + /* 3G - 2048x1080p47.95 */ > > + /* 3G - 2048x1080p48 */ > > + { 2048, 1080, 48, XLNX_V4L2_DV_BT_2048X1080P48 }, > > + /* 3G - 2048x1080p50 */ > > + { 2048, 1080, 50, XLNX_V4L2_DV_BT_2048X1080P50 }, > > + /* 3G - 2048x1080p59.94 */ > > + /* 3G - 2048x1080p60 */ > > + { 2048, 1080, 60, XLNX_V4L2_DV_BT_2048X1080P60 }, > > + > > + /* 6G - 3840X2160p23.98 */ > > + /* 6G - 3840X2160p24 */ > > + { 3840, 2160, 24, V4L2_DV_BT_CEA_3840X2160P24 }, > > + /* 6G - 3840X2160p25 */ > > + { 3840, 2160, 25, V4L2_DV_BT_CEA_3840X2160P25 }, > > + /* 6G - 3840X2160p29.97 */ > > + /* 6G - 3840X2160p30 */ > > + { 3840, 2160, 30, V4L2_DV_BT_CEA_3840X2160P30 }, > > + /* 6G - 4096X2160p23.98 */ > > + /* 6G - 4096X2160p24 */ > > + { 4096, 2160, 24, V4L2_DV_BT_CEA_4096X2160P24 }, > > + /* 6G - 4096X2160p25 */ > > + { 4096, 2160, 25, V4L2_DV_BT_CEA_4096X2160P25 }, > > + /* 6G - 4096X2160p29.97 */ > > + /* 6G - 4096X2160p30 */ > > + { 4096, 2160, 30, V4L2_DV_BT_CEA_4096X2160P30 }, > > + /* 12G - 3840X2160p47.95 */ > > + /* 12G - 3840X2160p48 */ > > + { 3840, 2160, 48, V4L2_DV_BT_CEA_3840X2160P48 }, > > + > > + /* 12G - 3840X2160p50 */ > > + { 3840, 2160, 50, V4L2_DV_BT_CEA_3840X2160P50 }, > > + /* 12G - 3840X2160p59.94 */ > > + /* 12G - 3840X2160p60 */ > > + { 3840, 2160, 60, V4L2_DV_BT_CEA_3840X2160P60 }, > > + > > + /* 12G - 4096X2160p47.95 */ > > + /* 12G - 4096X2160p48 */ > > + { 3840, 2160, 48, V4L2_DV_BT_CEA_4096X2160P48 }, > > + > > + /* 12G - 4096X2160p50 */ > > + { 4096, 2160, 50, V4L2_DV_BT_CEA_4096X2160P50 }, > > + /* 12G - 4096X2160p59.94 */ > > + /* 12G - 4096X2160p60 */ > > + { 4096, 2160, 60, V4L2_DV_BT_CEA_4096X2160P60 }, > > +}; > > + > > +static const struct v4l2_dv_timings_cap xsdirxss_timings_cap = { > > + .type = V4L2_DV_BT_656_1120, > > + .pad = 0, > > + .reserved = { 0 }, > > + V4L2_INIT_BT_TIMINGS(XSDIRXSS_WIDTH_MIN, XSDIRXSS_WIDTH_MAX, > > + XSDIRXSS_HEIGHT_MIN, XSDIRXSS_HEIGHT_MAX, > > + XSDIRXSS_PIXELCLOCK_MIN, XSDIRXSS_PIXELCLOCK_MAX, > > + V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_SDI, > > + V4L2_DV_BT_CAP_PROGRESSIVE > > + | V4L2_DV_BT_CAP_INTERLACED) > > + > > +}; As this is only used in xsdirxss_dv_timings_cap(), I would just set the fields there. Up to you. > > + > > +struct regmap { > > + const char *name; > > + u32 offset; > > +}; > > + > > +static const struct regmap xsdirxss_regmap[] = { > > + { .name = "Reset Control", .offset = XSDIRX_RST_CTRL_REG }, > > + { .name = "Module Control", .offset = XSDIRX_MDL_CTRL_REG }, > > + { .name = "Interrupt Enable", .offset = XSDIRX_IER_REG }, > > + { .name = "Global Interrupt Enable", .offset = XSDIRX_GLBL_IER_REG }, > > + { .name = "ST352 Valid", .offset = XSDIRX_ST352_VALID_REG }, > > + { .name = "ST352 DS1", .offset = XSDIRX_ST352_DS1_REG }, > > + { .name = "ST352 DS2", .offset = XSDIRX_ST352_DS2_REG }, > > + { .name = "ST352 DS3", .offset = XSDIRX_ST352_DS3_REG }, > > + { .name = "ST352 DS4", .offset = XSDIRX_ST352_DS4_REG }, > > + { .name = "ST352 DS5", .offset = XSDIRX_ST352_DS5_REG }, > > + { .name = "ST352 DS6", .offset = XSDIRX_ST352_DS6_REG }, > > + { .name = "ST352 DS7", .offset = XSDIRX_ST352_DS7_REG }, > > + { .name = "ST352 DS8", .offset = XSDIRX_ST352_DS8_REG }, > > + { .name = "ST352 DS9", .offset = XSDIRX_ST352_DS9_REG }, > > + { .name = "ST352 DS10", .offset = XSDIRX_ST352_DS10_REG }, > > + { .name = "ST352 DS11", .offset = XSDIRX_ST352_DS11_REG }, > > + { .name = "ST352 DS12", .offset = XSDIRX_ST352_DS12_REG }, > > + { .name = "ST352 DS13", .offset = XSDIRX_ST352_DS13_REG }, > > + { .name = "ST352 DS14", .offset = XSDIRX_ST352_DS14_REG }, > > + { .name = "ST352 DS15", .offset = XSDIRX_ST352_DS15_REG }, > > + { .name = "ST352 DS16", .offset = XSDIRX_ST352_DS16_REG }, > > + { .name = "Version", .offset = XSDIRX_VERSION_REG }, > > + { .name = "Subsystem Config ", .offset = XSDIRX_SS_CONFIG_REG }, > > + { .name = "Mode Detect", .offset = XSDIRX_MODE_DET_STAT_REG }, > > + { .name = "Transport Stream Detect", .offset = XSDIRX_TS_DET_STAT_REG }, > > + { .name = "EDH Status", .offset = XSDIRX_EDH_STAT_REG }, > > + { .name = "EDH Error Count", .offset = XSDIRX_EDH_ERRCNT_EN_REG }, > > + { .name = "CRC error indication", .offset = XSDIRX_CRC_ERRCNT_REG }, > > + { .name = "Video Lock Window", .offset = XSDIRX_VID_LOCK_WINDOW_REG }, > > +}; > > + > > +static inline struct xsdirxss_state * > > +to_xsdirxssstate(struct v4l2_subdev *subdev) > > +{ > > + return container_of(subdev, struct xsdirxss_state, subdev); > > +} > > + > > +/* > > + * Register related operations > > + */ > > +static inline u32 xsdirxss_read(struct xsdirxss_state *xsdirxss, u32 addr) > > +{ > > + return ioread32(xsdirxss->iomem + addr); > > +} > > + > > +static inline void xsdirxss_write(struct xsdirxss_state *xsdirxss, u32 addr, > > + u32 value) > > +{ > > + iowrite32(value, xsdirxss->iomem + addr); > > +} > > + > > +static inline void xsdirxss_clr(struct xsdirxss_state *xsdirxss, u32 addr, > > + u32 clr) > > +{ > > + xsdirxss_write(xsdirxss, addr, xsdirxss_read(xsdirxss, addr) & ~clr); > > +} > > + > > +static inline void xsdirxss_set(struct xsdirxss_state *xsdirxss, u32 addr, > > + u32 set) > > +{ > > + xsdirxss_write(xsdirxss, addr, xsdirxss_read(xsdirxss, addr) | set); > > +} > > + > > +#define XSDIRX_CORE_DISABLE(state) xsdirxss_clr((state), XSDIRX_RST_CTRL_REG,\ > > + XSDIRX_RST_CTRL_SS_EN_MASK) > > + > > +#define XSDIRX_CORE_ENABLE(state) xsdirxss_set((state), XSDIRX_RST_CTRL_REG,\ > > + XSDIRX_RST_CTRL_SS_EN_MASK) > > + > > +#define XSDIRX_GLOBAL_INTR_ENABLE(state) \ > > + xsdirxss_set((state), XSDIRX_GLBL_IER_REG, XSDIRX_GLBL_INTR_EN_MASK) > > + > > +#define XSDIRX_GLOBAL_INTR_DISABLE(state) \ > > + xsdirxss_clr((state), XSDIRX_GLBL_IER_REG, XSDIRX_GLBL_INTR_EN_MASK) Any reason to make these macros and not inline functions ? > > + > > +static int xsdirx_set_modedetect(struct xsdirxss_state *state, u16 mask) > > +{ > > + u32 val; > > + struct device *dev = state->dev; > > + > > + mask &= XSDIRX_DETECT_ALL_MODES; > > + if (!mask) { > > + dev_err(dev, "Invalid bit mask = 0x%08x\n", mask); > > + return -EINVAL; > > + } > > + > > + dev_dbg(dev, "mask = 0x%x\n", mask); > > + > > + val = xsdirxss_read(state, XSDIRX_MDL_CTRL_REG); > > + val &= ~XSDIRX_MDL_CTRL_MODE_DET_EN_MASK; > > + val &= ~XSDIRX_MDL_CTRL_MODE_AUTO_DET_MASK; > > + val &= ~XSDIRX_MDL_CTRL_FORCED_MODE_MASK; > > + > > + if (hweight16(mask) > 1) { > > + /* Multi mode detection as more than 1 bit set in mask */ > > + dev_dbg(dev, "Detect multiple modes\n"); > > + > > + if (mask & BIT(XSDIRX_MODE_SD_OFFSET)) > > + val |= XSDIRX_MDL_CTRL_MODE_SD_EN_MASK; > > + if (mask & BIT(XSDIRX_MODE_HD_OFFSET)) > > + val |= XSDIRX_MDL_CTRL_MODE_HD_EN_MASK; > > + /* > > + * There is only one bit in IP to detect 3G mode. > > + * So set it when 3GA or 3GB mask is set. > > + */ > > + if (mask & (BIT(XSDIRX_MODE_3GA_OFFSET) | > > + BIT(XSDIRX_MODE_3GB_OFFSET))) > > + val |= XSDIRX_MDL_CTRL_MODE_3G_EN_MASK; > > + if (mask & BIT(XSDIRX_MODE_6G_OFFSET)) > > + val |= XSDIRX_MDL_CTRL_MODE_6G_EN_MASK; > > + if (mask & BIT(XSDIRX_MODE_12GI_OFFSET)) > > + val |= XSDIRX_MDL_CTRL_MODE_12GI_EN_MASK; > > + if (mask & BIT(XSDIRX_MODE_12GF_OFFSET)) > > + val |= XSDIRX_MDL_CTRL_MODE_12GF_EN_MASK; > > + > > + val |= XSDIRX_MDL_CTRL_MODE_DET_EN_MASK; > > + } else { > > + /* Fixed Mode */ > > + u32 forced_mode_mask; > > + > > + dev_dbg(dev, "Detect fixed mode\n"); > > + > > + /* Find offset of first bit set */ > > + switch (mask) { > > + case XSDIRX_MODE_SD_OFFSET: > > + forced_mode_mask = XSDIRX_MODE_SD_MASK; > > + break; > > + case XSDIRX_MODE_HD_OFFSET: > > + forced_mode_mask = XSDIRX_MODE_HD_MASK; > > + break; > > + /* > > + * There is only one bit in IP to detect 3G mode. > > + * So set it when 3GA or 3GB mask is set. > > + */ > > + case XSDIRX_MODE_3GA_OFFSET: > > + case XSDIRX_MODE_3GB_OFFSET: > > + forced_mode_mask = XSDIRX_MODE_3G_MASK; > > + break; > > + case XSDIRX_MODE_6G_OFFSET: > > + forced_mode_mask = XSDIRX_MODE_6G_MASK; > > + break; > > + case XSDIRX_MODE_12GI_OFFSET: > > + forced_mode_mask = XSDIRX_MODE_12GI_MASK; > > + break; > > + case XSDIRX_MODE_12GF_OFFSET: > > + forced_mode_mask = XSDIRX_MODE_12GF_MASK; > > + break; > > + default: > > + dev_err(dev, "Invalid mask for fixed detect mode\n"); > > + return -EINVAL; > > + } > > + dev_dbg(dev, "Forced Mode Mask : 0x%x\n", > > + forced_mode_mask); > > + val |= forced_mode_mask << XSDIRX_MDL_CTRL_FORCED_MODE_OFFSET; > > + } > > + > > + dev_dbg(dev, "Modes to be detected : sdi ctrl reg = 0x%08x\n", > > + val); > > + xsdirxss_write(state, XSDIRX_MDL_CTRL_REG, val); > > + > > + return 0; > > +} > > + > > +static void xsdirx_streamflow_control(struct xsdirxss_state *state, bool enable) > > +{ > > + /* The sdi to native bridge is followed by native to axis4 bridge */ > > + /* > > + * TODO - Enable YUV444/RBG format in the bridge based > > + * on BYTE3 color format. > > + * XSDIRX_RST_CTRL_BRIDGE_CH_FMT_YUV444 > > + */ > > + if (enable) { > > + xsdirxss_set(state, XSDIRX_RST_CTRL_REG, > > + XSDIRX_RST_CTRL_VIDIN_AXI4S_MOD_ENB_MASK); > > + xsdirxss_set(state, XSDIRX_RST_CTRL_REG, > > + XSDIRX_RST_CTRL_SDIRX_BRIDGE_ENB_MASK); > > + } else { > > + xsdirxss_clr(state, XSDIRX_RST_CTRL_REG, > > + XSDIRX_RST_CTRL_SDIRX_BRIDGE_ENB_MASK); > > + xsdirxss_clr(state, XSDIRX_RST_CTRL_REG, > > + XSDIRX_RST_CTRL_VIDIN_AXI4S_MOD_ENB_MASK); > > + } > > + state->streaming = enable; > > +} > > + > > +static void xsdirxss_get_framerate(struct v4l2_fract *frame_interval, > > + u32 framerate) > > +{ > > + switch (framerate) { > > + case XSDIRX_TS_DET_STAT_RATE_23_98HZ: > > + frame_interval->numerator = 1001; > > + frame_interval->denominator = 24000; > > + break; > > + case XSDIRX_TS_DET_STAT_RATE_24HZ: > > + frame_interval->numerator = 1000; > > + frame_interval->denominator = 24000; > > + break; > > + case XSDIRX_TS_DET_STAT_RATE_25HZ: > > + frame_interval->numerator = 1000; > > + frame_interval->denominator = 25000; > > + break; > > + case XSDIRX_TS_DET_STAT_RATE_29_97HZ: > > + frame_interval->numerator = 1001; > > + frame_interval->denominator = 30000; > > + break; > > + case XSDIRX_TS_DET_STAT_RATE_30HZ: > > + frame_interval->numerator = 1000; > > + frame_interval->denominator = 30000; > > + break; > > + case XSDIRX_TS_DET_STAT_RATE_47_95HZ: > > + frame_interval->numerator = 1001; > > + frame_interval->denominator = 48000; > > + break; > > + case XSDIRX_TS_DET_STAT_RATE_48HZ: > > + frame_interval->numerator = 1000; > > + frame_interval->denominator = 48000; > > + break; > > + case XSDIRX_TS_DET_STAT_RATE_50HZ: > > + frame_interval->numerator = 1000; > > + frame_interval->denominator = 50000; > > + break; > > + case XSDIRX_TS_DET_STAT_RATE_59_94HZ: > > + frame_interval->numerator = 1001; > > + frame_interval->denominator = 60000; > > + break; > > + case XSDIRX_TS_DET_STAT_RATE_60HZ: > > + frame_interval->numerator = 1000; > > + frame_interval->denominator = 60000; > > + break; > > + default: > > + frame_interval->numerator = 1; > > + frame_interval->denominator = 1; > > + } > > +} > > + > > +static void xsdirxss_set_gtclk(struct xsdirxss_state *state) > > +{ > > + struct clk *gtclk; > > + unsigned long clkrate; > > + int ret, is_frac; > > + u32 mode; > > + > > + mode = xsdirxss_read(state, XSDIRX_MODE_DET_STAT_REG); > > + mode &= XSDIRX_MODE_DET_STAT_RX_MODE_MASK; > > + > > + /* > > + * TODO: For now, don't change the clock rate for any mode except 12G. > > + * In future, configure gt clock for all modes and enable clock only > > + * when needed (stream on/off). > > + */ > > + if (mode != XSDIRX_MODE_12GI_MASK && mode != XSDIRX_MODE_12GF_MASK) > > + return; > > + > > + /* When numerator is 1001 then frame rate is fractional else integer */ > > + is_frac = state->frame_interval.numerator == 1001 ? 1 : 0; > > + > > + if (state->prev_is_frac == is_frac) > > + return; > > + > > + XSDIRX_GLOBAL_INTR_DISABLE(state); > > + xsdirxss_clr(state, XSDIRX_IER_REG, XSDIRX_INTR_ALL_MASK); > > + XSDIRX_CORE_DISABLE(state); > > + > > + /* get sdi_rx_clk */ > > + gtclk = state->clks[1].clk; > > + > > + /* calculate clkrate */ > > + if (!is_frac) > > + clkrate = CLK_INT; > > + else > > + clkrate = (CLK_INT * 1000) / 1001; > > + > > + ret = clk_set_rate(gtclk, clkrate); This function is called from the IRQ handler, and with a spinlock held. clk_set_rate() can sleep as the clock source can be an external I2C-controlled chip. Have you tested this code path ? I think taking the spinlock at top level locations will need to be reconsidered. > > + if (ret) > > + dev_err(state->dev, "failed to set clk rate = %d\n", ret); > > + > > + state->prev_is_frac = is_frac; > > + clkrate = clk_get_rate(gtclk); > > + > > + dev_dbg(state->dev, "clkrate = %lu is_frac = %d\n", > > + clkrate, is_frac); > > + > > + if (state->framer_enable) { > > + xsdirxss_set(state, XSDIRX_MDL_CTRL_REG, > > + XSDIRX_MDL_CTRL_FRM_EN_MASK); > > + } else { > > + xsdirxss_clr(state, XSDIRX_MDL_CTRL_REG, > > + XSDIRX_MDL_CTRL_FRM_EN_MASK); > > + } No need for braces. > > + xsdirxss_write(state, XSDIRX_EDH_ERRCNT_EN_REG, > > + state->edhmask & XSDIRX_EDH_ALLERR_MASK); > > + xsdirxss_write(state, XSDIRX_VID_LOCK_WINDOW_REG, state->vidlocked); > > + xsdirx_set_modedetect(state, state->searchmask); > > + XSDIRX_CORE_ENABLE(state); > > + xsdirxss_set(state, XSDIRX_IER_REG, XSDIRX_INTR_ALL_MASK); > > + XSDIRX_GLOBAL_INTR_ENABLE(state); > > +} > > + > > +/** > > + * xsdirx_get_stream_properties - Get SDI Rx stream properties > > + * @state: pointer to driver state > > + * > > + * This function decodes the stream's ST352 payload (if available) to get > > + * stream properties like width, height, picture type (interlaced/progressive), > > + * etc. > > + * > > + * Return: 0 for success else errors > > + */ > > +static int xsdirx_get_stream_properties(struct xsdirxss_state *state) > > +{ > > + struct device *dev = state->dev; > > + u32 mode, payload = 0, val, family, valid, tscan; > > + u8 byte1 = 0, active_luma = 0, pic_type = 0, framerate = 0; > > + u8 sampling = XST352_BYTE3_COLOR_FORMAT_422; > > + struct v4l2_mbus_framefmt *format = &state->format; > > + u32 bpc = XST352_BYTE4_BIT_DEPTH_10; > > + u32 colorimetry = XST352_BYTE3_COLORIMETRY_BT709; > > + > > + mode = xsdirxss_read(state, XSDIRX_MODE_DET_STAT_REG); > > + mode &= XSDIRX_MODE_DET_STAT_RX_MODE_MASK; > > + > > + valid = xsdirxss_read(state, XSDIRX_ST352_VALID_REG); > > + > > + if (mode >= XSDIRX_MODE_3G_MASK && !valid) { > > + dev_err(dev, "No valid ST352 payload present even for 3G mode and above\n"); > > + return -EINVAL; > > + } > > + > > + val = xsdirxss_read(state, XSDIRX_TS_DET_STAT_REG); > > + if (valid & XSDIRX_ST352_VALID_DS1_MASK) { > > + payload = xsdirxss_read(state, XSDIRX_ST352_DS1_REG); > > + byte1 = FIELD_GET(XST352_PAYLOAD_BYTE1_MASK, payload); > > + active_luma = FIELD_GET(XST352_BYTE3_ACT_LUMA_COUNT_MASK, > > + payload); > > + pic_type = FIELD_GET(XST352_BYTE2_PIC_TYPE_MASK, payload); > > + framerate = FIELD_GET(XST352_BYTE2_FPS_MASK, payload); > > + tscan = FIELD_GET(XST352_BYTE2_TS_TYPE_MASK, payload); > > + sampling = FIELD_GET(XST352_BYTE3_COLOR_FORMAT_MASK, payload); > > + bpc = FIELD_GET(XST352_BYTE4_BIT_DEPTH_MASK, payload); > > + colorimetry = FIELD_GET(XST352_BYTE3_COLORIMETRY_MASK, payload); > > + } else { > > + dev_dbg(dev, "No ST352 payload available : Mode = %d\n", mode); > > + framerate = FIELD_GET(XSDIRX_TS_DET_STAT_RATE_MASK, val); > > + tscan = FIELD_GET(XSDIRX_TS_DET_STAT_SCAN_MASK, val); > > + } > > + > > + if ((bpc == XST352_BYTE4_BIT_DEPTH_10 && state->bpc != 10) || > > + (bpc == XST352_BYTE4_BIT_DEPTH_12 && state->bpc != 12)) { > > + dev_dbg(dev, "Bit depth not supported. bpc = %d state->bpc = %d\n", > > + bpc, state->bpc); > > + return -EINVAL; > > + } > > + > > + family = FIELD_GET(XSDIRX_TS_DET_STAT_FAMILY_MASK, val); > > + state->ts_is_interlaced = tscan ? false : true; > > + > > + dev_dbg(dev, "ts_is_interlaced = %d, family = %d\n", > > + state->ts_is_interlaced, family); > > + > > + switch (mode) { > > + case XSDIRX_MODE_HD_MASK: > > + if (!valid) { > > + /* No payload obtained */ > > + dev_dbg(dev, "frame rate : %d, tscan = %d\n", > > + framerate, tscan); > > + /* > > + * NOTE : A progressive segmented frame pSF will be > > + * reported incorrectly as Interlaced as we rely on IP's > > + * transport scan locked bit. > > + */ > > + dev_warn(dev, "pSF will be incorrectly reported as Interlaced\n"); > > + > > + switch (framerate) { > > + case XSDIRX_TS_DET_STAT_RATE_23_98HZ: > > + case XSDIRX_TS_DET_STAT_RATE_24HZ: > > + case XSDIRX_TS_DET_STAT_RATE_25HZ: > > + case XSDIRX_TS_DET_STAT_RATE_29_97HZ: > > + case XSDIRX_TS_DET_STAT_RATE_30HZ: > > + if (family == XSDIRX_SMPTE_ST_296) { > > + format->width = 1280; > > + format->height = 720; > > + format->field = V4L2_FIELD_NONE; > > + } else if (family == XSDIRX_SMPTE_ST_2048_2) { > > + format->width = 2048; > > + format->height = 1080; > > + if (tscan) > > + format->field = V4L2_FIELD_NONE; > > + else > > + format->field = > > + V4L2_FIELD_ALTERNATE; > > + } else { > > + format->width = 1920; > > + format->height = 1080; > > + if (tscan) > > + format->field = V4L2_FIELD_NONE; > > + else > > + format->field = > > + V4L2_FIELD_ALTERNATE; > > + } > > + break; > > + case XSDIRX_TS_DET_STAT_RATE_50HZ: > > + case XSDIRX_TS_DET_STAT_RATE_59_94HZ: > > + case XSDIRX_TS_DET_STAT_RATE_60HZ: > > + if (family == XSDIRX_SMPTE_ST_274) { > > + format->width = 1920; > > + format->height = 1080; > > + } else { > > + format->width = 1280; > > + format->height = 720; > > + } > > + format->field = V4L2_FIELD_NONE; > > + break; > > + default: > > + format->width = 1920; > > + format->height = 1080; > > + format->field = V4L2_FIELD_NONE; > > + } > > + } else { > > + dev_dbg(dev, "Got the payload\n"); > > + switch (byte1) { > > + case XST352_BYTE1_ST292_1x720L_1_5G: > > + /* SMPTE ST 292-1 for 720 line payloads */ > > + format->width = 1280; > > + format->height = 720; > > + break; > > + case XST352_BYTE1_ST292_1x1080L_1_5G: > > + /* SMPTE ST 292-1 for 1080 line payloads */ > > + format->height = 1080; > > + if (active_luma) > > + format->width = 2048; > > + else > > + format->width = 1920; > > + break; > > + default: > > + dev_dbg(dev, "Unknown HD Mode SMPTE standard\n"); > > + return -EINVAL; > > + } > > + } > > + break; > > + case XSDIRX_MODE_SD_MASK: > > + format->field = V4L2_FIELD_ALTERNATE; > > + > > + switch (family) { > > + case XSDIRX_NTSC: > > + format->width = 720; > > + format->height = 486; > > + break; > > + case XSDIRX_PAL: > > + format->width = 720; > > + format->height = 576; > > + break; > > + default: > > + dev_dbg(dev, "Unknown SD Mode SMPTE standard\n"); > > + return -EINVAL; > > + } > > + break; > > + case XSDIRX_MODE_3G_MASK: > > + switch (byte1) { > > + case XST352_BYTE1_ST425_2008_750L_3GB: > > + /* Sec 4.1.6.1 SMPTE 425-2008 */ > > + case XST352_BYTE1_ST372_2x720L_3GB: > > + /* Table 13 SMPTE 425-2008 */ > > + format->width = 1280; > > + format->height = 720; > > + break; > > + case XST352_BYTE1_ST425_2008_1125L_3GA: > > + /* ST352 Table SMPTE 425-1 */ > > + case XST352_BYTE1_ST372_DL_3GB: > > + /* Table 13 SMPTE 425-2008 */ > > + case XST352_BYTE1_ST372_2x1080L_3GB: > > + /* Table 13 SMPTE 425-2008 */ > > + format->height = 1080; > > + if (active_luma) > > + format->width = 2048; > > + else > > + format->width = 1920; > > + break; > > + default: > > + dev_dbg(dev, "Unknown 3G Mode SMPTE standard\n"); > > + return -EINVAL; > > + } > > + break; > > + case XSDIRX_MODE_6G_MASK: > > + switch (byte1) { > > + case XST352_BYTE1_ST2081_10_DL_2160L_6G: > > + /* Dual link 6G */ > > + case XST352_BYTE1_ST2081_10_2160L_6G: > > + /* Table 3 SMPTE ST 2081-10 */ > > + format->height = 2160; > > + if (active_luma) > > + format->width = 4096; > > + else > > + format->width = 3840; > > + break; > > + case XST352_BYTE1_ST2081_10_2_1080L_6G: > > + format->height = 1080; > > + if (active_luma) > > + format->width = 2048; > > + else > > + format->width = 1920; > > + break; > > + default: > > + dev_dbg(dev, "Unknown 6G Mode SMPTE standard\n"); > > + return -EINVAL; > > + } > > + break; > > + case XSDIRX_MODE_12GI_MASK: > > + case XSDIRX_MODE_12GF_MASK: > > + switch (byte1) { > > + case XST352_BYTE1_ST2082_10_2160L_12G: > > + /* Section 4.3.1 SMPTE ST 2082-10 */ > > + format->height = 2160; > > + if (active_luma) > > + format->width = 4096; > > + else > > + format->width = 3840; > > + break; > > + default: > > + dev_dbg(dev, "Unknown 12G Mode SMPTE standard\n"); > > + return -EINVAL; > > + } > > + break; > > + default: > > + dev_err(dev, "Invalid Mode\n"); > > + return -EINVAL; > > + } > > + > > + if (valid) { > > + if (pic_type) > > + format->field = V4L2_FIELD_NONE; > > + else > > + format->field = V4L2_FIELD_ALTERNATE; > > + > > + if (format->height == 1080 && pic_type && !tscan) > > + format->field = V4L2_FIELD_ALTERNATE; > > + > > + /* > > + * In 3GB DL pSF mode the video is similar to interlaced. > > + * So though it is a progressive video, its transport is > > + * interlaced and is sent as two width x (height/2) buffers. > > + */ > > + if (byte1 == XST352_BYTE1_ST372_DL_3GB) { > > + if (state->ts_is_interlaced) > > + format->field = V4L2_FIELD_ALTERNATE; > > + else > > + format->field = V4L2_FIELD_NONE; > > + } > > + } > > + > > + if (format->field == V4L2_FIELD_ALTERNATE) > > + format->height = format->height / 2; > > + > > + switch (sampling) { > > + case XST352_BYTE3_COLOR_FORMAT_422: > > + if (state->bpc == 10) > > + format->code = MEDIA_BUS_FMT_UYVY10_1X20; > > + else > > + format->code = MEDIA_BUS_FMT_UYVY12_1X24; > > + break; > > + case XST352_BYTE3_COLOR_FORMAT_420: > > + case XST352_BYTE3_COLOR_FORMAT_YUV444: > > + case XST352_BYTE3_COLOR_FORMAT_GBR: > > + format->code = 0; > > + dev_dbg(dev, "No corresponding media bus formats\n"); > > + break; > > + default: > > + dev_err(dev, "Unsupported color format : %d\n", sampling); > > + return -EINVAL; > > + } > > + > > + /* Refer Table 3 SMPTE ST 2081-10:2018 */ > > + switch (colorimetry) { > > + case XST352_BYTE3_COLORIMETRY_BT709: > > + format->colorspace = V4L2_COLORSPACE_REC709; > > + break; > > + /* When HDR support is added UHDTV will have BT2020 colorspace */ > > + case XST352_BYTE3_COLORIMETRY_UHDTV: > > + case XST352_BYTE3_COLORIMETRY_COLOR_VANC: > > + case XST352_BYTE3_COLORIMETRY_UNKNOWN: > > + default: > > + dev_err(dev, "Unknown colorimetry : %d\n", colorimetry); > > I'm a bit surprised. I would expect that SDTV over SDI would use > V4L2_COLORSPACE_SMPTE170M, but I don't see that here. > > > + return -EINVAL; > > + } > > + > > + xsdirxss_get_framerate(&state->frame_interval, framerate); > > + > > + dev_dbg(dev, "Stream width = %d height = %d Field = %d payload = 0x%08x ts = 0x%08x\n", > > + format->width, format->height, format->field, payload, val); > > + dev_dbg(dev, "frame rate numerator = %d denominator = %d\n", > > + state->frame_interval.numerator, > > + state->frame_interval.denominator); > > + dev_dbg(dev, "Stream code = 0x%x\n", format->code); > > + return 0; > > +} > > + > > +/** > > + * xsdirxss_irq_handler - Interrupt handler for SDI Rx > > + * @irq: IRQ number > > + * @dev_id: Pointer to device state > > + * > > + * The SDI Rx interrupts are cleared by writing 1 to corresponding bit. > > + * > > + * Return: IRQ_HANDLED after handling interrupts > > + */ > > +static irqreturn_t xsdirxss_irq_handler(int irq, void *dev_id) > > +{ > > + struct xsdirxss_state *state = (struct xsdirxss_state *)dev_id; > > + struct device *dev = state->dev; > > + u32 status; > > + > > + status = xsdirxss_read(state, XSDIRX_ISR_REG); > > + xsdirxss_write(state, XSDIRX_ISR_REG, status); > > + dev_dbg(dev, "interrupt status = 0x%08x\n", status); > > + > > + if (!status) > > + return IRQ_NONE; > > + > > + if (status & XSDIRX_INTR_VIDLOCK_MASK || > > + status & XSDIRX_INTR_VIDUNLOCK_MASK) { > > + u32 val1, val2; > > + struct v4l2_event event = { 0 }; > > + unsigned long flags; > > + > > + dev_dbg(dev, "video lock/unlock interrupt\n"); > > + > > + spin_lock_irqsave(&state->slock, flags); > > + xsdirx_streamflow_control(state, false); > > + > > + val1 = xsdirxss_read(state, XSDIRX_MODE_DET_STAT_REG); > > + val2 = xsdirxss_read(state, XSDIRX_TS_DET_STAT_REG); > > + > > + if ((val1 & XSDIRX_MODE_DET_STAT_MODE_LOCK_MASK) && > > + (val2 & XSDIRX_TS_DET_STAT_LOCKED_MASK)) { > > + u32 mask = XSDIRX_RST_CTRL_RST_CRC_ERRCNT_MASK | > > + XSDIRX_RST_CTRL_RST_EDH_ERRCNT_MASK; > > + > > + dev_dbg(dev, "video lock interrupt\n"); > > + > > + xsdirxss_set(state, XSDIRX_RST_CTRL_REG, mask); > > + xsdirxss_clr(state, XSDIRX_RST_CTRL_REG, mask); > > + > > + val1 = xsdirxss_read(state, XSDIRX_ST352_VALID_REG); > > + val2 = xsdirxss_read(state, XSDIRX_ST352_DS1_REG); > > + > > + dev_dbg(dev, "valid st352 mask = 0x%08x\n", val1); > > + dev_dbg(dev, "st352 payload = 0x%08x\n", val2); > > + > > + if (!xsdirx_get_stream_properties(state)) { > > + state->vidlocked = true; > > + xsdirxss_set_gtclk(state); > > + } else { > > + dev_err(dev, "Unable to get stream properties!\n"); > > + state->vidlocked = false; > > + } > > + } else { > > + dev_dbg(dev, "video unlock interrupt\n"); > > + state->vidlocked = false; > > + } > > + spin_unlock_irqrestore(&state->slock, flags); > > + > > + event.type = V4L2_EVENT_SOURCE_CHANGE; > > + event.u.src_change.changes = V4L2_EVENT_SRC_CH_RESOLUTION; > > + v4l2_subdev_notify_event(&state->subdev, &event); > > + } > > + > > + if (status & (XSDIRX_INTR_UNDERFLOW_MASK | XSDIRX_INTR_OVERFLOW_MASK)) { > > + struct v4l2_event event = { 0 }; > > + > > + dev_dbg(dev, "Video in to AXI4 Stream core under/overflow interrupt\n"); > > + > > + event.type = V4L2_EVENT_XILINX_SDIRX_UND_OVR_FLOW; > > + if (status & XSDIRX_INTR_UNDERFLOW_MASK) > > + event.u.data[0] = XILINX_SDIRX_UNDERFLOW_EVENT; Should this be event.u.data[0] |= XILINX_SDIRX_UNDERFLOW_EVENT; > > + if (status & XSDIRX_INTR_OVERFLOW_MASK) > > + event.u.data[0] = XILINX_SDIRX_OVERFLOW_EVENT; And this event.u.data[0] |= XILINX_SDIRX_OVERFLOW_EVENT; in case both underflow and overflow need to be reported at the same time ? I'm not sure that can happen in practice though, but even if it can't, it also won't hurt to treat the field as a bitflag. > > + > > + v4l2_subdev_notify_event(&state->subdev, &event); > > + } > > + return IRQ_HANDLED; > > +} > > + > > +/** > > + * xsdirxss_subscribe_event - Subscribe to video lock and unlock event > > + * @sd: V4L2 Sub device > > + * @fh: V4L2 File Handle > > + * @sub: Subcribe event structure > > + * > > + * Return: 0 on success, errors otherwise > > + */ > > +static int xsdirxss_subscribe_event(struct v4l2_subdev *sd, > > + struct v4l2_fh *fh, > > + struct v4l2_event_subscription *sub) > > +{ > > + int ret; > > + struct xsdirxss_state *xsdirxss = to_xsdirxssstate(sd); > > + > > + dev_dbg(xsdirxss->dev, "Event subscribed : 0x%08x\n", sub->type); > > + switch (sub->type) { > > + case V4L2_EVENT_XILINX_SDIRX_UND_OVR_FLOW: > > + ret = v4l2_event_subscribe(fh, sub, XSDIRX_MAX_EVENTS, NULL); > > + break; > > + case V4L2_EVENT_SOURCE_CHANGE: > > + ret = v4l2_src_change_event_subscribe(fh, sub); > > + break; > > + default: > > + ret = v4l2_ctrl_subscribe_event(fh, sub); It's customary to have a break at the end of the last case. > > + } > > + return ret; > > +} > > + > > +/** > > + * xsdirxss_s_ctrl - This is used to set the Xilinx SDI Rx V4L2 controls > > + * @ctrl: V4L2 control to be set > > + * > > + * This function is used to set the V4L2 controls for the Xilinx SDI Rx > > + * Subsystem. > > + * > > + * Return: 0 on success, errors otherwise > > + */ > > +static int xsdirxss_s_ctrl(struct v4l2_ctrl *ctrl) > > +{ > > + int ret = 0; > > + struct xsdirxss_state *xsdirxss = > > + container_of(ctrl->handler, struct xsdirxss_state, > > + ctrl_handler); > > + struct device *dev = xsdirxss->dev; > > + unsigned long flags; > > + > > + dev_dbg(dev, "set ctrl id = 0x%08x val = 0x%08x\n", > > + ctrl->id, ctrl->val); > > + > > + spin_lock_irqsave(&xsdirxss->slock, flags); > > + > > + if (xsdirxss->streaming) { > > + spin_unlock_irqrestore(&xsdirxss->slock, flags); > > + dev_err(dev, "Cannot set controls while streaming\n"); > > + return -EINVAL; > > + } > > + > > + XSDIRX_CORE_DISABLE(xsdirxss); > > + switch (ctrl->id) { > > + case V4L2_CID_XILINX_SDIRX_FRAMER: > > + xsdirxss->framer_enable = ctrl->val; > > + if (xsdirxss->framer_enable) { > > + xsdirxss_set(xsdirxss, XSDIRX_MDL_CTRL_REG, > > + XSDIRX_MDL_CTRL_FRM_EN_MASK); > > + } else { > > + xsdirxss_clr(xsdirxss, XSDIRX_MDL_CTRL_REG, > > + XSDIRX_MDL_CTRL_FRM_EN_MASK); > > + } > > + break; > > + case V4L2_CID_XILINX_SDIRX_VIDLOCK_WINDOW: > > + /* > > + * The video lock window is the amount of time for which the > > + * the mode and transport stream should be locked to get the > > + * video lock interrupt. > > + */ > > + xsdirxss->vidlockwin = ctrl->val; > > + xsdirxss_write(xsdirxss, XSDIRX_VID_LOCK_WINDOW_REG, > > + xsdirxss->vidlockwin); > > + break; > > + case V4L2_CID_XILINX_SDIRX_EDH_ERROR_SOURCES: > > + xsdirxss->edhmask = ctrl->val & XSDIRX_EDH_ALLERR_MASK; > > The '& XSDIRX_EDH_ALLERR_MASK' is not needed since the control's 'max' value > is set to XSDIRX_EDH_ALLERR_MASK, so ctrl->val can't contain any other bits. > The control framework ensures that. > > > + xsdirxss_write(xsdirxss, XSDIRX_EDH_ERRCNT_EN_REG, > > + xsdirxss->edhmask); > > + break; > > + case V4L2_CID_XILINX_SDIRX_SEARCH_MODES: > > + if (!ctrl->val) { > > This check should be done in a try_ctrl function instead of s_ctrl. > > Interesting, this is the first bitmask control where you don't want it to > be 0. If we get more of these in the future, then it would make sense if this > is supported in the control framework itself (e.g. if min is set to 1, then > that means that the value can't be 0). But for now just check this in the > try_ctrl() function. > > > + spin_unlock_irqrestore(&xsdirxss->slock, flags); > > + dev_err(dev, "Select at least one mode!\n"); > > + return -EINVAL; > > + } > > + > > + if (xsdirxss->mode == XSDI_STD_3G) { > > + dev_dbg(dev, "Upto 3G supported\n"); > > + ctrl->val &= ~(BIT(XSDIRX_MODE_6G_OFFSET) | > > + BIT(XSDIRX_MODE_12GI_OFFSET) | > > + BIT(XSDIRX_MODE_12GF_OFFSET)); > > + } > > + > > + if (xsdirxss->mode == XSDI_STD_6G) { > > + dev_dbg(dev, "Upto 6G supported\n"); > > + ctrl->val &= ~(BIT(XSDIRX_MODE_12GI_OFFSET) | > > + BIT(XSDIRX_MODE_12GF_OFFSET)); > > + } > > This shouldn't be done here. Instead the 'max' field of the control must be > set correctly based on the mode. You can call v4l2_ctrl_modify_range() in > xsdirxss_probe() to update the max value. Hans, I wrote this comment in v2: "The traditional approach to select timing standards is to use ioctls. Hans, do you think a custom control is fine here, or should the dv timings ioctls be extended (or new sdi timings ioctls created) ? If we go for a single control, I'm a bit concerned that this control will restrict the search when multiple bits are set, but force a specific mode when a single bit is set. I don't have enough experience with SDI to tell whether this is the right behaviour." What do you think ? It's of course hard to standardize an API with a single device as an example (although there's also a spec to help here), so I'm not opposed to using controls in this driver. > > + > > + ret = xsdirx_set_modedetect(xsdirxss, ctrl->val); > > + if (!ret) > > + xsdirxss->searchmask = ctrl->val; > > + break; > > + default: > > + ret = -EINVAL; > > + break; > > + } > > + XSDIRX_CORE_ENABLE(xsdirxss); > > + > > + spin_unlock_irqrestore(&xsdirxss->slock, flags); > > + return ret; > > +} > > + > > +/** > > + * xsdirxss_g_volatile_ctrl - get the Xilinx SDI Rx controls > > + * @ctrl: Pointer to V4L2 control > > + * > > + * Return: 0 on success, errors otherwise > > + */ > > +static int xsdirxss_g_volatile_ctrl(struct v4l2_ctrl *ctrl) > > +{ > > + u32 val; > > + struct xsdirxss_state *xsdirxss = > > + container_of(ctrl->handler, > > + struct xsdirxss_state, ctrl_handler); > > + struct device *dev = xsdirxss->dev; > > + unsigned long flags; > > + > > + spin_lock_irqsave(&xsdirxss->slock, flags); > > + if (!xsdirxss->vidlocked) { > > + spin_unlock_irqrestore(&xsdirxss->slock, flags); > > + dev_err(dev, "Can't get values when video not locked!\n"); > > + return -EINVAL; > > + } > > + switch (ctrl->id) { > > + case V4L2_CID_XILINX_SDIRX_MODE_DETECT: > > + val = xsdirxss_read(xsdirxss, XSDIRX_MODE_DET_STAT_REG); > > + val &= XSDIRX_MODE_DET_STAT_RX_MODE_MASK; > > + > > + switch (val) { > > + case XSDIRX_MODE_SD_MASK: > > + ctrl->val = XSDIRX_MODE_SD_OFFSET; > > + break; > > + case XSDIRX_MODE_HD_MASK: > > + ctrl->val = XSDIRX_MODE_HD_OFFSET; > > + break; > > + case XSDIRX_MODE_3G_MASK: > > + val = xsdirxss_read(xsdirxss, XSDIRX_MODE_DET_STAT_REG); > > + val &= XSDIRX_MODE_DET_STAT_LVLB_3G_MASK; > > + ctrl->val = val ? XSDIRX_MODE_3GB_OFFSET : > > + XSDIRX_MODE_3GA_OFFSET; > > + break; > > + case XSDIRX_MODE_6G_MASK: > > + ctrl->val = XSDIRX_MODE_6G_OFFSET; > > + break; > > + case XSDIRX_MODE_12GI_MASK: > > + ctrl->val = XSDIRX_MODE_12GI_OFFSET; > > + break; > > + case XSDIRX_MODE_12GF_MASK: > > + ctrl->val = XSDIRX_MODE_12GF_OFFSET; > > + break; > > + } > > There is no interrupt that will tell you when the mode changes? It's much > nicer if updating this control is interrupt driven rather than requiring > userspace to poll. > > > + break; > > + case V4L2_CID_XILINX_SDIRX_CRC: > > + ctrl->val = xsdirxss_read(xsdirxss, XSDIRX_CRC_ERRCNT_REG); > > + xsdirxss_write(xsdirxss, XSDIRX_CRC_ERRCNT_REG, 0xffff); > > + break; > > + case V4L2_CID_XILINX_SDIRX_EDH_ERRCNT: > > + val = xsdirxss_read(xsdirxss, XSDIRX_MODE_DET_STAT_REG); > > + val &= XSDIRX_MODE_DET_STAT_RX_MODE_MASK; > > + if (val == XSDIRX_MODE_SD_MASK) { > > + ctrl->val = xsdirxss_read(xsdirxss, > > + XSDIRX_EDH_ERRCNT_REG); > > + } else { > > + spin_unlock_irqrestore(&xsdirxss->slock, flags); > > + dev_dbg(dev, "%d - not in SD mode\n", ctrl->id); > > + return -EINVAL; > > Getting a control value shouldn't fail. Just set ctrl->val to 0 and > return 0. You can leave the dev_dbg though, that can be useful. > > > + } > > + break; > > + case V4L2_CID_XILINX_SDIRX_EDH_STATUS: > > + val = xsdirxss_read(xsdirxss, XSDIRX_MODE_DET_STAT_REG); > > + val &= XSDIRX_MODE_DET_STAT_RX_MODE_MASK; > > + if (val == XSDIRX_MODE_SD_MASK) { > > + ctrl->val = xsdirxss_read(xsdirxss, > > + XSDIRX_EDH_STAT_REG); > > + } else { > > + spin_unlock_irqrestore(&xsdirxss->slock, flags); > > + dev_dbg(dev, "%d - not in SD mode\n", ctrl->id); > > + return -EINVAL; > > Ditto. > > > + } > > + break; > > + case V4L2_CID_XILINX_SDIRX_TS_IS_INTERLACED: > > + ctrl->val = xsdirxss->ts_is_interlaced; > > + break; > > I assume this control will disappear once you added support for > FIELD_ALTERNATE_PROG? I'm not sure FIELD_ALTERNATE_PROG is a good idea. The v4l2_field specifies today how frames are split into multiple buffers. There's an implicit assumption that a frame split into two buffers is captured with interlacing. In the SDI case, the two concepts get decoupled, a progressive frame can be transmitted (and captured) in two separate parts. If we add a *_PROG field, we'll need to duplicate most of the v4l2_field values with a _PROG suffix, as the progressive frame can be captured in alternate buffers on a video node, but also in separate odd and even buffers on two video nodes. Tt the hardware level, data is transmitted with odd lines on one link, and even lines on a second link. There are then two instances of this IP core, one for each link. One instance would receive and process the even lines, the other instance the odd lines. The output of the two instances can then be connected to two separate DMA engines, or combined in the FPGA fabric, depending on how the user designs the system. > > + default: > > + spin_unlock_irqrestore(&xsdirxss->slock, flags); > > + dev_err(dev, "Get Invalid control id 0x%0x\n", ctrl->id); > > + return -EINVAL; > > You can drop the default case altogether: this function will only be called > for volatile controls. > > > + } > > + > > + spin_unlock_irqrestore(&xsdirxss->slock, flags); > > + return 0; > > +} > > + > > +/** > > + * xsdirxss_log_status - Logs the status of the SDI Rx Subsystem > > + * @sd: Pointer to V4L2 subdevice structure > > + * > > + * This function prints the current status of Xilinx SDI Rx Subsystem > > + * > > + * Return: 0 on success > > + */ > > +static int xsdirxss_log_status(struct v4l2_subdev *sd) > > +{ > > + struct xsdirxss_state *xsdirxss = to_xsdirxssstate(sd); > > + u32 i; > > + > > + v4l2_info(sd, "***** SDI Rx subsystem reg dump start *****\n"); > > + v4l2_info(sd, "No : Register Name : Value\n"); > > + for (i = 0; i < ARRAY_SIZE(xsdirxss_regmap); i++) { > > + v4l2_info(sd, "%02d : %s register : 0x%08x\n", i, > > + xsdirxss_regmap[i].name, > > + xsdirxss_read(xsdirxss, xsdirxss_regmap[i].offset)); > > + } > > + v4l2_info(sd, "***** SDI Rx subsystem reg dump end *****\n"); > > + > > + v4l2_ctrl_subdev_log_status(sd); > > + > > + return 0; > > +} > > + > > +/** > > + * xsdirxss_g_frame_interval - Get the frame interval > > + * @sd: V4L2 Sub device > > + * @fi: Pointer to V4l2 Sub device frame interval structure > > + * > > + * This function is used to get the frame interval. > > + * The frame rate can be integral or fractional. > > + * Integral frame rate e.g. numerator = 1000, denominator = 24000 => 24 fps > > + * Fractional frame rate e.g. numerator = 1001, denominator = 24000 => 23.97 fps > > + * > > + * Return: 0 on success > > + */ > > +static int xsdirxss_g_frame_interval(struct v4l2_subdev *sd, > > + struct v4l2_subdev_frame_interval *fi) > > +{ > > + struct xsdirxss_state *xsdirxss = to_xsdirxssstate(sd); > > + unsigned long flags; > > + > > + if (!xsdirxss->vidlocked) { > > + dev_err(xsdirxss->dev, "Video not locked!\n"); > > + return -EINVAL; > > + } > > + > > + spin_lock_irqsave(&xsdirxss->slock, flags); > > + fi->interval = xsdirxss->frame_interval; > > + spin_unlock_irqrestore(&xsdirxss->slock, flags); > > + > > + dev_dbg(xsdirxss->dev, "frame rate numerator = %d denominator = %d\n", > > + xsdirxss->frame_interval.numerator, > > + xsdirxss->frame_interval.denominator); You should print fi->interval, not xsdirxss->frame_interval, as you're outside of the spinlock. > > + return 0; > > +} > > + > > +/** > > + * xsdirxss_s_stream - It is used to start/stop the streaming. > > + * @sd: V4L2 Sub device > > + * @enable: Flag (True / False) > > + * > > + * This function controls the start or stop of streaming for the > > + * Xilinx SDI Rx Subsystem. > > + * > > + * Return: 0 on success, errors otherwise > > + */ > > +static int xsdirxss_s_stream(struct v4l2_subdev *sd, int enable) > > +{ > > + struct xsdirxss_state *xsdirxss = to_xsdirxssstate(sd); > > + struct device *dev = xsdirxss->dev; > > + unsigned long flags; > > + > > + spin_lock_irqsave(&xsdirxss->slock, flags); > > + if (enable == xsdirxss->streaming) { > > + spin_unlock_irqrestore(&xsdirxss->slock, flags); > > + dev_dbg(dev, "already in same streaming state as requested\n"); > > + return 0; > > + } > > + > > + if (enable) { > > + if (!xsdirxss->vidlocked) { > > + spin_unlock_irqrestore(&xsdirxss->slock, flags); > > + dev_err(dev, "Video is not locked\n"); > > + return -EINVAL; > > + } > > + xsdirx_streamflow_control(xsdirxss, true); > > + } else { > > + xsdirx_streamflow_control(xsdirxss, false); > > + } > > + spin_unlock_irqrestore(&xsdirxss->slock, flags); > > + dev_dbg(dev, "Streaming %s\n", enable ? "started" : "stopped"); > > + return 0; > > +} > > + > > +/** > > + * xsdirxss_g_input_status - It is used to determine if the video signal > > + * is present / locked onto or not. > > + * > > + * @sd: V4L2 Sub device > > + * @status: status of signal locked > > + * > > + * This is used to determine if the video signal is present and locked onto > > + * by the SDI Rx core or not based on vidlocked flag. > > + * > > + * Return: zero on success > > + */ > > +static int xsdirxss_g_input_status(struct v4l2_subdev *sd, u32 *status) > > +{ > > + struct xsdirxss_state *xsdirxss = to_xsdirxssstate(sd); > > + unsigned long flags; > > + > > + spin_lock_irqsave(&xsdirxss->slock, flags); > > + if (!xsdirxss->vidlocked) > > + *status = V4L2_IN_ST_NO_SYNC | V4L2_IN_ST_NO_SIGNAL; > > + else > > + *status = 0; > > + > > + spin_unlock_irqrestore(&xsdirxss->slock, flags); > > + return 0; > > +} > > + > > +static struct v4l2_mbus_framefmt * > > +__xsdirxss_get_pad_format(struct xsdirxss_state *xsdirxss, > > + struct v4l2_subdev_pad_config *cfg, > > + unsigned int pad, u32 which) > > +{ > > + switch (which) { > > + case V4L2_SUBDEV_FORMAT_TRY: > > + return v4l2_subdev_get_try_format(&xsdirxss->subdev, cfg, pad); > > + case V4L2_SUBDEV_FORMAT_ACTIVE: > > + return &xsdirxss->src_format; > > + default: > > + return NULL; > > + } > > +} > > + > > +/** > > + * xsdirxss_init_cfg - Initialise the pad format config to default > > + * @sd: Pointer to V4L2 Sub device structure > > + * @cfg: Pointer to sub device pad information structure > > + * > > + * This function is used to initialize the pad format with the default > > + * values. > > + * > > + * Return: 0 on success > > + */ > > +static int xsdirxss_init_cfg(struct v4l2_subdev *sd, > > + struct v4l2_subdev_pad_config *cfg) > > +{ > > + struct xsdirxss_state *xsdirxss = to_xsdirxssstate(sd); > > + struct v4l2_mbus_framefmt *format; > > + > > + format = v4l2_subdev_get_try_format(sd, cfg, 0); > > + *format = xsdirxss->default_format; > > + > > + return 0; > > +} > > + > > +/** > > + * xsdirxss_get_set_format - This is used to get/set the pad format > > + * @sd: Pointer to V4L2 Sub device structure > > + * @cfg: Pointer to sub device pad information structure > > + * @fmt: Pointer to pad level media bus format > > + * > > + * This function is used to get and set the pad format. > > + * Since the pad format is fixed in hardware, it can't be > > + * modified on run time. So set and get are same. > > + * > > + * Return: 0 on success > > + */ > > +static int xsdirxss_get_set_format(struct v4l2_subdev *sd, > > + struct v4l2_subdev_pad_config *cfg, > > + struct v4l2_subdev_format *fmt) > > +{ > > + struct xsdirxss_state *xsdirxss = to_xsdirxssstate(sd); > > + unsigned long flags; > > + > > + spin_lock_irqsave(&xsdirxss->slock, flags); > > + if (!xsdirxss->vidlocked) { > > + spin_unlock_irqrestore(&xsdirxss->slock, flags); > > + dev_err(xsdirxss->dev, "Video not locked!\n"); > > + return -EINVAL; > > + } > > + > > + fmt->format = *__xsdirxss_get_pad_format(xsdirxss, cfg, > > + fmt->pad, fmt->which); > > + > > + spin_unlock_irqrestore(&xsdirxss->slock, flags); > > + dev_dbg(xsdirxss->dev, > > + "stream width %d height %d code %d field %d colorspace %d xfer_func %d quantization %d\n", > > + fmt->format.width, fmt->format.height, > > + fmt->format.code, fmt->format.field, > > + fmt->format.colorspace, fmt->format.xfer_func, > > + fmt->format.quantization); > > + return 0; > > +} > > + > > +/** > > + * xsdirxss_enum_mbus_code - Handle pixel format enumeration > > + * @sd: pointer to v4l2 subdev structure > > + * @cfg: V4L2 subdev pad configuration > > + * @code: pointer to v4l2_subdev_mbus_code_enum structure > > + * > > + * Return: -EINVAL or zero on success > > + */ > > +static int xsdirxss_enum_mbus_code(struct v4l2_subdev *sd, > > + struct v4l2_subdev_pad_config *cfg, > > + struct v4l2_subdev_mbus_code_enum *code) > > +{ > > + struct xsdirxss_state *xsdirxss = to_xsdirxssstate(sd); > > + u32 index = code->index; > > + u32 maxindex; > > + > > + if (xsdirxss->bpc == 10) > > + maxindex = ARRAY_SIZE(xsdirxss_10bpc_mbus_fmts); > > + else > > + maxindex = ARRAY_SIZE(xsdirxss_12bpc_mbus_fmts); > > + > > + if (code->pad || index >= maxindex) > > + return -EINVAL; > > + > > + if (xsdirxss->bpc == 10) > > + code->code = xsdirxss_10bpc_mbus_fmts[index]; > > + else > > + code->code = xsdirxss_12bpc_mbus_fmts[index]; > > + > > + return 0; > > +} > > + > > +/** > > + * xsdirxss_enum_dv_timings - Enumerate all the supported DV timings > > + * @sd: pointer to v4l2 subdev structure > > + * @timings: DV timings structure to be returned. > > + * > > + * Return: -EINVAL incase of invalid index and pad or zero on success > > + */ > > +static int xsdirxss_enum_dv_timings(struct v4l2_subdev *sd, > > + struct v4l2_enum_dv_timings *timings) > > +{ > > + if (timings->index >= ARRAY_SIZE(fmt_cap)) > > + return -EINVAL; > > + > > + if (timings->pad != 0) > > + return -EINVAL; > > + > > + timings->timings = fmt_cap[timings->index]; > > + return 0; > > +} > > + > > +/** > > + * xsdirxss_query_dv_timings - Query for the current DV timings > > + * @sd: pointer to v4l2 subdev structure > > + * @timings: DV timings structure to be returned. > > + * > > + * Return: -ENOLCK when video is not locked, -ERANGE when corresponding timing > > + * entry is not found or zero on success. > > + */ > > +static int xsdirxss_query_dv_timings(struct v4l2_subdev *sd, > > + struct v4l2_dv_timings *timings) > > +{ > > + struct xsdirxss_state *state = to_xsdirxssstate(sd); > > + unsigned int i; > > + unsigned long flags; > > + > > + spin_lock_irqsave(&state->slock, flags); > > + if (!state->vidlocked) { > > + spin_unlock_irqrestore(&state->slock, flags); > > + return -ENOLCK; > > + } > > + > > + for (i = 0; i < ARRAY_SIZE(xsdirxss_dv_timings); i++) { > > + if (state->format.width == xsdirxss_dv_timings[i].width && > > + state->format.height == xsdirxss_dv_timings[i].height && > > + state->frame_interval.denominator == > > + (xsdirxss_dv_timings[i].fps * 1000)) { > > + *timings = xsdirxss_dv_timings[i].timing; > > + state->detected_timings_index = i; > > + spin_unlock_irqrestore(&state->slock, flags); > > + return 0; > > + } > > + } > > This limits the available timings to those explicitly supported by this > driver. Is that intended? What it you receive something that's not in this > list? Do you still want to be able to receive it? > > > + spin_unlock_irqrestore(&state->slock, flags); > > + > > + return -ERANGE; > > +} > > + > > +static int xsdirxss_s_dv_timings(struct v4l2_subdev *sd, > > + struct v4l2_dv_timings *timings) > > +{ > > + struct xsdirxss_state *state = to_xsdirxssstate(sd); > > + u32 i = state->detected_timings_index; > > + unsigned long flags; > > + > > + spin_lock_irqsave(&state->slock, flags); > > + if (!state->vidlocked) { > > + spin_unlock_irqrestore(&state->slock, flags); > > + return -EINVAL; > > + } > > + > > + /* input timing should match query dv_timing */ > > + if (!v4l2_match_dv_timings(timings, > > + &xsdirxss_dv_timings[i].timing, > > + 0, false)) { > > + spin_unlock_irqrestore(&state->slock, flags); > > + return -EINVAL; > > + } > > + > > + state->current_timings = *timings; > > + > > + /* Update the media bus format */ > > + state->src_format = state->format; > > + spin_unlock_irqrestore(&state->slock, flags); > > + > > + return 0; > > +} > > + > > +static int xsdirxss_g_dv_timings(struct v4l2_subdev *sd, > > + struct v4l2_dv_timings *timings) > > +{ > > + struct xsdirxss_state *state = to_xsdirxssstate(sd); > > + > > + *timings = state->current_timings; > > + return 0; > > +} > > + > > +static int xsdirxss_dv_timings_cap(struct v4l2_subdev *sd, > > + struct v4l2_dv_timings_cap *cap) > > +{ > > + if (cap->pad != 0) > > + return -EINVAL; > > + > > + *cap = xsdirxss_timings_cap; > > + return 0; > > +} > > + > > +/* ----------------------------------------------------------------------------- > > + * Media Operations > > + */ > > + > > +static const struct media_entity_operations xsdirxss_media_ops = { > > + .link_validate = v4l2_subdev_link_validate > > +}; > > + > > +static const struct v4l2_ctrl_ops xsdirxss_ctrl_ops = { > > + .g_volatile_ctrl = xsdirxss_g_volatile_ctrl, > > + .s_ctrl = xsdirxss_s_ctrl > > +}; > > + > > +static const struct v4l2_ctrl_config xsdirxss_edh_ctrls[] = { > > + { > > + .ops = &xsdirxss_ctrl_ops, > > + .id = V4L2_CID_XILINX_SDIRX_EDH_ERROR_SOURCES, > > + .name = "SDI Rx : EDH Error Count Enable", > > No space before ':'. > > > + .type = V4L2_CTRL_TYPE_BITMASK, > > + .min = 0, > > + .max = XSDIRX_EDH_ALLERR_MASK, > > + .def = 0, > > + }, { > > + .ops = &xsdirxss_ctrl_ops, > > + .id = V4L2_CID_XILINX_SDIRX_EDH_ERRCNT, > > + .name = "SDI Rx : EDH Error Count", > > + .type = V4L2_CTRL_TYPE_INTEGER, > > + .min = 0, > > + .max = 0xffff, > > + .step = 1, > > + .def = 0, > > + .flags = V4L2_CTRL_FLAG_VOLATILE | V4L2_CTRL_FLAG_READ_ONLY, > > + }, { > > + .ops = &xsdirxss_ctrl_ops, > > + .id = V4L2_CID_XILINX_SDIRX_EDH_STATUS, > > + .name = "SDI Rx : EDH Status", > > + .type = V4L2_CTRL_TYPE_INTEGER, > > This should be a bitmask type. Should this be a control at all? Isn't this more > something to log with log_status? Is this something that an application needs to > use, or is it just a debugging aid? It feels like the latter. > > > + .min = 0, > > + .max = 0xffffffff, > > + .step = 1, > > + .def = 0, > > + .flags = V4L2_CTRL_FLAG_VOLATILE | V4L2_CTRL_FLAG_READ_ONLY, > > + } > > +}; > > + > > +static const struct v4l2_ctrl_config xsdirxss_ctrls[] = { > > + { > > + .ops = &xsdirxss_ctrl_ops, > > + .id = V4L2_CID_XILINX_SDIRX_FRAMER, > > + .name = "SDI Rx : Enable Framer", > > + .type = V4L2_CTRL_TYPE_BOOLEAN, > > + .min = false, > > + .max = true, > > + .step = 1, > > + .def = true, > > + }, { > > + .ops = &xsdirxss_ctrl_ops, > > + .id = V4L2_CID_XILINX_SDIRX_VIDLOCK_WINDOW, > > + .name = "SDI Rx : Video Lock Window", > > + .type = V4L2_CTRL_TYPE_INTEGER, > > + .min = 0, > > + .max = 0xffffffff, > > max should be 0x7fffffff since this is a s32. > > > + .step = 1, > > + .def = XSDIRX_DEFAULT_VIDEO_LOCK_WINDOW, > > + }, { > > + .ops = &xsdirxss_ctrl_ops, > > + .id = V4L2_CID_XILINX_SDIRX_SEARCH_MODES, > > + .name = "SDI Rx : Modes search Mask", > > search -> Search > > > + .type = V4L2_CTRL_TYPE_BITMASK, > > + .min = 0, > > + .max = XSDIRX_DETECT_ALL_MODES, > > + .def = XSDIRX_DETECT_ALL_MODES, > > + }, { > > + .ops = &xsdirxss_ctrl_ops, > > + .id = V4L2_CID_XILINX_SDIRX_MODE_DETECT, > > + .name = "SDI Rx : Mode Detect Status", > > Mode Detect Status -> Detected Mode > > > + .type = V4L2_CTRL_TYPE_INTEGER, > > This is really a menu control. > > > + .min = XSDIRX_MODE_SD_OFFSET, > > + .max = XSDIRX_MODE_12GF_OFFSET, > > + .step = 1, > > + .flags = V4L2_CTRL_FLAG_VOLATILE | V4L2_CTRL_FLAG_READ_ONLY, > > + }, { > > + .ops = &xsdirxss_ctrl_ops, > > + .id = V4L2_CID_XILINX_SDIRX_CRC, > > + .name = "SDI Rx : CRC Error status", > > + .type = V4L2_CTRL_TYPE_INTEGER, > > This is really two controls based on the description in the header: > > One bitmask for the 16 data streams and one accumulated error count. Hans, as this is highly device-specific, and the two values need to be read together, do we really want to mandate all the complexity of creating two controls in a cluster ? It seems overkill to me. > > + .min = 0, > > + .max = 0xffffffff, > > + .step = 1, > > + .def = 0, > > + .flags = V4L2_CTRL_FLAG_VOLATILE | V4L2_CTRL_FLAG_READ_ONLY, > > + }, { > > + .ops = &xsdirxss_ctrl_ops, > > + .id = V4L2_CID_XILINX_SDIRX_TS_IS_INTERLACED, > > + .name = "SDI Rx : TS is Interlaced", > > + .type = V4L2_CTRL_TYPE_BOOLEAN, > > + .min = false, > > + .max = true, > > + .def = false, > > + .step = 1, > > + .flags = V4L2_CTRL_FLAG_VOLATILE | V4L2_CTRL_FLAG_READ_ONLY, > > + }, > > +}; > > + > > +static const struct v4l2_subdev_core_ops xsdirxss_core_ops = { > > + .log_status = xsdirxss_log_status, > > + .subscribe_event = xsdirxss_subscribe_event, > > + .unsubscribe_event = v4l2_event_subdev_unsubscribe, > > +}; > > + > > +static const struct v4l2_subdev_video_ops xsdirxss_video_ops = { > > + .g_frame_interval = xsdirxss_g_frame_interval, > > + .s_stream = xsdirxss_s_stream, > > + .g_input_status = xsdirxss_g_input_status, > > + .query_dv_timings = xsdirxss_query_dv_timings, > > + .g_dv_timings = xsdirxss_g_dv_timings, > > + .s_dv_timings = xsdirxss_s_dv_timings, > > +}; > > + > > +static const struct v4l2_subdev_pad_ops xsdirxss_pad_ops = { > > + .init_cfg = xsdirxss_init_cfg, > > + .get_fmt = xsdirxss_get_set_format, > > + .set_fmt = xsdirxss_get_set_format, > > + .enum_mbus_code = xsdirxss_enum_mbus_code, > > + .enum_dv_timings = xsdirxss_enum_dv_timings, > > + .dv_timings_cap = xsdirxss_dv_timings_cap, > > +}; > > + > > +static const struct v4l2_subdev_ops xsdirxss_ops = { > > + .core = &xsdirxss_core_ops, > > + .video = &xsdirxss_video_ops, > > + .pad = &xsdirxss_pad_ops > > +}; > > + > > +/* ----------------------------------------------------------------------------- > > + * Platform Device Driver > > + */ > > + > > +static int xsdirxss_parse_of(struct xsdirxss_state *xsdirxss) > > +{ > > + struct device_node *node = xsdirxss->dev->of_node; > > + struct device *dev = xsdirxss->dev; > > + int ret; > > + > > + xsdirxss->include_edh = of_property_read_bool(node, "xlnx,include-edh"); > > + dev_dbg(dev, "EDH property = %s\n", > > + xsdirxss->include_edh ? "Present" : "Absent"); > > + > > + ret = of_property_read_u32(node, "xlnx,line-rate", &xsdirxss->mode); > > + if (ret < 0) { > > + dev_err(dev, "xlnx,line-rate property not found\n"); > > + return ret; > > + } > > + > > + if (xsdirxss->mode != XSDI_STD_3G && xsdirxss->mode != XSDI_STD_6G && > > + xsdirxss->mode != XSDI_STD_12G_8DS) { > > + dev_err(dev, "Invalid Line Rate\n"); > > + return -EINVAL; > > + } > > + > > + dev_dbg(dev, "SDI Rx Line Rate / mode = %d\n", xsdirxss->mode); > > + > > + ret = of_property_read_u32(node, "xlnx,bpc", &xsdirxss->bpc); > > + if (ret == -EINVAL) { > > + xsdirxss->bpc = 10; > > + dev_dbg(dev, "set default bpc as 10\n"); > > + } else if (ret < 0) { > > + dev_err(dev, "failed to get xlnx,bpc\n"); > > + return ret; > > + } > > + > > + if (xsdirxss->bpc != 10 && xsdirxss->bpc != 12) { > > + dev_err(dev, "bits per component=%u. Can be 10 or 12 only\n", > > + xsdirxss->bpc); > > + return -EINVAL; > > + } > > + > > + return ret; > > +} > > + > > +static int xsdirxss_probe(struct platform_device *pdev) > > +{ > > + struct v4l2_subdev *subdev; > > + struct xsdirxss_state *xsdirxss; > > + struct device *dev; > > + int ret, irq; > > + unsigned int num_ctrls, i; > > + > > + xsdirxss = devm_kzalloc(&pdev->dev, sizeof(*xsdirxss), GFP_KERNEL); > > + if (!xsdirxss) > > + return -ENOMEM; > > + > > + xsdirxss->dev = &pdev->dev; > > + dev = xsdirxss->dev; > > + > > + spin_lock_init(&xsdirxss->slock); > > + ret = xsdirxss_parse_of(xsdirxss); > > + if (ret < 0) > > + return ret; > > + > > + xsdirxss->iomem = devm_platform_ioremap_resource(pdev, 0); > > + if (IS_ERR(xsdirxss->iomem)) > > + return PTR_ERR(xsdirxss->iomem); > > + > > + xsdirxss->num_clks = ARRAY_SIZE(xsdirxss_clks); > > + xsdirxss->clks = devm_kcalloc(dev, xsdirxss->num_clks, > > + sizeof(*xsdirxss->clks), GFP_KERNEL); > > + if (!xsdirxss->clks) > > + return -ENOMEM; > > + > > + for (i = 0; i < xsdirxss->num_clks; i++) > > + xsdirxss->clks[i].id = xsdirxss_clks[i]; > > + > > + ret = devm_clk_bulk_get(dev, xsdirxss->num_clks, xsdirxss->clks); > > + if (ret) > > + return ret; > > + > > + ret = clk_bulk_prepare_enable(xsdirxss->num_clks, xsdirxss->clks); > > + if (ret) > > + return ret; > > + > > + /* Reset the core */ > > + xsdirx_streamflow_control(xsdirxss, false); > > + XSDIRX_CORE_DISABLE(xsdirxss); > > + /* Clear all interrupts */ > > + xsdirxss_set(xsdirxss, XSDIRX_ISR_REG, XSDIRX_INTR_ALL_MASK); > > + xsdirxss_clr(xsdirxss, XSDIRX_IER_REG, XSDIRX_INTR_ALL_MASK); > > + xsdirxss_set(xsdirxss, XSDIRX_IER_REG, XSDIRX_INTR_ALL_MASK); > > + XSDIRX_GLOBAL_INTR_ENABLE(xsdirxss); > > + xsdirxss_write(xsdirxss, XSDIRX_CRC_ERRCNT_REG, 0xffff); > > + > > + /* Register interrupt handler */ > > + irq = platform_get_irq(pdev, 0); > > + ret = devm_request_threaded_irq(dev, irq, NULL, xsdirxss_irq_handler, > > + IRQF_ONESHOT, dev_name(dev), xsdirxss); > > + if (ret) { > > + dev_err(dev, "Err = %d Interrupt handler reg failed!\n", > > + ret); > > + goto clk_err; > > + } > > + > > + /* Initialize V4L2 subdevice and media entity */ > > + xsdirxss->pad.flags = MEDIA_PAD_FL_SOURCE; > > + > > + /* Initialize the default format */ > > + if (xsdirxss->bpc == 10) > > + xsdirxss->default_format.code = MEDIA_BUS_FMT_UYVY10_1X20; > > + else > > + xsdirxss->default_format.code = MEDIA_BUS_FMT_UYVY12_1X24; > > + xsdirxss->default_format.field = V4L2_FIELD_NONE; > > + xsdirxss->default_format.colorspace = V4L2_COLORSPACE_REC709; > > + xsdirxss->default_format.width = XSDIRX_DEFAULT_WIDTH; > > + xsdirxss->default_format.height = XSDIRX_DEFAULT_HEIGHT; > > + xsdirxss->default_format.xfer_func = V4L2_XFER_FUNC_709; > > + xsdirxss->default_format.quantization = V4L2_QUANTIZATION_LIM_RANGE; > > + > > + xsdirxss->format = xsdirxss->default_format; > > + > > + /* Initialize V4L2 subdevice and media entity */ > > + subdev = &xsdirxss->subdev; > > + v4l2_subdev_init(subdev, &xsdirxss_ops); > > + > > + subdev->dev = &pdev->dev; > > + strscpy(subdev->name, dev_name(dev), sizeof(subdev->name)); > > + > > + subdev->flags = V4L2_SUBDEV_FL_HAS_EVENTS | V4L2_SUBDEV_FL_HAS_DEVNODE; > > + > > + subdev->entity.ops = &xsdirxss_media_ops; > > + > > + v4l2_set_subdevdata(subdev, xsdirxss); > > + > > + ret = media_entity_pads_init(&subdev->entity, 1, &xsdirxss->pad); > > + if (ret < 0) > > + goto error; > > + > > + /* Initialise and register the controls */ > > + num_ctrls = ARRAY_SIZE(xsdirxss_ctrls); > > + > > + if (xsdirxss->include_edh) > > + num_ctrls += ARRAY_SIZE(xsdirxss_edh_ctrls); > > + > > + v4l2_ctrl_handler_init(&xsdirxss->ctrl_handler, num_ctrls); > > + > > + for (i = 0; i < ARRAY_SIZE(xsdirxss_ctrls); i++) { > > + struct v4l2_ctrl *ctrl; > > + > > + dev_dbg(dev, "%d %s ctrl = 0x%x\n", i, xsdirxss_ctrls[i].name, > > + xsdirxss_ctrls[i].id); > > + > > + ctrl = v4l2_ctrl_new_custom(&xsdirxss->ctrl_handler, > > + &xsdirxss_ctrls[i], NULL); You can drop the ctrl variable, it's not used. Same below. > > + } > > + > > + if (xsdirxss->include_edh) { > > + for (i = 0; i < ARRAY_SIZE(xsdirxss_edh_ctrls); i++) { > > + struct v4l2_ctrl *ctrl; > > + > > + dev_dbg(dev, "%d %s ctrl = 0x%x\n", i, > > + xsdirxss_edh_ctrls[i].name, > > + xsdirxss_edh_ctrls[i].id); > > + > > + ctrl = v4l2_ctrl_new_custom(&xsdirxss->ctrl_handler, > > + &xsdirxss_edh_ctrls[i], > > + NULL); > > + } > > + } > > + > > + if (xsdirxss->ctrl_handler.error) { > > + dev_err(dev, "failed to add controls\n"); > > + ret = xsdirxss->ctrl_handler.error; > > + goto error; > > + } > > + > > + subdev->ctrl_handler = &xsdirxss->ctrl_handler; > > + > > + ret = v4l2_ctrl_handler_setup(&xsdirxss->ctrl_handler); > > + if (ret < 0) { > > + dev_err(dev, "failed to set controls\n"); > > + goto error; > > + } > > + > > + platform_set_drvdata(pdev, xsdirxss); > > + > > + ret = v4l2_async_register_subdev(subdev); > > + if (ret < 0) { > > + dev_err(dev, "failed to register subdev\n"); > > + goto error; > > + } > > + > > + xsdirxss->prev_is_frac = -1; > > + > > + XSDIRX_CORE_ENABLE(xsdirxss); > > + > > + return 0; > > +error: > > + v4l2_ctrl_handler_free(&xsdirxss->ctrl_handler); > > + media_entity_cleanup(&subdev->entity); > > + XSDIRX_GLOBAL_INTR_DISABLE(xsdirxss); > > + xsdirxss_clr(xsdirxss, XSDIRX_IER_REG, XSDIRX_INTR_ALL_MASK); > > +clk_err: > > + clk_bulk_disable_unprepare(xsdirxss->num_clks, xsdirxss->clks); > > + return ret; > > +} > > + > > +static int xsdirxss_remove(struct platform_device *pdev) > > +{ > > + struct xsdirxss_state *xsdirxss = platform_get_drvdata(pdev); > > + struct v4l2_subdev *subdev = &xsdirxss->subdev; > > + > > + XSDIRX_CORE_DISABLE(xsdirxss); > > + XSDIRX_GLOBAL_INTR_DISABLE(xsdirxss); > > + xsdirxss_clr(xsdirxss, XSDIRX_IER_REG, XSDIRX_INTR_ALL_MASK); > > + xsdirx_streamflow_control(xsdirxss, false); > > + > > + v4l2_async_unregister_subdev(subdev); > > + v4l2_ctrl_handler_free(&xsdirxss->ctrl_handler); > > + media_entity_cleanup(&subdev->entity); > > + > > + clk_bulk_disable_unprepare(xsdirxss->num_clks, xsdirxss->clks); > > + > > + return 0; > > +} > > + > > +static const struct of_device_id xsdirxss_of_id_table[] = { > > + { .compatible = "xlnx,v-smpte-uhdsdi-rx-ss-2.0" }, > > + { } > > +}; > > +MODULE_DEVICE_TABLE(of, xsdirxss_of_id_table); > > + > > +static struct platform_driver xsdirxss_driver = { > > + .driver = { > > + .name = "xilinx-sdirxss", > > + .of_match_table = xsdirxss_of_id_table, > > + }, > > + .probe = xsdirxss_probe, > > + .remove = xsdirxss_remove, > > +}; > > + > > +module_platform_driver(xsdirxss_driver); > > + > > +MODULE_AUTHOR("Vishal Sagar "); > > +MODULE_DESCRIPTION("Xilinx SDI Rx Subsystem Driver"); > > +MODULE_LICENSE("GPL v2"); > > diff --git a/include/uapi/linux/v4l2-controls.h b/include/uapi/linux/v4l2-controls.h > > index 62271418c1be..9526a6acc6f4 100644 > > --- a/include/uapi/linux/v4l2-controls.h > > +++ b/include/uapi/linux/v4l2-controls.h > > @@ -198,6 +198,12 @@ enum v4l2_colorfx { > > */ > > #define V4L2_CID_USER_ATMEL_ISC_BASE (V4L2_CID_USER_BASE + 0x10c0) > > > > +/* > > + * The base for the Xilinx SDI Rx driver controls. > > + * We reserve 16 controls for this driver. > > + */ > > +#define V4L2_CID_USER_XILINX_SDIRX_BASE (V4L2_CID_USER_BASE + 0x10e0) > > + > > /* MPEG-class control IDs */ > > /* The MPEG controls are applicable to all codec controls > > * and the 'MPEG' part of the define is historical */ > > diff --git a/include/uapi/linux/xilinx-sdirxss.h b/include/uapi/linux/xilinx-sdirxss.h > > new file mode 100644 > > index 000000000000..1bcbf5852b22 > > --- /dev/null > > +++ b/include/uapi/linux/xilinx-sdirxss.h > > @@ -0,0 +1,283 @@ > > +/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ > > +/* > > + * Xilinx SDI Rx Subsystem mode, event, custom timings and > > + * flag definitions. > > + * > > + * Copyright (C) 2019 - 2020 Xilinx, Inc. > > + * > > + * Contacts: Vishal Sagar > > + */ > > + > > +#ifndef __UAPI_XILINX_SDIRXSS_H__ > > +#define __UAPI_XILINX_SDIRXSS_H__ > > + > > +#include > > +#include > > +#include > > +#include > > + > > +/* > > + * Events > > + * > > + * V4L2_EVENT_XILINX_SDIRX_UND_OVR_FLOW: Video in to AXI4 Stream core > > + * under/overflowed during a resolution or frame rate change. > > + */ > > +#define V4L2_EVENT_XILINX_SDIRX_CLASS (V4L2_EVENT_PRIVATE_START | 0x200) > > +#define V4L2_EVENT_XILINX_SDIRX_UND_OVR_FLOW \ > > + (V4L2_EVENT_XILINX_SDIRX_CLASS | 0x1) > > + > > +#define XILINX_SDIRX_UNDERFLOW_EVENT BIT(1) > > +#define XILINX_SDIRX_OVERFLOW_EVENT BIT(2) > > +/* > > + * This enum is used to prepare the bitmask of modes to be detected > > + */ > > +enum { > > + XSDIRX_MODE_SD_OFFSET = 0, > > + XSDIRX_MODE_HD_OFFSET, > > + XSDIRX_MODE_3GA_OFFSET, > > + XSDIRX_MODE_3GB_OFFSET, > > + XSDIRX_MODE_6G_OFFSET, > > + XSDIRX_MODE_12GI_OFFSET, > > + XSDIRX_MODE_12GF_OFFSET, > > + XSDIRX_MODE_NUM_SUPPORTED, > > +}; > > These are all standard SDI modes, right? > > > + > > +#define XSDIRX_DETECT_ALL_MODES (BIT(XSDIRX_MODE_SD_OFFSET) | \ > > + BIT(XSDIRX_MODE_HD_OFFSET) | \ > > + BIT(XSDIRX_MODE_3GA_OFFSET) | \ > > + BIT(XSDIRX_MODE_3GB_OFFSET) | \ > > + BIT(XSDIRX_MODE_6G_OFFSET) | \ > > + BIT(XSDIRX_MODE_12GI_OFFSET) | \ > > + BIT(XSDIRX_MODE_12GF_OFFSET)) > > + > > +/* > > + * EDH - Error Detection and Handling. > > + * In the SD-SDI mode, the UHD-SDI core fully supports RP 165. > > + * The bitmask is named as XSDIRX_EDH_ERRCNT_XX_YY_ERR except > > + * for packet checksum error. > > + * > > + * XX - EDH Error Types > > + * ANC - Ancillary Data Packet Errors > > + * FF - Full Field Errors > > + * AP - Active Portion Errors > > + * > > + * YY - Error Flags > > + * EDH - error detected here > > + * EDA - error Detected already > > + * IDH - internal error detected here > > + * IDA - internal error detected already > > + * UES - unknown error status > > + * > > + * Refer to Sec 4.3 Error Flags in RP 165-1994 for details > > + */ > > + > > +#define XSDIRX_EDH_ERRCNT_ANC_EDH_ERR BIT(0) > > +#define XSDIRX_EDH_ERRCNT_ANC_EDA_ERR BIT(1) > > +#define XSDIRX_EDH_ERRCNT_ANC_IDH_ERR BIT(2) > > +#define XSDIRX_EDH_ERRCNT_ANC_IDA_ERR BIT(3) > > +#define XSDIRX_EDH_ERRCNT_ANC_UES_ERR BIT(4) > > +#define XSDIRX_EDH_ERRCNT_FF_EDH_ERR BIT(5) > > +#define XSDIRX_EDH_ERRCNT_FF_EDA_ERR BIT(6) > > +#define XSDIRX_EDH_ERRCNT_FF_IDH_ERR BIT(7) > > +#define XSDIRX_EDH_ERRCNT_FF_IDA_ERR BIT(8) > > +#define XSDIRX_EDH_ERRCNT_FF_UES_ERR BIT(9) > > +#define XSDIRX_EDH_ERRCNT_AP_EDH_ERR BIT(10) > > +#define XSDIRX_EDH_ERRCNT_AP_EDA_ERR BIT(11) > > +#define XSDIRX_EDH_ERRCNT_AP_IDH_ERR BIT(12) > > +#define XSDIRX_EDH_ERRCNT_AP_IDA_ERR BIT(13) > > +#define XSDIRX_EDH_ERRCNT_AP_UES_ERR BIT(14) > > +#define XSDIRX_EDH_ERRCNT_PKT_CHKSUM_ERR BIT(15) > > + > > +#define XSDIRX_EDH_ALLERR_MASK 0xFFFF > > Lowercase 0xffff. > > And these error conditions are also standardized? > > If so, then I think these defines/enums can be part of V4L2 itself rather > than Xilinx specific. > > > + > > +/* > > + * V4L2 Controls - We reserved 16 controls for this driver. > > I'd increase that to 32. > > > + * > > + * The V4L2_CID_XILINX_SDIRX_EDH_* controls are present only if > > + * EDH is enabled. > > + * The controls which can be set should only be set before enabling > > + * streaming. The controls which can be got should be called while > > + * streaming to get correct values. > > + * The V4L2_CID_XILINX_SDIRX_MODE_DETECT can be called when query dv timing > > query dv timing -> query_dv_timings > > > + * returns a valid timing. > > + */ > > + > > +/* > > + * Framer Control to enable or disable the framer. When this is set, the framer > > + * automatically readjusts the output word alignment to match the alignment of > > + * each timing reference signal(TRS). Normally this should be set. But user may > > + * control this input to implement TRS filtering to prevent a signal misaligned > > + * TRS from causing erroneous alignment changes. > > + * Refer to PG205 rx_frame_en for more details. > > + */ > > +#define V4L2_CID_XILINX_SDIRX_FRAMER (V4L2_CID_USER_XILINX_SDIRX_BASE + 1) > > + > > +/* > > + * Video Lock Window Control to set the video lock window value > > + * This is the amount of time the mode and transport stream need > > + * to be locked before a video lock interrupt occurs. > > + */ > > +#define V4L2_CID_XILINX_SDIRX_VIDLOCK_WINDOW (V4L2_CID_USER_XILINX_SDIRX_BASE + 2) > > + > > +/* > > + * EDH Error Mask Control to enable EDH error count > > + * This control takes in the bitmask of XSDIRX_EDH_ERRCNT_*_ERR to enable counting > > + * such errors. > > + */ > > +#define V4L2_CID_XILINX_SDIRX_EDH_ERROR_SOURCES (V4L2_CID_USER_XILINX_SDIRX_BASE + 3) > > If these EDH error sources are from the SDI standard, then this can become a standard > control as well. > > > + > > +/* > > + * Mode search Control to pass the bit mask of modes to detect. > > + * If only 1 bit is set, the driver programs IP to be in fixed mode else > > + * in multi detection mode. > > + * > > + * Set this when not streaming. > > + * > > + * bit 0 set to detect SD mode, > > + * bit 1 set to detect HD mode, > > + * bit 2 set to detect 3GA mode, > > + * bit 3 set to detect 3GB mode, > > + * bit 4 set to detect 6G mode, > > + * bit 5 set to detect 12G integer frame rate mode, > > + * bit 6 set to detect 12G fractional frame rate mode, > > + */ > > +#define V4L2_CID_XILINX_SDIRX_SEARCH_MODES (V4L2_CID_USER_XILINX_SDIRX_BASE + 4) > > Same here if these modes are standardized. > > > + > > +/* > > + * Get Detected SDI Mode control (read only) > > + * > > + * Control Value - Mode detected > > + * 0 - SD > > + * 1 - HD > > + * 2 - 3GA > > + * 3 - 3GB > > + * 4 - 6G > > + * 5 - 12G integer frame rate > > + * 6 - 12G fractional frame rate > > + */ > > +#define V4L2_CID_XILINX_SDIRX_MODE_DETECT (V4L2_CID_USER_XILINX_SDIRX_BASE + 5) > > Ditto. > > > + > > +/* Get number of CRC errors status control > > + * > > + * When a CRC is detected on a line, the CRC error signal of that data stream > > + * becomes asserted starting a few clock cycles after the last CRC word is > > + * output on the data stream ports following the EAV that ends the line > > + * containing the error. The CRC signal remains asserted for one line time. > > + * > > + * The LSB 16 bits of value returned by thsi control represent the error > > + * signal on each of 16 data streams. The MSB 16 bits contains the accumulated > > + * error count. > > + * > > + * Refer to PG205 rx_crc_err_dsX (X = 1 to 16) description for details. > > + */ > > +#define V4L2_CID_XILINX_SDIRX_CRC (V4L2_CID_USER_XILINX_SDIRX_BASE + 6) > > As suggested earlier, I think this should be split into two controls. > > > + > > +/* > > + * Get EDH error count control > > + * > > + * Reading this control will give the number of EDH errors occurred based > > + * on the bitmask passed in V4L2_CID_XILINX_SDIRX_EDH_ERROR_SOURCES. > > + * > > + * It increments once per field when any of the error conditions enabled by > > + * the RX_EDH_ERRCNT_EN register bit(s) occur during that field. > > + * > > + * Refer to PG205 rx_edh_errcnt > > + */ > > +#define V4L2_CID_XILINX_SDIRX_EDH_ERRCNT (V4L2_CID_USER_XILINX_SDIRX_BASE + 7) > > Even though the EDH errors appear to be standard, I'm not sure if this specific control > can be standardized. The precise behavior of a counter like this might differ between > HW implementations. > > > + > > +/* > > + * Get EDH status control > > + * > > + * This control returns the RX_EDH_STS register contents. > > + * Refer to PG290 register space section for more details. > > + */ > > +#define V4L2_CID_XILINX_SDIRX_EDH_STATUS (V4L2_CID_USER_XILINX_SDIRX_BASE + 8) > > As mentioned above: this is a dubious control, reporting it in log_status seems > a more logical approach. > > > + > > +/* Get Transport Interlaced status whether it is interlaced or not */ > > +#define V4L2_CID_XILINX_SDIRX_TS_IS_INTERLACED (V4L2_CID_USER_XILINX_SDIRX_BASE + 9) > > And as also mentioned above, this will be replaced by a new FIELD_ALTERNATE_PROG? > > > + > > +/* > > + * Xilinx DV timings > > + * TODO - Remove these once they are in v4l2-dv-timings.h > > + */ > > +#define XLNX_V4L2_DV_BT_2048X1080P24 { \ > > + .type = V4L2_DV_BT_656_1120, \ > > + V4L2_INIT_BT_TIMINGS(2048, 1080, 0, \ > > + V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ > > + 74250000, 510, 44, 148, 4, 5, 36, 0, 0, 0, \ > > + V4L2_DV_BT_STD_SDI) \ > > +} > > + > > +#define XLNX_V4L2_DV_BT_2048X1080P25 { \ > > + .type = V4L2_DV_BT_656_1120, \ > > + V4L2_INIT_BT_TIMINGS(2048, 1080, 0, \ > > + V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ > > + 74250000, 400, 44, 148, 4, 5, 36, 0, 0, 0, \ > > + V4L2_DV_BT_STD_SDI) \ > > +} > > + > > +#define XLNX_V4L2_DV_BT_2048X1080P30 { \ > > + .type = V4L2_DV_BT_656_1120, \ > > + V4L2_INIT_BT_TIMINGS(2048, 1080, 0, \ > > + V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ > > + 74250000, 66, 20, 66, 4, 5, 36, 0, 0, 0, \ > > + V4L2_DV_BT_STD_SDI) \ > > +} > > + > > +#define XLNX_V4L2_DV_BT_2048X1080I48 { \ > > + .type = V4L2_DV_BT_656_1120, \ > > + V4L2_INIT_BT_TIMINGS(2048, 1080, 1, \ > > + V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ > > + 74250000, 329, 44, 329, 2, 5, 15, 3, 5, 15, \ > > + V4L2_DV_BT_STD_SDI) \ > > +} > > + > > +#define XLNX_V4L2_DV_BT_2048X1080I50 { \ > > + .type = V4L2_DV_BT_656_1120, \ > > + V4L2_INIT_BT_TIMINGS(2048, 1080, 1, \ > > + V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ > > + 74250000, 274, 44, 274, 2, 5, 15, 3, 5, 15, \ > > + V4L2_DV_BT_STD_SDI) \ > > +} > > + > > +#define XLNX_V4L2_DV_BT_2048X1080I60 { \ > > + .type = V4L2_DV_BT_656_1120, \ > > + V4L2_INIT_BT_TIMINGS(2048, 1080, 1, \ > > + V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ > > + 74250000, 66, 20, 66, 2, 5, 15, 3, 5, 15, \ > > + V4L2_DV_BT_STD_SDI) \ > > +} > > + > > +#define XLNX_V4L2_DV_BT_2048X1080P48 { \ > > + .type = V4L2_DV_BT_656_1120, \ > > + V4L2_INIT_BT_TIMINGS(2048, 1080, 0, \ > > + V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ > > + 148500000, 510, 44, 148, 4, 5, 36, 0, 0, 0, \ > > + V4L2_DV_BT_STD_SDI) \ > > +} > > + > > +#define XLNX_V4L2_DV_BT_2048X1080P50 { \ > > + .type = V4L2_DV_BT_656_1120, \ > > + V4L2_INIT_BT_TIMINGS(2048, 1080, 0, \ > > + V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ > > + 148500000, 400, 44, 148, 4, 5, 36, 0, 0, 0, \ > > + V4L2_DV_BT_STD_SDI) \ > > +} > > + > > +#define XLNX_V4L2_DV_BT_2048X1080P60 { \ > > + .type = V4L2_DV_BT_656_1120, \ > > + V4L2_INIT_BT_TIMINGS(2048, 1080, 0, \ > > + V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ > > + 148500000, 88, 44, 20, 4, 5, 36, 0, 0, 0, \ > > + V4L2_DV_BT_STD_SDI) \ > > +} > > + > > +#define XLNX_V4L2_DV_BT_1920X1080I48 { \ > > + .type = V4L2_DV_BT_656_1120, \ > > + V4L2_INIT_BT_TIMINGS(1920, 1080, 1, \ > > + V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ > > + 148500000, 371, 88, 371, 2, 5, 15, 3, 5, 15, \ > > + V4L2_DV_BT_STD_SDI) \ > > +} > > + > > +#endif /* __UAPI_XILINX_SDIRXSS_H__ */ -- Regards, Laurent Pinchart