From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-11.5 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,USER_AGENT_SANE_1 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C225DC433E1 for ; Wed, 15 Jul 2020 22:48:09 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 53F7320658 for ; Wed, 15 Jul 2020 22:48:09 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="loDACpxs"; dkim=fail reason="signature verification failed" (1024-bit key) header.d=xilinx.onmicrosoft.com header.i=@xilinx.onmicrosoft.com header.b="YLhlEu9f" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 53F7320658 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=xilinx.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References:Message-ID: Subject:To:From:Date:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=aVrglFgQB5OufMa+2NjoOaVT/kfPE8D0GdcLC0fomUw=; b=loDACpxs8m8tolzeie9n6e/ls 4Rn2G0BqXgEqrfJpBpe2i/6I+G/LMmuRj+1060TKrOpH9kKnrISthnEh9niTrkP+KwsVMvxeCc3ZQ w9Am5VIAcfxxdKEnsKOZ+fgCCQcUKoWRk7alTDXH97asX+o16DELrQJiK/NnIEBmZ+SKW80mxJZci cNy0bfq1jInjG+XPkMRSgsJ711xKFWimiT1jJOKTm1cMO56AeaKcKbIU1ZYGDHcSzuFlnbysVdW68 NASSUWXGS44Vtu59pwYnvhsN5xGOw5MBtVBwG27bPD5cXqSg2sEIMRErMvTqcniz4ysMcgdwxddbB AYzgk+ZDg==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1jvqA4-0003rq-Lv; Wed, 15 Jul 2020 22:46:00 +0000 Received: from mail-eopbgr690085.outbound.protection.outlook.com ([40.107.69.85] helo=NAM04-CO1-obe.outbound.protection.outlook.com) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1jvq9z-0003oy-MC for linux-arm-kernel@lists.infradead.org; Wed, 15 Jul 2020 22:45:58 +0000 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=SlRagE1Rp/YbtEl670aemNGT3fUWLifOjuCgH7pSNgwb14ryDJO81Pnvgt5ktqE+lu+XEvLBs/1zkhjuIyQnjaye1tyv5nB7VrfRoyJTd49XkEtt/yQwJSmUZzJHNRWO0btUHMoq1m+v7i4OY6jG8LQaujGOXnykkj+xTuMhYgmvZF9GYBoupuyKOBf1uccZGlNGsRH6GO6F8Lc3rO6kaH+YuUSRL9xeF2EhwxdGPa0CoZUq/GxVCJfKv9omeju4Ig6hkxVtcK1jGeXCybjrXiRRSKW+uIfs+jWUKj4mmWIMVoHtIXYmtdHf/0c0FNVqP+7IPz83AqLH7y2KzKXRjA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=h6i4xwLiTh1MUghqkOvaUnXTiyDy2X/KyD9b1tLUQWE=; b=GOOHuE8k6EV37k2V08zhKJR3rcnEnAnOOH01JxJ2hnWC44wdYlpvYO0+i3BeR7eJM/qyXim7z7KMa2HJ4ZRGUYqhCmR3dwvpHiXcCce6xRK8/KTrJrJnxk7/KYtYIp/jvUuVGZnFzLertbrXmWZEG0MMZfkEgPZGXE6ClxttDH+ceVqMj3LgjXRcPaiAXc3iqfQg454XP1L1Oc8Tb/uq35sO/RJVN37JUjOs1lA2RGPGHJNyDxFQZlj3n/o1XZxf2TZsXVNHBjL7k7kckz/IFJ2i/jaNckQJbzNzevB25v5d4LWmK3ZtPcDBkBylJlu8oWT4EZOX48hfD6aIqwHGow== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 149.199.60.83) smtp.rcpttodomain=xs4all.nl smtp.mailfrom=xilinx.com; dmarc=bestguesspass action=none header.from=xilinx.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=xilinx.onmicrosoft.com; s=selector2-xilinx-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=h6i4xwLiTh1MUghqkOvaUnXTiyDy2X/KyD9b1tLUQWE=; b=YLhlEu9f2UQP1B3cjsv0qbChqJkjeG65/mOz1HjZzncEmq/gQuLgRxaUteQVKmoqwVw/ecXKqpTPaujeuwY9z7IdoxT4cQy6hiyELZvHwYjs7yPI/MsCMvvWcEcB65kfeehBX7cJiIPTo5FuPwE8duzE6vu6zedHx/upHmXT3qM= Received: from DM3PR12CA0101.namprd12.prod.outlook.com (2603:10b6:0:55::21) by CY4PR02MB2501.namprd02.prod.outlook.com (2603:10b6:903:72::11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3174.22; Wed, 15 Jul 2020 22:45:49 +0000 Received: from CY1NAM02FT058.eop-nam02.prod.protection.outlook.com (2603:10b6:0:55:cafe::ec) by DM3PR12CA0101.outlook.office365.com (2603:10b6:0:55::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3195.18 via Frontend Transport; Wed, 15 Jul 2020 22:45:48 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 149.199.60.83) smtp.mailfrom=xilinx.com; xs4all.nl; dkim=none (message not signed) header.d=none;xs4all.nl; dmarc=bestguesspass action=none header.from=xilinx.com; Received-SPF: Pass (protection.outlook.com: domain of xilinx.com designates 149.199.60.83 as permitted sender) receiver=protection.outlook.com; client-ip=149.199.60.83; helo=xsj-pvapsmtpgw01; Received: from xsj-pvapsmtpgw01 (149.199.60.83) by CY1NAM02FT058.mail.protection.outlook.com (10.152.74.149) with Microsoft SMTP Server id 15.20.3195.18 via Frontend Transport; Wed, 15 Jul 2020 22:45:47 +0000 Received: from [149.199.38.66] (port=45491 helo=xsj-pvapsmtp01) by xsj-pvapsmtpgw01 with esmtp (Exim 4.90) (envelope-from ) id 1jvq8C-0004lZ-5d; Wed, 15 Jul 2020 15:44:04 -0700 Received: from [127.0.0.1] (helo=localhost) by xsj-pvapsmtp01 with smtp (Exim 4.63) (envelope-from ) id 1jvq9r-0003ij-FG; Wed, 15 Jul 2020 15:45:47 -0700 Received: from xsj-pvapsmtp01 (mail.xilinx.com [149.199.38.66] (may be forged)) by xsj-smtp-dlp1.xlnx.xilinx.com (8.13.8/8.13.1) with ESMTP id 06FMjgk0030737; Wed, 15 Jul 2020 15:45:42 -0700 Received: from [172.19.2.244] (helo=xsjhyunkubuntu) by xsj-pvapsmtp01 with esmtp (Exim 4.63) (envelope-from ) id 1jvq9m-0003hq-KM; Wed, 15 Jul 2020 15:45:42 -0700 Received: by xsjhyunkubuntu (Postfix, from userid 13638) id D00172C6BB2; Wed, 15 Jul 2020 15:42:49 -0700 (PDT) Date: Wed, 15 Jul 2020 15:42:49 -0700 From: Hyun Kwon To: Vishal Sagar Subject: Re: [PATCH v3 3/3] media: v4l: xilinx: Add Xilinx UHD-SDI Rx Subsystem driver Message-ID: <20200715224248.GA3490@xilinx.com> References: <20200618053304.14551-1-vishal.sagar@xilinx.com> <20200618053304.14551-4-vishal.sagar@xilinx.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20200618053304.14551-4-vishal.sagar@xilinx.com> User-Agent: Mutt/1.5.24 (2015-08-30) X-RCIS-Action: ALLOW X-TM-AS-Product-Ver: IMSS-7.1.0.1224-8.2.0.1013-23620.005 X-TM-AS-User-Approved-Sender: Yes;Yes X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-Forefront-Antispam-Report: CIP:149.199.60.83; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:xsj-pvapsmtpgw01; PTR:unknown-60-83.xilinx.com; CAT:NONE; SFTY:; SFS:(136003)(396003)(346002)(39860400002)(376002)(46966005)(7416002)(316002)(186003)(42186006)(83380400001)(6636002)(37006003)(30864003)(2906002)(47076004)(336012)(81166007)(70586007)(5660300002)(54906003)(6862004)(33656002)(82740400003)(356005)(8676002)(478600001)(26005)(6266002)(426003)(8936002)(107886003)(44832011)(1076003)(82310400002)(36756003)(70206006)(2616005)(4326008)(42866002)(559001)(579004)(309714004); DIR:OUT; SFP:1101; X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: f62b8fd2-880a-48c5-a165-08d82910d123 X-MS-TrafficTypeDiagnostic: CY4PR02MB2501: X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Oob-TLC-OOBClassifiers: OLM:5236; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: aLpXJiYX88L5FZtAqbieXUqc/wNEDJDx5ipZkjcSGxU3CTQ7FuHc6oUGjkvQAH00F/MgG+kAc5JyM+7jlaMP1wxSr0KiNJhZ4xPQxEfpLg+8WB2HgS3u8ZaMpbeS018lSf7parb7CKXAp7E/Y0lxnSdZdb2x/w9QB63dJNZLBzmj8sz0kG43y09pm8bCAJMR0iKt899mhEV3fctQuFwK8TJMmLzJEqykDifmLkRtRSDw2OTEnHIug3riFTxCuDqQKYY+JZk5Tu/Ot1XIOr3uzJqvKnswmDIUyz1lf/9RoeIosxbu6WxzrYiwdnvvokVtIVAFC4L67M2u6gWy8hf90MkKvvwv6mlCBXs+b7pu9Eeh8JsXHzYlZVSsY7FV8JVlEGCBeazS12gvJDwnoSaF+X+Ly8zWqJ9u8MUMzbOOLFJ/dDtvfdVsepQwAC+W6ORA X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Jul 2020 22:45:47.7764 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f62b8fd2-880a-48c5-a165-08d82910d123 X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c; Ip=[149.199.60.83]; Helo=[xsj-pvapsmtpgw01] X-MS-Exchange-CrossTenant-AuthSource: CY1NAM02FT058.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY4PR02MB2501 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200715_184556_054285_997E698D X-CRM114-Status: GOOD ( 27.81 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "mark.rutland@arm.com" , "devicetree@vger.kernel.org" , Dinesh Kumar , Sandip Kothari , "linux-kernel@vger.kernel.org" , "hverkuil@xs4all.nl" , "robh+dt@kernel.org" , Michal Simek , "laurent.pinchart@ideasonboard.com" , Vishal Sagar , "joe@perches.com" , "mchehab@kernel.org" , "linux-arm-kernel@lists.infradead.org" , "linux-media@vger.kernel.org" Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org SGkgVmlzaGFsLAoKVGhhbmsgeW91IGZvciB0aGUgcGF0Y2guIFNvcnJ5IGZvciBsYXRlIHJlc3Bv bnNlLgoKT24gV2VkLCBKdW4gMTcsIDIwMjAgYXQgMTA6MzM6MDRQTSAtMDcwMCwgVmlzaGFsIFNh Z2FyIHdyb3RlOgo+IFRoZSBYaWxpbnggVUhELVNESSBSeCBzdWJzeXN0ZW0gc29mdCBJUCBpcyB1 c2VkIHRvIGNhcHR1cmUgbmF0aXZlIFNESQo+IHN0cmVhbXMgZnJvbSBTREkgc291cmNlcyBsaWtl IFNESSBicm9hZGNhc3QgZXF1aXBtZW50IGxpa2UgY2FtZXJhcyBhbmQKPiBtaXhlcnMuIFRoaXMg YmxvY2sgb3V0cHV0cyBlaXRoZXIgbmF0aXZlIFNESSwgbmF0aXZlIHZpZGVvIG9yCj4gQVhJNC1T dHJlYW0gY29tcGxpYW50IGRhdGEgc3RyZWFtIGZvciBmdXJ0aGVyIHByb2Nlc3NpbmcuIFBsZWFz ZSByZWZlcgo+IHRvIFBHMjkwIGZvciBkZXRhaWxzLgo+IAo+IFRoZSBkcml2ZXIgaXMgdXNlZCB0 byBjb25maWd1cmUgdGhlIElQIHRvIGFkZCBmcmFtZXIsIHNlYXJjaCBmb3IKPiBzcGVjaWZpYyBt b2RlcywgZ2V0IHRoZSBkZXRlY3RlZCBtb2RlLCBzdHJlYW0gcGFyYW1ldGVycywgZXJyb3JzLCBl dGMuCj4gSXQgYWxzbyBnZW5lcmF0ZXMgZXZlbnRzIGZvciB2aWRlbyBsb2NrL3VubG9jaywgYnJp ZGdlIG92ZXIvdW5kZXIgZmxvdy4KPiAKPiBUaGUgZHJpdmVyIHN1cHBvcnRzIDEwLzEyIGJwYyBZ VVYgNDIyIG1lZGlhIGJ1cyBmb3JtYXQgY3VycmVudGx5LiBJdAo+IGFsc28gZGVjb2RlcyB0aGUg c3RyZWFtIHBhcmFtZXRlcnMgYmFzZWQgb24gdGhlIFNUMzUyIHBhY2tldCBlbWJlZGRlZCBpbiB0 aGUKPiBzdHJlYW0uIEluIGNhc2UgdGhlIFNUMzUyIHBhY2tldCBpc24ndCBwcmVzZW50IGluIHRo ZSBzdHJlYW0sIHRoZSBjb3JlJ3MKPiBkZXRlY3RlZCBwcm9wZXJ0aWVzIGFyZSB1c2VkIHRvIHNl dCBzdHJlYW0gcHJvcGVydGllcy4KPiAKPiBUaGUgZHJpdmVyIGN1cnJlbnRseSBzdXBwb3J0cyBv bmx5IHRoZSBBWEk0LVN0cmVhbSBJUCBjb25maWd1cmF0aW9uLgo+IAo+IFNpZ25lZC1vZmYtYnk6 IFZpc2hhbCBTYWdhciA8dmlzaGFsLnNhZ2FyQHhpbGlueC5jb20+Cj4gLS0tCj4gdjMKPiAtIGZp eGVkIEtDb25maWcgd2l0aCBiZXR0ZXIgZGVzY3JpcHRpb24KPiAtIHJlbW92ZWQgdW5uZWNlc3Nh cnkgaGVhZGVyIGZpbGVzCj4gLSBjb252ZXJ0ZWQgdXBwZXJjYXNlIHRvIGxvd2VyY2FzZSBmb3Ig YWxsIGhleCB2YWx1ZXMKPiAtIG1lcmdlZCBjb3JlIHN0cnVjdCB0byBzdGF0ZSBzdHJ1Y3QKPiAt IHJlbW92ZWQgbW9zdCBvbmUgbGluZSBmdW5jdGlvbnMgYW5kIHJlcGxhY2VkIHdpdGggZGlyZWN0 IHJlZwo+ICAgcmVhZC93cml0ZSBvciBtYWNyb3MKPiAtIGR0IHByb3BlcnR5IGJwcCB0byBicGMu IGRlZmF1bHQgMTAuIG5vdCBtYW5kYXRvcnkuCj4gLSBmaXhlZCBzdWJzY3JpYmUgZXZlbnRzLCBs b2dfc3RhdHVzLCBzX3N0cmVhbQo+IC0gbWVyZ2VkIG92ZXJmbG93L3VuZGVyZmxvdyB0byBvbmUg ZXZlbnQKPiAtIG1vdmVkIGFsbCBjb250cm9scyB0byB4aWxpbngtc2Rpcnhzcy5oCj4gLSBtYXgg ZXZlbnRzIGZyb20gMTI4IHRvIDgKPiAtIHVzZWQgRklFTERfR0VUKCkgaW5zdGVhZCBvZiBjdXN0 b20gbWFjcm8KPiAtIHVwZGF0ZWQgdGhlIGNvbnRyb2xzIGRvY3VtZW50YXRpb24KPiAtIGFkZGVk IHNwaW5sb2NrCj4gLSByZW1vdmVkIDNHQiBjb250cm9sIGFuZCBhZGRlZCBtb2RlIHRvIGRldGVj dCBiaXRtYXNrCj4gLSBmaXhlZCBmb3JtYXQgZm9yICh3aWR0aCwgaGVpZ2h0LCBjb2xvcnNwYWNl LCB4ZmVyIGZ1bmMsIGV0YykKPiAtIGFkZGVkIGR2X3RpbWluZ3NfY2FwLCBzL2dfZHZfdGltaW5n cwo+IC0gZml4ZWQgc2V0L2dldF9mb3JtYXQKPiAtIGZpeCB2NGwgY29udHJvbCByZWdpc3RyYXRp b25zCj4gLSBmaXggb3JkZXIgb2YgcmVnaXN0cmF0aW9uIC8gZGVyZWdpc3RyYXRpb24gaW4gcHJv YmUoKSByZW1vdmUoKQo+IC0gZml4ZWQgb3RoZXIgY29tbWVudHMgZnJvbSBIeXVuLCBMYXVyZW50 IGFuZCBIYW5zCj4gLSB0aGluZ3MgeWV0IHRvIGNsb3NlCj4gICAtIGFkZGluZyBzb3VyY2UgcG9y dCBmb3IgY29ubmVjdG9yIChMYXVyZW50J3Mgc3VnZ2VzdGlvbikKPiAgIC0gYWRkaW5nIG5ldyBG SUVMRCB0eXBlIGZvciBUcmFuc3BvcnQgU3RyZWFtIFY0TDJfRklFTERfQUxURVJOQVRFX1BST0cg KEhhbidzIHN1Z2dlc3Rpb24pCj4gICAtIFVwZGF0ZSAvIHJlbW92ZSBFREggb3IgQ1JDIHJlbGF0 ZWQgY29udHJvbHMKPiAKPiB2Mgo+IC0gQWRkZWQgRFYgdGltaW5nIHN1cHBvcnQgYmFzZWQgb24g SGFucyBWZXJrdWlsxZsgZmVlZGJhY2sKPiAtIE1vcmUgZG9jdW1lbnRhdGlvbiB0byBjdXN0b20g djRsIGNvbnRyb2xzIGFuZCBldmVudHMKPiAtIEZpeGVkIEh5dW7FmyBjb21tZW50cwo+IC0gQWRk ZWQgbWFjcm8gZm9yIG1hc2tpbmcgYW5kIHNoaWZ0aW5nIGFzIHBlciBKb2UgUGVyY2hlcyBjb21t ZW50cwo+IC0gVXBkYXRlZCB0byBsYXRlc3QgYXMgcGVyIFhpbGlueCBnaXRodWIgcmVwbyBkcml2 ZXIgbGlrZQo+ICAgYWRkaW5nIG5ldyBEViB0aW1pbmdzIG5vdCBpbiBtYWlubGluZSB5ZXQgdXB0 aWxsIDAzLzIxLzIwCj4gCj4gIGRyaXZlcnMvbWVkaWEvcGxhdGZvcm0veGlsaW54L0tjb25maWcg ICAgICAgICB8ICAgMTEgKwo+ICBkcml2ZXJzL21lZGlhL3BsYXRmb3JtL3hpbGlueC9NYWtlZmls ZSAgICAgICAgfCAgICAxICsKPiAgLi4uL21lZGlhL3BsYXRmb3JtL3hpbGlueC94aWxpbngtc2Rp cnhzcy5jICAgIHwgMjEyMSArKysrKysrKysrKysrKysrKwo+ICBpbmNsdWRlL3VhcGkvbGludXgv djRsMi1jb250cm9scy5oICAgICAgICAgICAgfCAgICA2ICsKPiAgaW5jbHVkZS91YXBpL2xpbnV4 L3hpbGlueC1zZGlyeHNzLmggICAgICAgICAgIHwgIDI4MyArKysKPiAgNSBmaWxlcyBjaGFuZ2Vk LCAyNDIyIGluc2VydGlvbnMoKykKPiAgY3JlYXRlIG1vZGUgMTAwNjQ0IGRyaXZlcnMvbWVkaWEv cGxhdGZvcm0veGlsaW54L3hpbGlueC1zZGlyeHNzLmMKPiAgY3JlYXRlIG1vZGUgMTAwNjQ0IGlu Y2x1ZGUvdWFwaS9saW51eC94aWxpbngtc2Rpcnhzcy5oCj4gCj4gZGlmZiAtLWdpdCBhL2RyaXZl cnMvbWVkaWEvcGxhdGZvcm0veGlsaW54L0tjb25maWcgYi9kcml2ZXJzL21lZGlhL3BsYXRmb3Jt L3hpbGlueC9LY29uZmlnCj4gaW5kZXggMDFjOTZmYjY2NDE0Li41NzhjZGNjMTAzNmUgMTAwNjQ0 Cj4gLS0tIGEvZHJpdmVycy9tZWRpYS9wbGF0Zm9ybS94aWxpbngvS2NvbmZpZwo+ICsrKyBiL2Ry aXZlcnMvbWVkaWEvcGxhdGZvcm0veGlsaW54L0tjb25maWcKPiBAQCAtMTIsNiArMTIsMTcgQEAg Y29uZmlnIFZJREVPX1hJTElOWAo+ICAKPiAgaWYgVklERU9fWElMSU5YCj4gIAo+ICtjb25maWcg VklERU9fWElMSU5YX1NESVJYU1MKPiArCXRyaXN0YXRlICJYaWxpbnggVUhEIFNESSBSeCBTdWJz eXN0ZW0iCj4gKwloZWxwCj4gKwkgIERyaXZlciBmb3IgWGlsaW54IFVIRC1TREkgUnggU3Vic3lz dGVtLiBUaGlzIGlzIGEgVjRMIHN1Yi1kZXZpY2UKPiArCSAgYmFzZWQgZHJpdmVyIHRoYXQgdGFr ZXMgaW5wdXQgZnJvbSBhIFNESSBzb3VyY2UgbGlrZSBTREkgY2FtZXJhIGFuZAo+ICsJICBjb252 ZXJ0cyBpdCBpbnRvIGFuIEFYSTQtU3RyZWFtLiBUaGUgc3Vic3lzdGVtIGNvbXByaXNlcyBhIFNN UFRFCj4gKwkgIFVIRC1TREkgUnggY29yZSwgYSBTREkgUnggdG8gTmF0aXZlIFZpZGVvIGJyaWRn ZSBhbmQgYSBWaWRlbyBJbiB0bwo+ICsJICBBWEk0LVN0cmVhbSBicmlkZ2UuIFRoZSBkcml2ZXIg aXMgdXNlZCB0byBzZXQgZGlmZmVyZW50IHN0cmVhbQo+ICsJICBkZXRlY3Rpb24gbW9kZXMgYW5k IGlkZW50aWZ5IHN0cmVhbSBwcm9wZXJ0aWVzIHRvIHByb3Blcmx5IGNvbmZpZ3VyZQo+ICsJICBk b3duc3RyZWFtLgo+ICsKPiAgY29uZmlnIFZJREVPX1hJTElOWF9UUEcKPiAgCXRyaXN0YXRlICJY aWxpbnggVmlkZW8gVGVzdCBQYXR0ZXJuIEdlbmVyYXRvciIKPiAgCWRlcGVuZHMgb24gVklERU9f WElMSU5YCj4gZGlmZiAtLWdpdCBhL2RyaXZlcnMvbWVkaWEvcGxhdGZvcm0veGlsaW54L01ha2Vm aWxlIGIvZHJpdmVycy9tZWRpYS9wbGF0Zm9ybS94aWxpbngvTWFrZWZpbGUKPiBpbmRleCA0Y2Rj MGIxZWM3YTUuLjNiZWFmMjRkODMyYyAxMDA2NDQKPiAtLS0gYS9kcml2ZXJzL21lZGlhL3BsYXRm b3JtL3hpbGlueC9NYWtlZmlsZQo+ICsrKyBiL2RyaXZlcnMvbWVkaWEvcGxhdGZvcm0veGlsaW54 L01ha2VmaWxlCj4gQEAgLTMsNSArMyw2IEBACj4gIHhpbGlueC12aWRlby1vYmpzICs9IHhpbGlu eC1kbWEubyB4aWxpbngtdmlwLm8geGlsaW54LXZpcHAubwo+ICAKPiAgb2JqLSQoQ09ORklHX1ZJ REVPX1hJTElOWCkgKz0geGlsaW54LXZpZGVvLm8KPiArb2JqLSQoQ09ORklHX1ZJREVPX1hJTElO WF9TRElSWFNTKSArPSB4aWxpbngtc2Rpcnhzcy5vCj4gIG9iai0kKENPTkZJR19WSURFT19YSUxJ TlhfVFBHKSArPSB4aWxpbngtdHBnLm8KPiAgb2JqLSQoQ09ORklHX1ZJREVPX1hJTElOWF9WVEMp ICs9IHhpbGlueC12dGMubwo+IGRpZmYgLS1naXQgYS9kcml2ZXJzL21lZGlhL3BsYXRmb3JtL3hp bGlueC94aWxpbngtc2Rpcnhzcy5jIGIvZHJpdmVycy9tZWRpYS9wbGF0Zm9ybS94aWxpbngveGls aW54LXNkaXJ4c3MuYwo+IG5ldyBmaWxlIG1vZGUgMTAwNjQ0Cj4gaW5kZXggMDAwMDAwMDAwMDAw Li5lMzlhYWI3YzY1NmEKPiAtLS0gL2Rldi9udWxsCj4gKysrIGIvZHJpdmVycy9tZWRpYS9wbGF0 Zm9ybS94aWxpbngveGlsaW54LXNkaXJ4c3MuYwo+IEBAIC0wLDAgKzEsMjEyMSBAQAo+ICsvLyBT UERYLUxpY2Vuc2UtSWRlbnRpZmllcjogR1BMLTIuMAo+ICsvKgo+ICsgKiBEcml2ZXIgZm9yIFhp bGlueCBTREkgUnggU3Vic3lzdGVtCj4gKyAqCj4gKyAqIENvcHlyaWdodCAoQykgMjAxNyAtIDIw MjAgWGlsaW54LCBJbmMuCj4gKyAqCj4gKyAqIENvbnRhY3RzOiBWaXNoYWwgU2FnYXIgPHZpc2hh bC5zYWdhckB4aWxpbnguY29tPgo+ICsgKi8KPiArCj4gKyNpbmNsdWRlIDxkdC1iaW5kaW5ncy9t ZWRpYS94aWxpbngtc2RpLmg+Cj4gKyNpbmNsdWRlIDxsaW51eC9iaXRzLmg+Cj4gKyNpbmNsdWRl IDxsaW51eC9iaXRmaWVsZC5oPgo+ICsjaW5jbHVkZSA8bGludXgvY2xrLmg+Cj4gKyNpbmNsdWRl IDxsaW51eC9tb2R1bGUuaD4KPiArI2luY2x1ZGUgPGxpbnV4L3BsYXRmb3JtX2RldmljZS5oPgo+ ICsjaW5jbHVkZSA8bGludXgveGlsaW54LXNkaXJ4c3MuaD4KPiArI2luY2x1ZGUgPG1lZGlhL21l ZGlhLWVudGl0eS5oPgo+ICsjaW5jbHVkZSA8bWVkaWEvdjRsMi1jdHJscy5oPgo+ICsjaW5jbHVk ZSA8bWVkaWEvdjRsMi1kdi10aW1pbmdzLmg+Cj4gKyNpbmNsdWRlIDxtZWRpYS92NGwyLWV2ZW50 Lmg+Cj4gKyNpbmNsdWRlIDxtZWRpYS92NGwyLXN1YmRldi5oPgo+ICsKPiArLyoKPiArICogU0RJ IFJ4IHJlZ2lzdGVyIG1hcCwgYml0bWFzayBhbmQgb2Zmc2V0cwo+ICsgKi8KPiArI2RlZmluZSBY U0RJUlhfUlNUX0NUUkxfUkVHCQkweDAwCj4gKyNkZWZpbmUgWFNESVJYX01ETF9DVFJMX1JFRwkJ MHgwNAo+ICsjZGVmaW5lIFhTRElSWF9HTEJMX0lFUl9SRUcJCTB4MGMKPiArI2RlZmluZSBYU0RJ UlhfSVNSX1JFRwkJCTB4MTAKPiArI2RlZmluZSBYU0RJUlhfSUVSX1JFRwkJCTB4MTQKPiArI2Rl ZmluZSBYU0RJUlhfU1QzNTJfVkFMSURfUkVHCQkweDE4Cj4gKyNkZWZpbmUgWFNESVJYX1NUMzUy X0RTMV9SRUcJCTB4MWMKPiArI2RlZmluZSBYU0RJUlhfU1QzNTJfRFMzX1JFRwkJMHgyMAo+ICsj ZGVmaW5lIFhTRElSWF9TVDM1Ml9EUzVfUkVHCQkweDI0Cj4gKyNkZWZpbmUgWFNESVJYX1NUMzUy X0RTN19SRUcJCTB4MjgKPiArI2RlZmluZSBYU0RJUlhfU1QzNTJfRFM5X1JFRwkJMHgyYwo+ICsj ZGVmaW5lIFhTRElSWF9TVDM1Ml9EUzExX1JFRwkJMHgzMAo+ICsjZGVmaW5lIFhTRElSWF9TVDM1 Ml9EUzEzX1JFRwkJMHgzNAo+ICsjZGVmaW5lIFhTRElSWF9TVDM1Ml9EUzE1X1JFRwkJMHgzOAo+ ICsjZGVmaW5lIFhTRElSWF9WRVJTSU9OX1JFRwkJMHgzYwo+ICsjZGVmaW5lIFhTRElSWF9TU19D T05GSUdfUkVHCQkweDQwCj4gKyNkZWZpbmUgWFNESVJYX01PREVfREVUX1NUQVRfUkVHCTB4NDQK PiArI2RlZmluZSBYU0RJUlhfVFNfREVUX1NUQVRfUkVHCQkweDQ4Cj4gKyNkZWZpbmUgWFNESVJY X0VESF9TVEFUX1JFRwkJMHg0Ywo+ICsjZGVmaW5lIFhTRElSWF9FREhfRVJSQ05UX0VOX1JFRwkw eDUwCj4gKyNkZWZpbmUgWFNESVJYX0VESF9FUlJDTlRfUkVHCQkweDU0Cj4gKyNkZWZpbmUgWFNE SVJYX0NSQ19FUlJDTlRfUkVHCQkweDU4Cj4gKyNkZWZpbmUgWFNESVJYX1ZJRF9MT0NLX1dJTkRP V19SRUcJMHg1Ywo+ICsjZGVmaW5lIFhTRElSWF9TVDM1Ml9EUzJfUkVHCQkweDcwCj4gKyNkZWZp bmUgWFNESVJYX1NUMzUyX0RTNF9SRUcJCTB4NzQKPiArI2RlZmluZSBYU0RJUlhfU1QzNTJfRFM2 X1JFRwkJMHg3OAo+ICsjZGVmaW5lIFhTRElSWF9TVDM1Ml9EUzhfUkVHCQkweDdjCj4gKyNkZWZp bmUgWFNESVJYX1NUMzUyX0RTMTBfUkVHCQkweDgwCj4gKyNkZWZpbmUgWFNESVJYX1NUMzUyX0RT MTJfUkVHCQkweDg0Cj4gKyNkZWZpbmUgWFNESVJYX1NUMzUyX0RTMTRfUkVHCQkweDg4Cj4gKyNk ZWZpbmUgWFNESVJYX1NUMzUyX0RTMTZfUkVHCQkweDhjCj4gKwo+ICsjZGVmaW5lIFhTRElSWF9S U1RfQ1RSTF9TU19FTl9NQVNLCQkJQklUKDApCj4gKyNkZWZpbmUgWFNESVJYX1JTVF9DVFJMX1NS U1RfTUFTSwkJCUJJVCgxKQo+ICsjZGVmaW5lIFhTRElSWF9SU1RfQ1RSTF9SU1RfQ1JDX0VSUkNO VF9NQVNLCQlCSVQoMikKPiArI2RlZmluZSBYU0RJUlhfUlNUX0NUUkxfUlNUX0VESF9FUlJDTlRf TUFTSwkJQklUKDMpCj4gKyNkZWZpbmUgWFNESVJYX1JTVF9DVFJMX1NESVJYX0JSSURHRV9FTkJf TUFTSwkJQklUKDgpCj4gKyNkZWZpbmUgWFNESVJYX1JTVF9DVFJMX1ZJRElOX0FYSTRTX01PRF9F TkJfTUFTSwlCSVQoOSkKPiArI2RlZmluZSBYU0RJUlhfUlNUX0NUUkxfQlJJREdFX0NIX0ZNVF9P RkZTRVQJCTEwCj4gKyNkZWZpbmUgWFNESVJYX1JTVF9DVFJMX0JSSURHRV9DSF9GTVRfTUFTSwkJ R0VOTUFTSygxMiwgMTApCj4gKyNkZWZpbmUgWFNESVJYX1JTVF9DVFJMX0JSSURHRV9DSF9GTVRf WVVWNDQ0CQkxCj4gKwo+ICsjZGVmaW5lIFhTRElSWF9NRExfQ1RSTF9GUk1fRU5fTUFTSwkJQklU KDQpCj4gKyNkZWZpbmUgWFNESVJYX01ETF9DVFJMX01PREVfREVUX0VOX01BU0sJQklUKDUpCj4g KyNkZWZpbmUgWFNESVJYX01ETF9DVFJMX01PREVfSERfRU5fTUFTSwkJQklUKDgpCj4gKyNkZWZp bmUgWFNESVJYX01ETF9DVFJMX01PREVfU0RfRU5fTUFTSwkJQklUKDkpCj4gKyNkZWZpbmUgWFNE SVJYX01ETF9DVFJMX01PREVfM0dfRU5fTUFTSwkJQklUKDEwKQo+ICsjZGVmaW5lIFhTRElSWF9N RExfQ1RSTF9NT0RFXzZHX0VOX01BU0sJCUJJVCgxMSkKPiArI2RlZmluZSBYU0RJUlhfTURMX0NU UkxfTU9ERV8xMkdJX0VOX01BU0sJQklUKDEyKQo+ICsjZGVmaW5lIFhTRElSWF9NRExfQ1RSTF9N T0RFXzEyR0ZfRU5fTUFTSwlCSVQoMTMpCj4gKyNkZWZpbmUgWFNESVJYX01ETF9DVFJMX01PREVf QVVUT19ERVRfTUFTSwlHRU5NQVNLKDEzLCA4KQo+ICsKPiArI2RlZmluZSBYU0RJUlhfTURMX0NU UkxfRk9SQ0VEX01PREVfT0ZGU0VUCTE2Cj4gKyNkZWZpbmUgWFNESVJYX01ETF9DVFJMX0ZPUkNF RF9NT0RFX01BU0sJR0VOTUFTSygxOCwgMTYpCj4gKwo+ICsjZGVmaW5lIFhTRElSWF9HTEJMX0lO VFJfRU5fTUFTSwlCSVQoMCkKPiArCj4gKyNkZWZpbmUgWFNESVJYX0lOVFJfVklETE9DS19NQVNL CUJJVCgwKQo+ICsjZGVmaW5lIFhTRElSWF9JTlRSX1ZJRFVOTE9DS19NQVNLCUJJVCgxKQo+ICsj ZGVmaW5lIFhTRElSWF9JTlRSX09WRVJGTE9XX01BU0sJQklUKDkpCj4gKyNkZWZpbmUgWFNESVJY X0lOVFJfVU5ERVJGTE9XX01BU0sJQklUKDEwKQo+ICsKPiArI2RlZmluZSBYU0RJUlhfSU5UUl9B TExfTUFTSwkoWFNESVJYX0lOVFJfVklETE9DS19NQVNLIHxcCj4gKwkJCQlYU0RJUlhfSU5UUl9W SURVTkxPQ0tfTUFTSyB8XAo+ICsJCQkJWFNESVJYX0lOVFJfT1ZFUkZMT1dfTUFTSyB8XAo+ICsJ CQkJWFNESVJYX0lOVFJfVU5ERVJGTE9XX01BU0spCj4gKwo+ICsjZGVmaW5lIFhTRElSWF9TVDM1 Ml9WQUxJRF9EUzFfTUFTSwlCSVQoMCkKPiArI2RlZmluZSBYU0RJUlhfU1QzNTJfVkFMSURfRFMz X01BU0sJQklUKDEpCj4gKyNkZWZpbmUgWFNESVJYX1NUMzUyX1ZBTElEX0RTNV9NQVNLCUJJVCgy KQo+ICsjZGVmaW5lIFhTRElSWF9TVDM1Ml9WQUxJRF9EUzdfTUFTSwlCSVQoMykKPiArI2RlZmlu ZSBYU0RJUlhfU1QzNTJfVkFMSURfRFM5X01BU0sJQklUKDQpCj4gKyNkZWZpbmUgWFNESVJYX1NU MzUyX1ZBTElEX0RTMTFfTUFTSwlCSVQoNSkKPiArI2RlZmluZSBYU0RJUlhfU1QzNTJfVkFMSURf RFMxM19NQVNLCUJJVCg2KQo+ICsjZGVmaW5lIFhTRElSWF9TVDM1Ml9WQUxJRF9EUzE1X01BU0sJ QklUKDcpCj4gKwo+ICsjZGVmaW5lIFhTRElSWF9NT0RFX0RFVF9TVEFUX1JYX01PREVfTUFTSwlH RU5NQVNLKDIsIDApCj4gKyNkZWZpbmUgWFNESVJYX01PREVfREVUX1NUQVRfTU9ERV9MT0NLX01B U0sJQklUKDMpCj4gKyNkZWZpbmUgWFNESVJYX01PREVfREVUX1NUQVRfQUNUX1NUUkVBTV9NQVNL CUdFTk1BU0soNiwgNCkKPiArI2RlZmluZSBYU0RJUlhfTU9ERV9ERVRfU1RBVF9BQ1RfU1RSRUFN X09GRlNFVAk0Cj4gKyNkZWZpbmUgWFNESVJYX01PREVfREVUX1NUQVRfTFZMQl8zR19NQVNLCUJJ VCg3KQo+ICsKPiArI2RlZmluZSBYU0RJUlhfVFNfREVUX1NUQVRfTE9DS0VEX01BU0sJCUJJVCgw KQo+ICsjZGVmaW5lIFhTRElSWF9UU19ERVRfU1RBVF9TQ0FOX01BU0sJCUJJVCgxKQo+ICsjZGVm aW5lIFhTRElSWF9UU19ERVRfU1RBVF9GQU1JTFlfTUFTSwkJR0VOTUFTSyg3LCA0KQo+ICsjZGVm aW5lIFhTRElSWF9UU19ERVRfU1RBVF9SQVRFX01BU0sJCUdFTk1BU0soMTEsIDgpCj4gKwo+ICsj ZGVmaW5lIFhTRElSWF9UU19ERVRfU1RBVF9SQVRFX05PTkUJCTB4MAo+ICsjZGVmaW5lIFhTRElS WF9UU19ERVRfU1RBVF9SQVRFXzIzXzk4SFoJCTB4Mgo+ICsjZGVmaW5lIFhTRElSWF9UU19ERVRf U1RBVF9SQVRFXzI0SFoJCTB4Mwo+ICsjZGVmaW5lIFhTRElSWF9UU19ERVRfU1RBVF9SQVRFXzQ3 Xzk1SFoJCTB4NAo+ICsjZGVmaW5lIFhTRElSWF9UU19ERVRfU1RBVF9SQVRFXzI1SFoJCTB4NQo+ ICsjZGVmaW5lIFhTRElSWF9UU19ERVRfU1RBVF9SQVRFXzI5Xzk3SFoJCTB4Ngo+ICsjZGVmaW5l IFhTRElSWF9UU19ERVRfU1RBVF9SQVRFXzMwSFoJCTB4Nwo+ICsjZGVmaW5lIFhTRElSWF9UU19E RVRfU1RBVF9SQVRFXzQ4SFoJCTB4OAo+ICsjZGVmaW5lIFhTRElSWF9UU19ERVRfU1RBVF9SQVRF XzUwSFoJCTB4OQo+ICsjZGVmaW5lIFhTRElSWF9UU19ERVRfU1RBVF9SQVRFXzU5Xzk0SFoJCTB4 YQo+ICsjZGVmaW5lIFhTRElSWF9UU19ERVRfU1RBVF9SQVRFXzYwSFoJCTB4Ygo+ICsKPiArI2Rl ZmluZSBYU0RJUlhfRURIX1NUQVRfRURIX0FQX01BU0sJQklUKDApCj4gKyNkZWZpbmUgWFNESVJY X0VESF9TVEFUX0VESF9GRl9NQVNLCUJJVCgxKQo+ICsjZGVmaW5lIFhTRElSWF9FREhfU1RBVF9F REhfQU5DX01BU0sJQklUKDIpCj4gKyNkZWZpbmUgWFNESVJYX0VESF9TVEFUX0FQX0ZMQUdfTUFT SwlHRU5NQVNLKDgsIDQpCj4gKyNkZWZpbmUgWFNESVJYX0VESF9TVEFUX0ZGX0ZMQUdfTUFTSwlH RU5NQVNLKDEzLCA5KQo+ICsjZGVmaW5lIFhTRElSWF9FREhfU1RBVF9BTkNfRkxBR19NQVNLCUdF Tk1BU0soMTgsIDE0KQo+ICsjZGVmaW5lIFhTRElSWF9FREhfU1RBVF9QS1RfRkxBR19NQVNLCUdF Tk1BU0soMjIsIDE5KQo+ICsKPiArI2RlZmluZSBYU0RJUlhfRURIX0VSUkNOVF9DT1VOVF9NQVNL CUdFTk1BU0soMTUsIDApCj4gKwo+ICsjZGVmaW5lIFhTRElSWF9DUkNfRVJSQ05UX0NPVU5UX01B U0sJR0VOTUFTSygzMSwgMTYpCj4gKyNkZWZpbmUgWFNESVJYX0NSQ19FUlJDTlRfRFNfQ1JDX01B U0sJR0VOTUFTSygxNSwgMCkKPiArCj4gKyNkZWZpbmUgWFNESVJYX1ZFUlNJT05fUkVWX01BU0sJ CUdFTk1BU0soNywgMCkKPiArI2RlZmluZSBYU0RJUlhfVkVSU0lPTl9QQVRDSElEX01BU0sJR0VO TUFTSygxMSwgOCkKPiArI2RlZmluZSBYU0RJUlhfVkVSU0lPTl9WRVJfUkVWX01BU0sJR0VOTUFT SygxNSwgMTIpCj4gKyNkZWZpbmUgWFNESVJYX1ZFUlNJT05fVkVSX01JTl9NQVNLCUdFTk1BU0so MjMsIDE2KQo+ICsjZGVmaW5lIFhTRElSWF9WRVJTSU9OX1ZFUl9NQUpfTUFTSwlHRU5NQVNLKDMx LCAyNCkKPiArCj4gKyNkZWZpbmUgWFNESVJYX1NTX0NPTkZJR19FREhfSU5DTFVERURfTUFTSwkJ QklUKDEpCj4gKwo+ICsjZGVmaW5lIFhTRElSWF9TVEFUX1NCX1JYX1REQVRBX0NIQU5HRV9ET05F X01BU0sJQklUKDApCj4gKyNkZWZpbmUgWFNESVJYX1NUQVRfU0JfUlhfVERBVEFfQ0hBTkdFX0ZB SUxfTUFTSwlCSVQoMSkKPiArI2RlZmluZSBYU0RJUlhfU1RBVF9TQl9SWF9UREFUQV9HVF9SRVNF VERPTkVfTUFTSwlCSVQoMikKPiArI2RlZmluZSBYU0RJUlhfU1RBVF9TQl9SWF9UREFUQV9HVF9C SVRSQVRFX01BU0sJCUJJVCgzKQo+ICsKPiArI2RlZmluZSBYU0RJUlhfREVGQVVMVF9XSURUSAkx OTIwCj4gKyNkZWZpbmUgWFNESVJYX0RFRkFVTFRfSEVJR0hUCTEwODAKPiArCj4gKyNkZWZpbmUg WFNESVJYX01BWF9TVFJfTEVOR1RICTE2CgpUaGlzIGlzIG5vdCB1c2VkLiBQbGVhc2UgcmVtb3Zl LgoKPiArCj4gKyNkZWZpbmUgWFNESVJYX0RFRkFVTFRfVklERU9fTE9DS19XSU5ET1cJMHgzMDAw CgpOb3Qgc3VyZSBpZiB0aGlzIG1hY3JvIGlzIG5lZWRlZC4gVGhlIHZhbHVlIGNhbiBiZSB1c2Vk IGRpcmVjdGx5LiBTaW5nbGUKdXNlciBtYWNybyB3aXRob3V0IGFkZGl0aW9uYWwgZGVzY3JpcHRp b24gbWF5IGJlIHJlbW92ZWQuIFBsZWFzZSBjaGVjay4KCj4gKwo+ICsjZGVmaW5lIFhTRElSWF9N T0RFX0hEX01BU0sJMHgwCj4gKyNkZWZpbmUgWFNESVJYX01PREVfU0RfTUFTSwkweDEKPiArI2Rl ZmluZSBYU0RJUlhfTU9ERV8zR19NQVNLCTB4Mgo+ICsjZGVmaW5lIFhTRElSWF9NT0RFXzZHX01B U0sJMHg0Cj4gKyNkZWZpbmUgWFNESVJYX01PREVfMTJHSV9NQVNLCTB4NQo+ICsjZGVmaW5lIFhT RElSWF9NT0RFXzEyR0ZfTUFTSwkweDYKClRoZXNlIGFyZSBub3QgbWFza3MsIHNvIF9NQVNLIGJl dHRlciBiZSByZW1vdmVkIGZyb20gbmFtZXMuCgo+ICsKPiArLyogTWF4aW11bSBudW1iZXIgb2Yg ZXZlbnRzIHBlciBmaWxlIGhhbmRsZS4gKi8KPiArI2RlZmluZSBYU0RJUlhfTUFYX0VWRU5UUwk4 Cj4gKwo+ICsvKiBTVDM1MiByZWxhdGVkIG1hY3JvcyAqLwo+ICsjZGVmaW5lIFhTVDM1Ml9QQVlM T0FEX0JZVEUxX01BU0sJR0VOTUFTSyg3LCAwKQo+ICsjZGVmaW5lIFhTVDM1Ml9QQVlMT0FEX0JZ VEUyX09GRlNFVAk4Cj4gKyNkZWZpbmUgWFNUMzUyX1BBWUxPQURfQllURTNfT0ZGU0VUCTE2Cj4g KyNkZWZpbmUgWFNUMzUyX1BBWUxPQURfQllURTRfT0ZGU0VUCTI0CgpMYXN0IDMgYXJlIG5vdCB1 c2VkLiBUaG9zZSBtYXkgaGF2ZSBiZWNvbWUgdW51c2VkIGZyb20gdXNpbmcgRklFTERfR0VUKCku ClBsZWFzZSByZW1vdmUuCgo+ICsKPiArI2RlZmluZSBYU1QzNTJfQllURTFfU1QyOTJfMXg3MjBM XzFfNUcJCTB4ODQKPiArI2RlZmluZSBYU1QzNTJfQllURTFfU1QyOTJfMXgxMDgwTF8xXzVHCQkw eDg1Cj4gKyNkZWZpbmUgWFNUMzUyX0JZVEUxX1NUNDI1XzIwMDhfNzUwTF8zR0IJMHg4OAo+ICsj ZGVmaW5lIFhTVDM1Ml9CWVRFMV9TVDQyNV8yMDA4XzExMjVMXzNHQQkweDg5Cj4gKyNkZWZpbmUg WFNUMzUyX0JZVEUxX1NUMzcyX0RMXzNHQgkJMHg4YQo+ICsjZGVmaW5lIFhTVDM1Ml9CWVRFMV9T VDM3Ml8yeDcyMExfM0dCCQkweDhiCj4gKyNkZWZpbmUgWFNUMzUyX0JZVEUxX1NUMzcyXzJ4MTA4 MExfM0dCCQkweDhjCj4gKyNkZWZpbmUgWFNUMzUyX0JZVEUxX1NUMjA4MV8xMF8yMTYwTF82RwkJ MHhjMAo+ICsjZGVmaW5lIFhTVDM1Ml9CWVRFMV9TVDIwODFfMTBfMl8xMDgwTF82RwkweGMxCj4g KyNkZWZpbmUgWFNUMzUyX0JZVEUxX1NUMjA4MV8xMF9ETF8yMTYwTF82RwkweGMyCj4gKyNkZWZp bmUgWFNUMzUyX0JZVEUxX1NUMjA4Ml8xMF8yMTYwTF8xMkcJMHhjZQo+ICsKPiArI2RlZmluZSBY U1QzNTJfQllURTJfVFNfVFlQRV9NQVNLCQlCSVQoMTUpCj4gKyNkZWZpbmUgWFNUMzUyX0JZVEUy X1BJQ19UWVBFX01BU0sJCUJJVCgxNCkKPiArI2RlZmluZSBYU1QzNTJfQllURTJfVFNfUElDX1RZ UEVfSU5URVJMQUNFRAkwCj4gKyNkZWZpbmUgWFNUMzUyX0JZVEUyX1RTX1BJQ19UWVBFX1BST0dS RVNTSVZFCTEKCk5vdCB1c2VkLiA6KSBQbGVhc2UgY2hlY2sgYW5kIHJlbW92ZSB1bm5lZWRlZCBk ZWZpbml0aW9ucy4KCj4gKwo+ICsjZGVmaW5lIFhTVDM1Ml9CWVRFMl9GUFNfTUFTSwkJCUdFTk1B U0soMTEsIDgpCj4gKyNkZWZpbmUgWFNUMzUyX0JZVEUyX0ZQU18yNEYJCQkweDIKPiArI2RlZmlu ZSBYU1QzNTJfQllURTJfRlBTXzI0CQkJMHgzCj4gKyNkZWZpbmUgWFNUMzUyX0JZVEUyX0ZQU180 OEYJCQkweDQKPiArI2RlZmluZSBYU1QzNTJfQllURTJfRlBTXzI1CQkJMHg1Cj4gKyNkZWZpbmUg WFNUMzUyX0JZVEUyX0ZQU18zMEYJCQkweDYKPiArI2RlZmluZSBYU1QzNTJfQllURTJfRlBTXzMw CQkJMHg3Cj4gKyNkZWZpbmUgWFNUMzUyX0JZVEUyX0ZQU180OAkJCTB4OAo+ICsjZGVmaW5lIFhT VDM1Ml9CWVRFMl9GUFNfNTAJCQkweDkKPiArI2RlZmluZSBYU1QzNTJfQllURTJfRlBTXzYwRgkJ CTB4YQo+ICsjZGVmaW5lIFhTVDM1Ml9CWVRFMl9GUFNfNjAJCQkweGIKPiArLyogVGFibGUgNCBT VCAyMDgxLTEwOjIwMTUgKi8KPiArI2RlZmluZSBYU1QzNTJfQllURTJfRlBTXzk2CQkJMHhjCj4g KyNkZWZpbmUgWFNUMzUyX0JZVEUyX0ZQU18xMDAJCQkweGQKPiArI2RlZmluZSBYU1QzNTJfQllU RTJfRlBTXzEyMAkJCTB4ZQo+ICsjZGVmaW5lIFhTVDM1Ml9CWVRFMl9GUFNfMTIwRgkJCTB4Zgo+ ICsKPiArI2RlZmluZSBYU1QzNTJfQllURTNfQUNUX0xVTUFfQ09VTlRfTUFTSwlCSVQoMjIpCj4g Kwo+ICsjZGVmaW5lIFhTVDM1Ml9CWVRFM19DT0xPUl9GT1JNQVRfTUFTSwkJR0VOTUFTSygxOSwg MTYpCj4gKyNkZWZpbmUgWFNUMzUyX0JZVEUzX0NPTE9SX0ZPUk1BVF80MjIJCTB4MAo+ICsjZGVm aW5lIFhTVDM1Ml9CWVRFM19DT0xPUl9GT1JNQVRfWVVWNDQ0CTB4MQo+ICsjZGVmaW5lIFhTVDM1 Ml9CWVRFM19DT0xPUl9GT1JNQVRfNDIwCQkweDMKPiArI2RlZmluZSBYU1QzNTJfQllURTNfQ09M T1JfRk9STUFUX0dCUgkJMHgyCj4gKwo+ICsjZGVmaW5lIFhTVDM1Ml9CWVRFM19DT0xPUklNRVRS WV9NQVNLCQlHRU5NQVNLKDIxLCAyMCkKPiArI2RlZmluZSBYU1QzNTJfQllURTNfQ09MT1JJTUVU UllfQlQ3MDkJCTAKPiArI2RlZmluZSBYU1QzNTJfQllURTNfQ09MT1JJTUVUUllfQ09MT1JfVkFO QwkxCj4gKyNkZWZpbmUgWFNUMzUyX0JZVEUzX0NPTE9SSU1FVFJZX1VIRFRWCQkyCj4gKyNkZWZp bmUgWFNUMzUyX0JZVEUzX0NPTE9SSU1FVFJZX1VOS05PV04JMwo+ICsKPiArI2RlZmluZSBYU1Qz NTJfQllURTRfQklUX0RFUFRIX01BU0sJCUdFTk1BU0soMjUsIDI0KQo+ICsjZGVmaW5lIFhTVDM1 Ml9CWVRFNF9CSVRfREVQVEhfMTAJCTB4MQo+ICsjZGVmaW5lIFhTVDM1Ml9CWVRFNF9CSVRfREVQ VEhfMTIJCTB4Mgo+ICsKPiArLyogR1QgaW5wdXQgY2xvY2sgZm9yIHNkaV9yeF9jbGsgKi8KPiAr I2RlZmluZSBDTEtfSU5UCQkxNDg1MDAwMDBVTAo+ICsKPiArI2RlZmluZSBYU0RJUlhTU19XSURU SF9NSU4gICAgICAgICAgICAgICAgICAgIDcyMAo+ICsjZGVmaW5lIFhTRElSWFNTX1dJRFRIX01B WCAgICAgICAgICAgICAgICAgICAgNDA5Ngo+ICsjZGVmaW5lIFhTRElSWFNTX0hFSUdIVF9NSU4g ICAgICAgICAgICAgICAgICAgMjQzCj4gKyNkZWZpbmUgWFNESVJYU1NfSEVJR0hUX01BWCAgICAg ICAgICAgICAgICAgICAyMTYwCj4gKyNkZWZpbmUgWFNESVJYU1NfUElYRUxDTE9DS19NSU4gICAg ICAgICAgICAgICAxMzUwMDAwMAo+ICsjZGVmaW5lIFhTRElSWFNTX1BJWEVMQ0xPQ0tfTUFYICAg ICAgICAgICAgICAgNTk0MDAwMDAwCj4gKwo+ICsvKioKPiArICogZW51bSBzZGlfZmFtaWx5X2Vu YyAtIFNESSBUcmFuc3BvcnQgVmlkZW8gRm9ybWF0IERldGVjdGVkIHdpdGggQWN0aXZlIFBpeGVs cwo+ICsgKiBAWFNESVJYX1NNUFRFX1NUXzI3NDogU01QVEUgU1QgMjc0IGRldGVjdGVkIHdpdGgg QVAgMTkyMHgxMDgwCj4gKyAqIEBYU0RJUlhfU01QVEVfU1RfMjk2OiBTTVBURSBTVCAyOTYgZGV0 ZWN0ZWQgd2l0aCBBUCAxMjgweDcyMAo+ICsgKiBAWFNESVJYX1NNUFRFX1NUXzIwNDhfMjogU01Q VEUgU1QgMjA0OC0yIGRldGVjdGVkIHdpdGggQVAgMjA0OHgxMDgwCj4gKyAqIEBYU0RJUlhfU01Q VEVfU1RfMjk1OiBTTVBURSBTVCAyOTUgZGV0ZWN0ZWQgd2l0aCBBUCAxOTIweDEwODAKPiArICog QFhTRElSWF9OVFNDOiBOVFNDIGVuY29kaW5nIGRldGVjdGVkIHdpdGggQVAgNzIweDQ4Ngo+ICsg KiBAWFNESVJYX1BBTDogUEFMIGVuY29kaW5nIGRldGVjdGVkIHdpdGggQVAgNzIweDU3Ngo+ICsg KiBAWFNESVJYX1RTX1VOS05PV046IFVua25vd24gU01QVEUgVHJhbnNwb3J0IGZhbWlseSB0eXBl Cj4gKyAqLwo+ICtlbnVtIHNkaV9mYW1pbHlfZW5jIHsKPiArCVhTRElSWF9TTVBURV9TVF8yNzQJ PSAwLAo+ICsJWFNESVJYX1NNUFRFX1NUXzI5Ngk9IDEsCj4gKwlYU0RJUlhfU01QVEVfU1RfMjA0 OF8yCT0gMiwKPiArCVhTRElSWF9TTVBURV9TVF8yOTUJPSAzLAo+ICsJWFNESVJYX05UU0MJCT0g OCwKPiArCVhTRElSWF9QQUwJCT0gOSwKPiArCVhTRElSWF9UU19VTktOT1dOCT0gMTUKPiArfTsK PiArCj4gKy8qKgo+ICsgKiBzdHJ1Y3QgeHNkaXJ4c3Nfc3RhdGUgLSBTREkgUnggU3Vic3lzdGVt IGRldmljZSBzdHJ1Y3R1cmUKPiArICogQHN1YmRldjogVGhlIHY0bDIgc3ViZGV2IHN0cnVjdHVy ZQo+ICsgKiBAY3RybF9oYW5kbGVyOiBjb250cm9sIGhhbmRsZXIKPiArICogQGRlZmF1bHRfZm9y bWF0OiBkZWZhdWx0IFY0TDIgbWVkaWEgYnVzIGZvcm1hdAo+ICsgKiBAcGFkOiBzb3VyY2UgbWVk aWEgcGFkCj4gKyAqIEBkZXY6IFBsYXRmb3JtIHN0cnVjdHVyZQo+ICsgKiBAaW9tZW06IEJhc2Ug YWRkcmVzcyBvZiBzdWJzeXN0ZW0KPiArICogQGNsa3M6IGFycmF5IG9mIGNsb2Nrcwo+ICsgKiBA cHJldl9pc19mcmFjOiBQcmV2aW91cyBjbG9jayBpcyBmcmFjdGlvbmFsIG9yIG5vdCBmbGFnCj4g KyAqIEBicGM6IEJpdHMgcGVyIGNvbXBvbmVudCwgY2FuIGJlIDEwIG9yIDEyCj4gKyAqIEBtb2Rl OiAzRy82Ry8xMkcgbW9kZQo+ICsgKiBAbnVtX2Nsa3M6IG51bWJlciBvZiBjbG9ja3MKPiArICog QGluY2x1ZGVfZWRoOiBFREggcHJvY2Vzc29yIHByZXNlbmNlCj4gKyAqIEBzbG9jazogc3Bpbmxv Y2sgdG8gcHJvdGVjdCBiZWxvdyBtZW1iZXJzCj4gKyAqIEBmb3JtYXQ6IEFjdGl2ZSBWNEwyIGZv cm1hdCBkZXRlY3RlZAo+ICsgKiBAc3JjX2Zvcm1hdDogQWN0aXZlIFY0TDIgZm9ybWF0IG9uIHNv dXJjZSBwYWQKPiArICogQGZyYW1lX2ludGVydmFsOiBDYXB0dXJlcyB0aGUgZnJhbWUgcmF0ZQo+ ICsgKiBAY3VycmVudF90aW1pbmdzOiBEViB0aW1pbmdzIGZyb20gYXBwbGljYXRpb24KPiArICog QGRldGVjdGVkX3RpbWluZ3NfaW5kZXg6IGluZGV4IG9mIERWIHRpbWluZ3MgZGV0ZWN0ZWQgb24g aW5jb21pbmcgc3RyZWFtCj4gKyAqIEB2aWRsb2Nrd2luOiBWaWRlbyBsb2NrIHdpbmRvdyB2YWx1 ZSBzZXQgYnkgY29udHJvbAo+ICsgKiBAZWRobWFzazogRURIIG1hc2sgc2V0IGJ5IGNvbnRyb2wK PiArICogQHNlYXJjaG1hc2s6IFNlYXJjaCBtYXNrIHNldCBieSBjb250cm9sCj4gKyAqIEBzdHJl YW1pbmc6IEZsYWcgZm9yIHN0b3Jpbmcgc3RyZWFtaW5nIHN0YXRlCj4gKyAqIEB2aWRsb2NrZWQ6 IEZsYWcgaW5kaWNhdGluZyBTREkgUnggaGFzIGxvY2tlZCBvbnRvIHZpZGVvIHN0cmVhbQo+ICsg KiBAdHNfaXNfaW50ZXJsYWNlZDogRmxhZyBpbmRpY2F0aW5nIFRyYW5zcG9ydCBTdHJlYW0gaXMg aW50ZXJsYWNlZC4KPiArICogQGZyYW1lcl9lbmFibGU6IEZsYWcgZm9yIGZyYW1lciBlbmFibGVk IG9yIG5vdCBzZXQgYnkgY29udHJvbAo+ICsgKgo+ICsgKiBUaGlzIHN0cnVjdHVyZSBjb250YWlu cyB0aGUgZGV2aWNlIGRyaXZlciByZWxhdGVkIHBhcmFtZXRlcnMKPiArICovCj4gK3N0cnVjdCB4 c2Rpcnhzc19zdGF0ZSB7Cj4gKwlzdHJ1Y3QgdjRsMl9zdWJkZXYgc3ViZGV2Owo+ICsJc3RydWN0 IHY0bDJfY3RybF9oYW5kbGVyIGN0cmxfaGFuZGxlcjsKPiArCXN0cnVjdCB2NGwyX21idXNfZnJh bWVmbXQgZGVmYXVsdF9mb3JtYXQ7Cj4gKwlzdHJ1Y3QgbWVkaWFfcGFkIHBhZDsKPiArCXN0cnVj dCBkZXZpY2UgKmRldjsKPiArCXZvaWQgX19pb21lbSAqaW9tZW07Cj4gKwlzdHJ1Y3QgY2xrX2J1 bGtfZGF0YSAqY2xrczsKPiArCWludCBwcmV2X2lzX2ZyYWM7Cj4gKwl1MzIgYnBjOwo+ICsJdTMy IG1vZGU7Cj4gKwl1bnNpZ25lZCBpbnQgbnVtX2Nsa3M7Cj4gKwlib29sIGluY2x1ZGVfZWRoOwo+ ICsKPiArCS8qCj4gKwkgKiBUaGlzIHNwaW5sb2NrIGlzIHVzZWQgdG8gcHJvdGVjdCB0aGUgYmVs b3cgbWVtYmVycwo+ICsJICogZm9ybWF0LCBzcmNfZm9ybWF0LCBmcmFtZV9pbnRlcnZhbCwgY3Vy cmVudF90aW1pbmdzLAo+ICsJICogZGV0ZWN0ZWRfdGltaW5nc19pbmRleCwgdmlkbG9ja3dpbiwg ZWRobWFzaywgc2VhcmNobWFzaywKPiArCSAqIHN0cmVhbWluZywgdmlkbG9ja2VkLCB0c19pc19p bnRlcmxhY2VkLCBmcmFtZXJfZW5hYmxlCj4gKwkgKi8KPiArCXNwaW5sb2NrX3Qgc2xvY2s7Cj4g KwlzdHJ1Y3QgdjRsMl9tYnVzX2ZyYW1lZm10IGZvcm1hdDsKPiArCXN0cnVjdCB2NGwyX21idXNf ZnJhbWVmbXQgc3JjX2Zvcm1hdDsKPiArCXN0cnVjdCB2NGwyX2ZyYWN0IGZyYW1lX2ludGVydmFs Owo+ICsJc3RydWN0IHY0bDJfZHZfdGltaW5ncyBjdXJyZW50X3RpbWluZ3M7Cj4gKwl1MzIgZGV0 ZWN0ZWRfdGltaW5nc19pbmRleDsKPiArCXUzMiB2aWRsb2Nrd2luOwo+ICsJdTMyIGVkaG1hc2s7 Cj4gKwl1MTYgc2VhcmNobWFzazsKPiArCWJvb2wgc3RyZWFtaW5nOwo+ICsJYm9vbCB2aWRsb2Nr ZWQ7Cj4gKwlib29sIHRzX2lzX2ludGVybGFjZWQ7CgpVc2Ugb2YgYm9vbCBpbiBzdHJ1Y3QgaXMg bm90IHJlY29tbWVuZGVkLiBOb3Qgc3VyZSBpZiBpdCdzIGRvYWJsZSB3aXRoIG9uZXMKZ2V0dGlu ZyB2YWx1ZXMgZnJvbSBvdGhlciBmdW5jdGlvbnMsIGJ1dCBJIGJlbGVpdmUgYWJvdmUgMyBjYW4g Y2hhbmdlIHVzaW5nCmJpdCBmaWVsZCBvciBub3JtYWwgaW50ZWdlciB0eXBlLgoKPiArCWJvb2wg ZnJhbWVyX2VuYWJsZTsKPiArfTsKPiArCj4gKy8qIExpc3Qgb2YgY2xvY2tzIHJlcXVpcmVkIGJ5 IFVIRC1TREkgUnggc3Vic3lzdGVtICovCj4gK3N0YXRpYyBjb25zdCBjaGFyICogY29uc3QgeHNk aXJ4c3NfY2xrc1tdID0gewo+ICsJInNfYXhpX2FjbGsiLCAic2RpX3J4X2NsayIsICJ2aWRlb19v dXRfY2xrIiwKPiArfTsKClRoaXMgY2FuIG1vdmUgaW50byBwcm9iZSgpIHRvIHJlZHVjZSB0aGUg c2NvcGUuCgo+ICsKPiArLyogVE9ETyAtIEFkZCBZVVYgNDQ0LzQyMCBhbmQgUkJHIDEwLzEyIGJw YyBtYnVzIGZvcm1hdHMgaGVyZSAqLwo+ICtzdGF0aWMgY29uc3QgdTMyIHhzZGlyeHNzXzEwYnBj X21idXNfZm10c1tdID0gewo+ICsJTUVESUFfQlVTX0ZNVF9VWVZZMTBfMVgyMCwKPiArfTsKPiAr Cj4gK3N0YXRpYyBjb25zdCB1MzIgeHNkaXJ4c3NfMTJicGNfbWJ1c19mbXRzW10gPSB7Cj4gKwlN RURJQV9CVVNfRk1UX1VZVlkxMl8xWDI0LAo+ICt9Owo+ICsKPiArc3RhdGljIGNvbnN0IHN0cnVj dCB2NGwyX2R2X3RpbWluZ3MgZm10X2NhcFtdID0gewo+ICsJVjRMMl9EVl9CVF9TRElfNzIwWDQ4 N0k2MCwKPiArCVY0TDJfRFZfQlRfQ0VBXzcyMFg1NzZJNTAsCj4gKwlWNEwyX0RWX0JUX0NFQV8x MjgwWDcyMFAyNCwKPiArCVY0TDJfRFZfQlRfQ0VBXzEyODBYNzIwUDI1LAo+ICsJVjRMMl9EVl9C VF9DRUFfMTI4MFg3MjBQMzAsCj4gKwlWNEwyX0RWX0JUX0NFQV8xMjgwWDcyMFA1MCwKPiArCVY0 TDJfRFZfQlRfQ0VBXzEyODBYNzIwUDYwLAo+ICsJVjRMMl9EVl9CVF9DRUFfMTkyMFgxMDgwUDI0 LAo+ICsJVjRMMl9EVl9CVF9DRUFfMTkyMFgxMDgwUDMwLAo+ICsJVjRMMl9EVl9CVF9DRUFfMTky MFgxMDgwSTUwLAo+ICsJVjRMMl9EVl9CVF9DRUFfMTkyMFgxMDgwSTYwLAo+ICsJVjRMMl9EVl9C VF9DRUFfMTkyMFgxMDgwUDQ4LAo+ICsJVjRMMl9EVl9CVF9DRUFfMTkyMFgxMDgwUDUwLAo+ICsJ VjRMMl9EVl9CVF9DRUFfMTkyMFgxMDgwUDYwLAo+ICsJVjRMMl9EVl9CVF9DRUFfMzg0MFgyMTYw UDI0LAo+ICsJVjRMMl9EVl9CVF9DRUFfMzg0MFgyMTYwUDMwLAo+ICsJVjRMMl9EVl9CVF9DRUFf Mzg0MFgyMTYwUDQ4LAo+ICsJVjRMMl9EVl9CVF9DRUFfMzg0MFgyMTYwUDUwLAo+ICsJVjRMMl9E Vl9CVF9DRUFfMzg0MFgyMTYwUDYwLAo+ICsJVjRMMl9EVl9CVF9DRUFfNDA5NlgyMTYwUDI0LAo+ ICsJVjRMMl9EVl9CVF9DRUFfNDA5NlgyMTYwUDI1LAo+ICsJVjRMMl9EVl9CVF9DRUFfNDA5Nlgy MTYwUDMwLAo+ICsJVjRMMl9EVl9CVF9DRUFfNDA5NlgyMTYwUDQ4LAo+ICsJVjRMMl9EVl9CVF9D RUFfNDA5NlgyMTYwUDUwLAo+ICsJVjRMMl9EVl9CVF9DRUFfNDA5NlgyMTYwUDYwLAo+ICsKPiAr CVhMTlhfVjRMMl9EVl9CVF8yMDQ4WDEwODBQMjQsCj4gKwlYTE5YX1Y0TDJfRFZfQlRfMjA0OFgx MDgwUDI1LAo+ICsJWExOWF9WNEwyX0RWX0JUXzIwNDhYMTA4MFAzMCwKPiArCVhMTlhfVjRMMl9E Vl9CVF8yMDQ4WDEwODBJNDgsCj4gKwlYTE5YX1Y0TDJfRFZfQlRfMjA0OFgxMDgwSTUwLAo+ICsJ WExOWF9WNEwyX0RWX0JUXzIwNDhYMTA4MEk2MCwKPiArCVhMTlhfVjRMMl9EVl9CVF8yMDQ4WDEw ODBQNDgsCj4gKwlYTE5YX1Y0TDJfRFZfQlRfMjA0OFgxMDgwUDUwLAo+ICsJWExOWF9WNEwyX0RW X0JUXzIwNDhYMTA4MFA2MCwKPiArCVhMTlhfVjRMMl9EVl9CVF8xOTIwWDEwODBJNDgsCj4gK307 Cj4gKwo+ICtzdHJ1Y3QgeHNkaXJ4c3NfZHZfbWFwIHsKPiArCXUzMiB3aWR0aDsKPiArCXUzMiBo ZWlnaHQ7Cj4gKwl1MzIgZnBzOwo+ICsJc3RydWN0IHY0bDJfZHZfdGltaW5ncyB0aW1pbmc7Cj4g K307Cj4gKwo+ICtzdGF0aWMgY29uc3Qgc3RydWN0IHhzZGlyeHNzX2R2X21hcCB4c2Rpcnhzc19k dl90aW1pbmdzW10gPSB7Cj4gKwkvKiBTRCAtIDcyMHg0ODdpNjAgKi8KPiArCXsgNzIwLCAyNDMs IDMwLCBWNEwyX0RWX0JUX1NESV83MjBYNDg3STYwIH0sCj4gKwkvKiBTRCAtIDcyMHg1NzZpNTAg Ki8KPiArCXsgNzIwLCAyODgsIDI1LCBWNEwyX0RWX0JUX0NFQV83MjBYNTc2STUwIH0sCj4gKwkv KiBIRCAtIDEyODB4NzIwcDIzLjk4ICovCj4gKwkvKiBIRCAtIDEyODB4NzIwcDI0ICovCj4gKwl7 IDEyODAsIDcyMCwgMjQsIFY0TDJfRFZfQlRfQ0VBXzEyODBYNzIwUDI0IH0sCj4gKwkvKiBIRCAt IDEyODB4NzIwcDI1ICovCj4gKwl7IDEyODAsIDcyMCwgMjUsIFY0TDJfRFZfQlRfQ0VBXzEyODBY NzIwUDI1IH0sCj4gKwkvKiBIRCAtIDEyODB4NzIwcDI5Ljk3ICovCj4gKwkvKiBIRCAtIDEyODB4 NzIwcDMwICovCj4gKwl7IDEyODAsIDcyMCwgMzAsIFY0TDJfRFZfQlRfQ0VBXzEyODBYNzIwUDMw IH0sCj4gKwkvKiBIRCAtIDEyODB4NzIwcDUwICovCj4gKwl7IDEyODAsIDcyMCwgNTAsIFY0TDJf RFZfQlRfQ0VBXzEyODBYNzIwUDUwIH0sCj4gKwkvKiBIRCAtIDEyODB4NzIwcDU5Ljk0ICovCj4g KwkvKiBIRCAtIDEyODB4NzIwcDYwICovCj4gKwl7IDEyODAsIDcyMCwgNjAsIFY0TDJfRFZfQlRf Q0VBXzEyODBYNzIwUDYwIH0sCj4gKwkvKiBIRCAtIDE5MjB4MTA4MHAyMy45OCAqLwo+ICsJLyog SEQgLSAxOTIweDEwODBwMjQgKi8KPiArCXsgMTkyMCwgMTA4MCwgMjQsIFY0TDJfRFZfQlRfQ0VB XzE5MjBYMTA4MFAyNCB9LAo+ICsJLyogSEQgLSAxOTIweDEwODBwMjUgKi8KPiArCXsgMTkyMCwg MTA4MCwgMjUsIFY0TDJfRFZfQlRfQ0VBXzE5MjBYMTA4MFAyNSB9LAo+ICsJLyogSEQgLSAxOTIw eDEwODBwMjkuOTcgKi8KPiArCS8qIEhEIC0gMTkyMHgxMDgwcDMwICovCj4gKwl7IDE5MjAsIDEw ODAsIDMwLCBWNEwyX0RWX0JUX0NFQV8xOTIwWDEwODBQMzAgfSwKPiArCj4gKwkvKiBIRCAtIDIw NDh4MTA4MHAyMy45OCAqLwo+ICsJLyogSEQgLSAyMDQ4eDEwODBwMjQgKi8KPiArCXsgMjA0OCwg MTA4MCwgMjQsIFhMTlhfVjRMMl9EVl9CVF8yMDQ4WDEwODBQMjQgfSwKPiArCS8qIEhEIC0gMjA0 OHgxMDgwcDI1ICovCj4gKwl7IDIwNDgsIDEwODAsIDI0LCBYTE5YX1Y0TDJfRFZfQlRfMjA0OFgx MDgwUDI1IH0sCj4gKwkvKiBIRCAtIDIwNDh4MTA4MHAyOS45NyAqLwo+ICsJLyogSEQgLSAyMDQ4 eDEwODBwMzAgKi8KPiArCXsgMjA0OCwgMTA4MCwgMjQsIFhMTlhfVjRMMl9EVl9CVF8yMDQ4WDEw ODBQMzAgfSwKPiArCS8qIEhEIC0gMTkyMHgxMDgwaTQ3Ljk1ICovCj4gKwkvKiBIRCAtIDE5MjB4 MTA4MGk0OCAqLwo+ICsJeyAxOTIwLCA1NDAsIDI0LCBYTE5YX1Y0TDJfRFZfQlRfMTkyMFgxMDgw STQ4IH0sCj4gKwo+ICsJLyogSEQgLSAxOTIweDEwODBpNTAgKi8KPiArCXsgMTkyMCwgNTQwLCAy NSwgVjRMMl9EVl9CVF9DRUFfMTkyMFgxMDgwSTUwIH0sCj4gKwkvKiBIRCAtIDE5MjB4MTA4MGk1 OS45NCAqLwo+ICsJLyogSEQgLSAxOTIweDEwODBpNjAgKi8KPiArCXsgMTkyMCwgNTQwLCAzMCwg VjRMMl9EVl9CVF9DRUFfMTkyMFgxMDgwSTYwIH0sCj4gKwo+ICsJLyogSEQgLSAyMDQ4eDEwODBp NDcuOTUgKi8KPiArCS8qIEhEIC0gMjA0OHgxMDgwaTQ4ICovCj4gKwl7IDIwNDgsIDU0MCwgMjQs IFhMTlhfVjRMMl9EVl9CVF8yMDQ4WDEwODBJNDggfSwKPiArCS8qIEhEIC0gMjA0OHgxMDgwaTUw ICovCj4gKwl7IDIwNDgsIDU0MCwgMjUsIFhMTlhfVjRMMl9EVl9CVF8yMDQ4WDEwODBJNTAgfSwK PiArCS8qIEhEIC0gMjA0OHgxMDgwaTU5Ljk0ICovCj4gKwkvKiBIRCAtIDIwNDh4MTA4MGk2MCAq Lwo+ICsJeyAyMDQ4LCA1NDAsIDMwLCBYTE5YX1Y0TDJfRFZfQlRfMjA0OFgxMDgwSTYwIH0sCj4g KwkvKiAzRyAtIDE5MjB4MTA4MHA0Ny45NSAqLwo+ICsJLyogM0cgLSAxOTIweDEwODBwNDggKi8K PiArCXsgMTkyMCwgMTA4MCwgNDgsIFY0TDJfRFZfQlRfQ0VBXzE5MjBYMTA4MFA0OCB9LAo+ICsK PiArCS8qIDNHIC0gMTkyMHgxMDgwcDUwIDE0OC41ICovCj4gKwl7IDE5MjAsIDEwODAsIDUwLCBW NEwyX0RWX0JUX0NFQV8xOTIwWDEwODBQNTAgfSwKPiArCS8qIDNHIC0gMTkyMHgxMDgwcDU5Ljk0 IDE0OC41LzEuMDAxICovCj4gKwkvKiAzRyAtIDE5MjB4MTA4MHA2MCAxNDguNSAqLwo+ICsJeyAx OTIwLCAxMDgwLCA2MCwgVjRMMl9EVl9CVF9DRUFfMTkyMFgxMDgwUDYwIH0sCj4gKwo+ICsJLyog M0cgLSAyMDQ4eDEwODBwNDcuOTUgKi8KPiArCS8qIDNHIC0gMjA0OHgxMDgwcDQ4ICovCj4gKwl7 IDIwNDgsIDEwODAsIDQ4LCBYTE5YX1Y0TDJfRFZfQlRfMjA0OFgxMDgwUDQ4IH0sCj4gKwkvKiAz RyAtIDIwNDh4MTA4MHA1MCAqLwo+ICsJeyAyMDQ4LCAxMDgwLCA1MCwgWExOWF9WNEwyX0RWX0JU XzIwNDhYMTA4MFA1MCB9LAo+ICsJLyogM0cgLSAyMDQ4eDEwODBwNTkuOTQgKi8KPiArCS8qIDNH IC0gMjA0OHgxMDgwcDYwICovCj4gKwl7IDIwNDgsIDEwODAsIDYwLCBYTE5YX1Y0TDJfRFZfQlRf MjA0OFgxMDgwUDYwIH0sCj4gKwo+ICsJLyogNkcgLSAzODQwWDIxNjBwMjMuOTggKi8KPiArCS8q IDZHIC0gMzg0MFgyMTYwcDI0ICovCj4gKwl7IDM4NDAsIDIxNjAsIDI0LCBWNEwyX0RWX0JUX0NF QV8zODQwWDIxNjBQMjQgfSwKPiArCS8qIDZHIC0gMzg0MFgyMTYwcDI1ICovCj4gKwl7IDM4NDAs IDIxNjAsIDI1LCBWNEwyX0RWX0JUX0NFQV8zODQwWDIxNjBQMjUgfSwKPiArCS8qIDZHIC0gMzg0 MFgyMTYwcDI5Ljk3ICovCj4gKwkvKiA2RyAtIDM4NDBYMjE2MHAzMCAqLwo+ICsJeyAzODQwLCAy MTYwLCAzMCwgVjRMMl9EVl9CVF9DRUFfMzg0MFgyMTYwUDMwIH0sCj4gKwkvKiA2RyAtIDQwOTZY MjE2MHAyMy45OCAqLwo+ICsJLyogNkcgLSA0MDk2WDIxNjBwMjQgKi8KPiArCXsgNDA5NiwgMjE2 MCwgMjQsIFY0TDJfRFZfQlRfQ0VBXzQwOTZYMjE2MFAyNCB9LAo+ICsJLyogNkcgLSA0MDk2WDIx NjBwMjUgKi8KPiArCXsgNDA5NiwgMjE2MCwgMjUsIFY0TDJfRFZfQlRfQ0VBXzQwOTZYMjE2MFAy NSB9LAo+ICsJLyogNkcgLSA0MDk2WDIxNjBwMjkuOTcgKi8KPiArCS8qIDZHIC0gNDA5NlgyMTYw cDMwICovCj4gKwl7IDQwOTYsIDIxNjAsIDMwLCBWNEwyX0RWX0JUX0NFQV80MDk2WDIxNjBQMzAg fSwKPiArCS8qIDEyRyAtIDM4NDBYMjE2MHA0Ny45NSAqLwo+ICsJLyogMTJHIC0gMzg0MFgyMTYw cDQ4ICovCj4gKwl7IDM4NDAsIDIxNjAsIDQ4LCBWNEwyX0RWX0JUX0NFQV8zODQwWDIxNjBQNDgg fSwKPiArCj4gKwkvKiAxMkcgLSAzODQwWDIxNjBwNTAgKi8KPiArCXsgMzg0MCwgMjE2MCwgNTAs IFY0TDJfRFZfQlRfQ0VBXzM4NDBYMjE2MFA1MCB9LAo+ICsJLyogMTJHIC0gMzg0MFgyMTYwcDU5 Ljk0ICovCj4gKwkvKiAxMkcgLSAzODQwWDIxNjBwNjAgKi8KPiArCXsgMzg0MCwgMjE2MCwgNjAs IFY0TDJfRFZfQlRfQ0VBXzM4NDBYMjE2MFA2MCB9LAo+ICsKPiArCS8qIDEyRyAtIDQwOTZYMjE2 MHA0Ny45NSAqLwo+ICsJLyogMTJHIC0gNDA5NlgyMTYwcDQ4ICovCj4gKwl7IDM4NDAsIDIxNjAs IDQ4LCBWNEwyX0RWX0JUX0NFQV80MDk2WDIxNjBQNDggfSwKPiArCj4gKwkvKiAxMkcgLSA0MDk2 WDIxNjBwNTAgKi8KPiArCXsgNDA5NiwgMjE2MCwgNTAsIFY0TDJfRFZfQlRfQ0VBXzQwOTZYMjE2 MFA1MCB9LAo+ICsJLyogMTJHIC0gNDA5NlgyMTYwcDU5Ljk0ICovCj4gKwkvKiAxMkcgLSA0MDk2 WDIxNjBwNjAgKi8KPiArCXsgNDA5NiwgMjE2MCwgNjAsIFY0TDJfRFZfQlRfQ0VBXzQwOTZYMjE2 MFA2MCB9LAo+ICt9Owo+ICsKPiArc3RhdGljIGNvbnN0IHN0cnVjdCB2NGwyX2R2X3RpbWluZ3Nf Y2FwIHhzZGlyeHNzX3RpbWluZ3NfY2FwID0gewo+ICsJLnR5cGUgPSBWNEwyX0RWX0JUXzY1Nl8x MTIwLAo+ICsJLnBhZCA9IDAsCj4gKwkucmVzZXJ2ZWQgPSB7IDAgfSwKPiArCVY0TDJfSU5JVF9C VF9USU1JTkdTKFhTRElSWFNTX1dJRFRIX01JTiwgWFNESVJYU1NfV0lEVEhfTUFYLAo+ICsJCQkg ICAgIFhTRElSWFNTX0hFSUdIVF9NSU4sIFhTRElSWFNTX0hFSUdIVF9NQVgsCj4gKwkJCSAgICAg WFNESVJYU1NfUElYRUxDTE9DS19NSU4sIFhTRElSWFNTX1BJWEVMQ0xPQ0tfTUFYLAo+ICsJCQkg ICAgIFY0TDJfRFZfQlRfU1REX0NFQTg2MSB8IFY0TDJfRFZfQlRfU1REX1NESSwKPiArCQkJICAg ICBWNEwyX0RWX0JUX0NBUF9QUk9HUkVTU0lWRQo+ICsJCQkgICAgIHwgVjRMMl9EVl9CVF9DQVBf SU5URVJMQUNFRCkKPiArCj4gK307Cj4gKwo+ICtzdHJ1Y3QgcmVnbWFwIHsKPiArCWNvbnN0IGNo YXIgKm5hbWU7Cj4gKwl1MzIgb2Zmc2V0Owo+ICt9Owo+ICsKPiArc3RhdGljIGNvbnN0IHN0cnVj dCByZWdtYXAgeHNkaXJ4c3NfcmVnbWFwW10gPSB7Cj4gKwl7IC5uYW1lID0gIlJlc2V0IENvbnRy b2wiLCAub2Zmc2V0ID0gWFNESVJYX1JTVF9DVFJMX1JFRyB9LAo+ICsJeyAubmFtZSA9ICJNb2R1 bGUgQ29udHJvbCIsIC5vZmZzZXQgPSBYU0RJUlhfTURMX0NUUkxfUkVHIH0sCj4gKwl7IC5uYW1l ID0gIkludGVycnVwdCBFbmFibGUiLCAub2Zmc2V0ID0gWFNESVJYX0lFUl9SRUcgfSwKPiArCXsg Lm5hbWUgPSAiR2xvYmFsIEludGVycnVwdCBFbmFibGUiLCAub2Zmc2V0ID0gWFNESVJYX0dMQkxf SUVSX1JFRyB9LAo+ICsJeyAubmFtZSA9ICJTVDM1MiBWYWxpZCIsIC5vZmZzZXQgPSBYU0RJUlhf U1QzNTJfVkFMSURfUkVHIH0sCj4gKwl7IC5uYW1lID0gIlNUMzUyIERTMSIsIC5vZmZzZXQgPSBY U0RJUlhfU1QzNTJfRFMxX1JFRyB9LAo+ICsJeyAubmFtZSA9ICJTVDM1MiBEUzIiLCAub2Zmc2V0 ID0gWFNESVJYX1NUMzUyX0RTMl9SRUcgfSwKPiArCXsgLm5hbWUgPSAiU1QzNTIgRFMzIiwgLm9m ZnNldCA9IFhTRElSWF9TVDM1Ml9EUzNfUkVHIH0sCj4gKwl7IC5uYW1lID0gIlNUMzUyIERTNCIs IC5vZmZzZXQgPSBYU0RJUlhfU1QzNTJfRFM0X1JFRyB9LAo+ICsJeyAubmFtZSA9ICJTVDM1MiBE UzUiLCAub2Zmc2V0ID0gWFNESVJYX1NUMzUyX0RTNV9SRUcgfSwKPiArCXsgLm5hbWUgPSAiU1Qz NTIgRFM2IiwgLm9mZnNldCA9IFhTRElSWF9TVDM1Ml9EUzZfUkVHIH0sCj4gKwl7IC5uYW1lID0g IlNUMzUyIERTNyIsIC5vZmZzZXQgPSBYU0RJUlhfU1QzNTJfRFM3X1JFRyB9LAo+ICsJeyAubmFt ZSA9ICJTVDM1MiBEUzgiLCAub2Zmc2V0ID0gWFNESVJYX1NUMzUyX0RTOF9SRUcgfSwKPiArCXsg Lm5hbWUgPSAiU1QzNTIgRFM5IiwgLm9mZnNldCA9IFhTRElSWF9TVDM1Ml9EUzlfUkVHIH0sCj4g Kwl7IC5uYW1lID0gIlNUMzUyIERTMTAiLCAub2Zmc2V0ID0gWFNESVJYX1NUMzUyX0RTMTBfUkVH IH0sCj4gKwl7IC5uYW1lID0gIlNUMzUyIERTMTEiLCAub2Zmc2V0ID0gWFNESVJYX1NUMzUyX0RT MTFfUkVHIH0sCj4gKwl7IC5uYW1lID0gIlNUMzUyIERTMTIiLCAub2Zmc2V0ID0gWFNESVJYX1NU MzUyX0RTMTJfUkVHIH0sCj4gKwl7IC5uYW1lID0gIlNUMzUyIERTMTMiLCAub2Zmc2V0ID0gWFNE SVJYX1NUMzUyX0RTMTNfUkVHIH0sCj4gKwl7IC5uYW1lID0gIlNUMzUyIERTMTQiLCAub2Zmc2V0 ID0gWFNESVJYX1NUMzUyX0RTMTRfUkVHIH0sCj4gKwl7IC5uYW1lID0gIlNUMzUyIERTMTUiLCAu b2Zmc2V0ID0gWFNESVJYX1NUMzUyX0RTMTVfUkVHIH0sCj4gKwl7IC5uYW1lID0gIlNUMzUyIERT MTYiLCAub2Zmc2V0ID0gWFNESVJYX1NUMzUyX0RTMTZfUkVHIH0sCj4gKwl7IC5uYW1lID0gIlZl cnNpb24iLCAub2Zmc2V0ID0gWFNESVJYX1ZFUlNJT05fUkVHIH0sCj4gKwl7IC5uYW1lID0gIlN1 YnN5c3RlbSBDb25maWcgIiwgLm9mZnNldCA9IFhTRElSWF9TU19DT05GSUdfUkVHIH0sCj4gKwl7 IC5uYW1lID0gIk1vZGUgRGV0ZWN0IiwgLm9mZnNldCA9IFhTRElSWF9NT0RFX0RFVF9TVEFUX1JF RyB9LAo+ICsJeyAubmFtZSA9ICJUcmFuc3BvcnQgU3RyZWFtIERldGVjdCIsIC5vZmZzZXQgPSBY U0RJUlhfVFNfREVUX1NUQVRfUkVHIH0sCj4gKwl7IC5uYW1lID0gIkVESCBTdGF0dXMiLCAub2Zm c2V0ID0gWFNESVJYX0VESF9TVEFUX1JFRyB9LAo+ICsJeyAubmFtZSA9ICJFREggRXJyb3IgQ291 bnQiLCAub2Zmc2V0ID0gWFNESVJYX0VESF9FUlJDTlRfRU5fUkVHIH0sCj4gKwl7IC5uYW1lID0g IkNSQyBlcnJvciBpbmRpY2F0aW9uIiwgLm9mZnNldCA9IFhTRElSWF9DUkNfRVJSQ05UX1JFRyB9 LAo+ICsJeyAubmFtZSA9ICJWaWRlbyBMb2NrIFdpbmRvdyIsIC5vZmZzZXQgPSBYU0RJUlhfVklE X0xPQ0tfV0lORE9XX1JFRyB9LAo+ICt9Owo+ICsKPiArc3RhdGljIGlubGluZSBzdHJ1Y3QgeHNk aXJ4c3Nfc3RhdGUgKgo+ICt0b194c2Rpcnhzc3N0YXRlKHN0cnVjdCB2NGwyX3N1YmRldiAqc3Vi ZGV2KQo+ICt7Cj4gKwlyZXR1cm4gY29udGFpbmVyX29mKHN1YmRldiwgc3RydWN0IHhzZGlyeHNz X3N0YXRlLCBzdWJkZXYpOwo+ICt9Cj4gKwo+ICsvKgo+ICsgKiBSZWdpc3RlciByZWxhdGVkIG9w ZXJhdGlvbnMKPiArICovCj4gK3N0YXRpYyBpbmxpbmUgdTMyIHhzZGlyeHNzX3JlYWQoc3RydWN0 IHhzZGlyeHNzX3N0YXRlICp4c2RpcnhzcywgdTMyIGFkZHIpCj4gK3sKPiArCXJldHVybiBpb3Jl YWQzMih4c2Rpcnhzcy0+aW9tZW0gKyBhZGRyKTsKPiArfQo+ICsKPiArc3RhdGljIGlubGluZSB2 b2lkIHhzZGlyeHNzX3dyaXRlKHN0cnVjdCB4c2Rpcnhzc19zdGF0ZSAqeHNkaXJ4c3MsIHUzMiBh ZGRyLAo+ICsJCQkJICB1MzIgdmFsdWUpCj4gK3sKPiArCWlvd3JpdGUzMih2YWx1ZSwgeHNkaXJ4 c3MtPmlvbWVtICsgYWRkcik7Cj4gK30KPiArCj4gK3N0YXRpYyBpbmxpbmUgdm9pZCB4c2Rpcnhz c19jbHIoc3RydWN0IHhzZGlyeHNzX3N0YXRlICp4c2RpcnhzcywgdTMyIGFkZHIsCj4gKwkJCQl1 MzIgY2xyKQo+ICt7Cj4gKwl4c2Rpcnhzc193cml0ZSh4c2RpcnhzcywgYWRkciwgeHNkaXJ4c3Nf cmVhZCh4c2RpcnhzcywgYWRkcikgJiB+Y2xyKTsKPiArfQo+ICsKPiArc3RhdGljIGlubGluZSB2 b2lkIHhzZGlyeHNzX3NldChzdHJ1Y3QgeHNkaXJ4c3Nfc3RhdGUgKnhzZGlyeHNzLCB1MzIgYWRk ciwKPiArCQkJCXUzMiBzZXQpCj4gK3sKPiArCXhzZGlyeHNzX3dyaXRlKHhzZGlyeHNzLCBhZGRy LCB4c2Rpcnhzc19yZWFkKHhzZGlyeHNzLCBhZGRyKSB8IHNldCk7Cj4gK30KPiArCgpJbiBteSBv cGluaW9uLCBmcm9tIGhlcmUgdG8KCj4gKyNkZWZpbmUgWFNESVJYX0NPUkVfRElTQUJMRShzdGF0 ZSkgIHhzZGlyeHNzX2Nscigoc3RhdGUpLCBYU0RJUlhfUlNUX0NUUkxfUkVHLFwKPiArCQkJCQkJ IFhTRElSWF9SU1RfQ1RSTF9TU19FTl9NQVNLKQo+ICsKPiArI2RlZmluZSBYU0RJUlhfQ09SRV9F TkFCTEUoc3RhdGUpICB4c2Rpcnhzc19zZXQoKHN0YXRlKSwgWFNESVJYX1JTVF9DVFJMX1JFRyxc Cj4gKwkJCQkJCVhTRElSWF9SU1RfQ1RSTF9TU19FTl9NQVNLKQo+ICsKPiArI2RlZmluZSBYU0RJ UlhfR0xPQkFMX0lOVFJfRU5BQkxFKHN0YXRlKQlcCj4gKwl4c2Rpcnhzc19zZXQoKHN0YXRlKSwg WFNESVJYX0dMQkxfSUVSX1JFRywgWFNESVJYX0dMQkxfSU5UUl9FTl9NQVNLKQo+ICsKPiArI2Rl ZmluZSBYU0RJUlhfR0xPQkFMX0lOVFJfRElTQUJMRShzdGF0ZSkJXAo+ICsJeHNkaXJ4c3NfY2xy KChzdGF0ZSksIFhTRElSWF9HTEJMX0lFUl9SRUcsIFhTRElSWF9HTEJMX0lOVFJfRU5fTUFTSykK CmhlcmUsIGlubGluaW5nIHNpbmdsZSBsaW5lcnMgb3Igc3RhdGljIGlubGluZSB3b3VsZCBiZSBi ZXR0ZXIgdGhhbiBhYm92ZSBtYWNyb3MuCgo+ICsKPiArc3RhdGljIGludCB4c2Rpcnhfc2V0X21v ZGVkZXRlY3Qoc3RydWN0IHhzZGlyeHNzX3N0YXRlICpzdGF0ZSwgdTE2IG1hc2spCj4gK3sKPiAr CXUzMiB2YWw7Cj4gKwlzdHJ1Y3QgZGV2aWNlICpkZXYgPSBzdGF0ZS0+ZGV2Owo+ICsKPiArCW1h c2sgJj0gWFNESVJYX0RFVEVDVF9BTExfTU9ERVM7Cj4gKwlpZiAoIW1hc2spIHsKPiArCQlkZXZf ZXJyKGRldiwgIkludmFsaWQgYml0IG1hc2sgPSAweCUwOHhcbiIsIG1hc2spOwo+ICsJCXJldHVy biAtRUlOVkFMOwo+ICsJfQo+ICsKPiArCWRldl9kYmcoZGV2LCAibWFzayA9IDB4JXhcbiIsIG1h c2spOwo+ICsKPiArCXZhbCA9IHhzZGlyeHNzX3JlYWQoc3RhdGUsIFhTRElSWF9NRExfQ1RSTF9S RUcpOwo+ICsJdmFsICY9IH5YU0RJUlhfTURMX0NUUkxfTU9ERV9ERVRfRU5fTUFTSzsKPiArCXZh bCAmPSB+WFNESVJYX01ETF9DVFJMX01PREVfQVVUT19ERVRfTUFTSzsKPiArCXZhbCAmPSB+WFNE SVJYX01ETF9DVFJMX0ZPUkNFRF9NT0RFX01BU0s7Cj4gKwo+ICsJaWYgKGh3ZWlnaHQxNihtYXNr KSA+IDEpIHsKPiArCQkvKiBNdWx0aSBtb2RlIGRldGVjdGlvbiBhcyBtb3JlIHRoYW4gMSBiaXQg c2V0IGluIG1hc2sgKi8KPiArCQlkZXZfZGJnKGRldiwgIkRldGVjdCBtdWx0aXBsZSBtb2Rlc1xu Iik7Cj4gKwo+ICsJCWlmIChtYXNrICYgQklUKFhTRElSWF9NT0RFX1NEX09GRlNFVCkpCj4gKwkJ CXZhbCB8PSBYU0RJUlhfTURMX0NUUkxfTU9ERV9TRF9FTl9NQVNLOwo+ICsJCWlmIChtYXNrICYg QklUKFhTRElSWF9NT0RFX0hEX09GRlNFVCkpCj4gKwkJCXZhbCB8PSBYU0RJUlhfTURMX0NUUkxf TU9ERV9IRF9FTl9NQVNLOwo+ICsJCS8qCj4gKwkJICogVGhlcmUgaXMgb25seSBvbmUgYml0IGlu IElQIHRvIGRldGVjdCAzRyBtb2RlLgo+ICsJCSAqIFNvIHNldCBpdCB3aGVuIDNHQSBvciAzR0Ig bWFzayBpcyBzZXQuCj4gKwkJICovCj4gKwkJaWYgKG1hc2sgJiAoQklUKFhTRElSWF9NT0RFXzNH QV9PRkZTRVQpIHwKPiArCQkJICAgIEJJVChYU0RJUlhfTU9ERV8zR0JfT0ZGU0VUKSkpCj4gKwkJ CXZhbCB8PSBYU0RJUlhfTURMX0NUUkxfTU9ERV8zR19FTl9NQVNLOwo+ICsJCWlmIChtYXNrICYg QklUKFhTRElSWF9NT0RFXzZHX09GRlNFVCkpCj4gKwkJCXZhbCB8PSBYU0RJUlhfTURMX0NUUkxf TU9ERV82R19FTl9NQVNLOwo+ICsJCWlmIChtYXNrICYgQklUKFhTRElSWF9NT0RFXzEyR0lfT0ZG U0VUKSkKPiArCQkJdmFsIHw9IFhTRElSWF9NRExfQ1RSTF9NT0RFXzEyR0lfRU5fTUFTSzsKPiAr CQlpZiAobWFzayAmIEJJVChYU0RJUlhfTU9ERV8xMkdGX09GRlNFVCkpCj4gKwkJCXZhbCB8PSBY U0RJUlhfTURMX0NUUkxfTU9ERV8xMkdGX0VOX01BU0s7Cj4gKwo+ICsJCXZhbCB8PSBYU0RJUlhf TURMX0NUUkxfTU9ERV9ERVRfRU5fTUFTSzsKPiArCX0gZWxzZSB7Cj4gKwkJLyogRml4ZWQgTW9k ZSAqLwo+ICsJCXUzMiBmb3JjZWRfbW9kZV9tYXNrOwo+ICsKPiArCQlkZXZfZGJnKGRldiwgIkRl dGVjdCBmaXhlZCBtb2RlXG4iKTsKPiArCj4gKwkJLyogRmluZCBvZmZzZXQgb2YgZmlyc3QgYml0 IHNldCAqLwo+ICsJCXN3aXRjaCAobWFzaykgewo+ICsJCWNhc2UgWFNESVJYX01PREVfU0RfT0ZG U0VUOgo+ICsJCQlmb3JjZWRfbW9kZV9tYXNrID0gWFNESVJYX01PREVfU0RfTUFTSzsKPiArCQkJ YnJlYWs7Cj4gKwkJY2FzZSBYU0RJUlhfTU9ERV9IRF9PRkZTRVQ6Cj4gKwkJCWZvcmNlZF9tb2Rl X21hc2sgPSBYU0RJUlhfTU9ERV9IRF9NQVNLOwo+ICsJCQlicmVhazsKPiArCQkvKgo+ICsJCSAq IFRoZXJlIGlzIG9ubHkgb25lIGJpdCBpbiBJUCB0byBkZXRlY3QgM0cgbW9kZS4KPiArCQkgKiBT byBzZXQgaXQgd2hlbiAzR0Egb3IgM0dCIG1hc2sgaXMgc2V0Lgo+ICsJCSAqLwo+ICsJCWNhc2Ug WFNESVJYX01PREVfM0dBX09GRlNFVDoKPiArCQljYXNlIFhTRElSWF9NT0RFXzNHQl9PRkZTRVQ6 Cj4gKwkJCWZvcmNlZF9tb2RlX21hc2sgPSBYU0RJUlhfTU9ERV8zR19NQVNLOwo+ICsJCQlicmVh azsKPiArCQljYXNlIFhTRElSWF9NT0RFXzZHX09GRlNFVDoKPiArCQkJZm9yY2VkX21vZGVfbWFz ayA9IFhTRElSWF9NT0RFXzZHX01BU0s7Cj4gKwkJCWJyZWFrOwo+ICsJCWNhc2UgWFNESVJYX01P REVfMTJHSV9PRkZTRVQ6Cj4gKwkJCWZvcmNlZF9tb2RlX21hc2sgPSBYU0RJUlhfTU9ERV8xMkdJ X01BU0s7Cj4gKwkJCWJyZWFrOwo+ICsJCWNhc2UgWFNESVJYX01PREVfMTJHRl9PRkZTRVQ6Cj4g KwkJCWZvcmNlZF9tb2RlX21hc2sgPSBYU0RJUlhfTU9ERV8xMkdGX01BU0s7Cj4gKwkJCWJyZWFr Owo+ICsJCWRlZmF1bHQ6Cj4gKwkJCWRldl9lcnIoZGV2LCAiSW52YWxpZCBtYXNrIGZvciBmaXhl ZCBkZXRlY3QgbW9kZVxuIik7Cj4gKwkJCXJldHVybiAtRUlOVkFMOwo+ICsJCX0KPiArCQlkZXZf ZGJnKGRldiwgIkZvcmNlZCBNb2RlIE1hc2sgOiAweCV4XG4iLAo+ICsJCQlmb3JjZWRfbW9kZV9t YXNrKTsKPiArCQl2YWwgfD0gZm9yY2VkX21vZGVfbWFzayA8PCBYU0RJUlhfTURMX0NUUkxfRk9S Q0VEX01PREVfT0ZGU0VUOwo+ICsJfQo+ICsKPiArCWRldl9kYmcoZGV2LCAiTW9kZXMgdG8gYmUg ZGV0ZWN0ZWQgOiBzZGkgY3RybCByZWcgPSAweCUwOHhcbiIsCj4gKwkJdmFsKTsKPiArCXhzZGly eHNzX3dyaXRlKHN0YXRlLCBYU0RJUlhfTURMX0NUUkxfUkVHLCB2YWwpOwo+ICsKPiArCXJldHVy biAwOwo+ICt9Cj4gKwo+ICtzdGF0aWMgdm9pZCB4c2Rpcnhfc3RyZWFtZmxvd19jb250cm9sKHN0 cnVjdCB4c2Rpcnhzc19zdGF0ZSAqc3RhdGUsIGJvb2wgZW5hYmxlKQo+ICt7Cj4gKwkvKiBUaGUg c2RpIHRvIG5hdGl2ZSBicmlkZ2UgaXMgZm9sbG93ZWQgYnkgbmF0aXZlIHRvIGF4aXM0IGJyaWRn ZSAqLwo+ICsJLyoKPiArCSAqIFRPRE8gLSBFbmFibGUgWVVWNDQ0L1JCRyBmb3JtYXQgaW4gdGhl IGJyaWRnZSBiYXNlZAo+ICsJICogb24gQllURTMgY29sb3IgZm9ybWF0Lgo+ICsJICogWFNESVJY X1JTVF9DVFJMX0JSSURHRV9DSF9GTVRfWVVWNDQ0Cj4gKwkgKi8KPiArCWlmIChlbmFibGUpIHsK PiArCQl4c2Rpcnhzc19zZXQoc3RhdGUsIFhTRElSWF9SU1RfQ1RSTF9SRUcsCj4gKwkJCSAgICAg WFNESVJYX1JTVF9DVFJMX1ZJRElOX0FYSTRTX01PRF9FTkJfTUFTSyk7Cj4gKwkJeHNkaXJ4c3Nf c2V0KHN0YXRlLCBYU0RJUlhfUlNUX0NUUkxfUkVHLAo+ICsJCQkgICAgIFhTRElSWF9SU1RfQ1RS TF9TRElSWF9CUklER0VfRU5CX01BU0spOwo+ICsJfSBlbHNlIHsKPiArCQl4c2Rpcnhzc19jbHIo c3RhdGUsIFhTRElSWF9SU1RfQ1RSTF9SRUcsCj4gKwkJCSAgICAgWFNESVJYX1JTVF9DVFJMX1NE SVJYX0JSSURHRV9FTkJfTUFTSyk7Cj4gKwkJeHNkaXJ4c3NfY2xyKHN0YXRlLCBYU0RJUlhfUlNU X0NUUkxfUkVHLAo+ICsJCQkgICAgIFhTRElSWF9SU1RfQ1RSTF9WSURJTl9BWEk0U19NT0RfRU5C X01BU0spOwo+ICsJfQo+ICsJc3RhdGUtPnN0cmVhbWluZyA9IGVuYWJsZTsKPiArfQo+ICsKPiAr c3RhdGljIHZvaWQgeHNkaXJ4c3NfZ2V0X2ZyYW1lcmF0ZShzdHJ1Y3QgdjRsMl9mcmFjdCAqZnJh bWVfaW50ZXJ2YWwsCj4gKwkJCQkgICB1MzIgZnJhbWVyYXRlKQo+ICt7Cj4gKwlzd2l0Y2ggKGZy YW1lcmF0ZSkgewo+ICsJY2FzZSBYU0RJUlhfVFNfREVUX1NUQVRfUkFURV8yM185OEhaOgo+ICsJ CWZyYW1lX2ludGVydmFsLT5udW1lcmF0b3IgPSAxMDAxOwo+ICsJCWZyYW1lX2ludGVydmFsLT5k ZW5vbWluYXRvciA9IDI0MDAwOwo+ICsJCWJyZWFrOwo+ICsJY2FzZSBYU0RJUlhfVFNfREVUX1NU QVRfUkFURV8yNEhaOgo+ICsJCWZyYW1lX2ludGVydmFsLT5udW1lcmF0b3IgPSAxMDAwOwo+ICsJ CWZyYW1lX2ludGVydmFsLT5kZW5vbWluYXRvciA9IDI0MDAwOwo+ICsJCWJyZWFrOwo+ICsJY2Fz ZSBYU0RJUlhfVFNfREVUX1NUQVRfUkFURV8yNUhaOgo+ICsJCWZyYW1lX2ludGVydmFsLT5udW1l cmF0b3IgPSAxMDAwOwo+ICsJCWZyYW1lX2ludGVydmFsLT5kZW5vbWluYXRvciA9IDI1MDAwOwo+ ICsJCWJyZWFrOwo+ICsJY2FzZSBYU0RJUlhfVFNfREVUX1NUQVRfUkFURV8yOV85N0haOgo+ICsJ CWZyYW1lX2ludGVydmFsLT5udW1lcmF0b3IgPSAxMDAxOwo+ICsJCWZyYW1lX2ludGVydmFsLT5k ZW5vbWluYXRvciA9IDMwMDAwOwo+ICsJCWJyZWFrOwo+ICsJY2FzZSBYU0RJUlhfVFNfREVUX1NU QVRfUkFURV8zMEhaOgo+ICsJCWZyYW1lX2ludGVydmFsLT5udW1lcmF0b3IgPSAxMDAwOwo+ICsJ CWZyYW1lX2ludGVydmFsLT5kZW5vbWluYXRvciA9IDMwMDAwOwo+ICsJCWJyZWFrOwo+ICsJY2Fz ZSBYU0RJUlhfVFNfREVUX1NUQVRfUkFURV80N185NUhaOgo+ICsJCWZyYW1lX2ludGVydmFsLT5u dW1lcmF0b3IgPSAxMDAxOwo+ICsJCWZyYW1lX2ludGVydmFsLT5kZW5vbWluYXRvciA9IDQ4MDAw Owo+ICsJCWJyZWFrOwo+ICsJY2FzZSBYU0RJUlhfVFNfREVUX1NUQVRfUkFURV80OEhaOgo+ICsJ CWZyYW1lX2ludGVydmFsLT5udW1lcmF0b3IgPSAxMDAwOwo+ICsJCWZyYW1lX2ludGVydmFsLT5k ZW5vbWluYXRvciA9IDQ4MDAwOwo+ICsJCWJyZWFrOwo+ICsJY2FzZSBYU0RJUlhfVFNfREVUX1NU QVRfUkFURV81MEhaOgo+ICsJCWZyYW1lX2ludGVydmFsLT5udW1lcmF0b3IgPSAxMDAwOwo+ICsJ CWZyYW1lX2ludGVydmFsLT5kZW5vbWluYXRvciA9IDUwMDAwOwo+ICsJCWJyZWFrOwo+ICsJY2Fz ZSBYU0RJUlhfVFNfREVUX1NUQVRfUkFURV81OV85NEhaOgo+ICsJCWZyYW1lX2ludGVydmFsLT5u dW1lcmF0b3IgPSAxMDAxOwo+ICsJCWZyYW1lX2ludGVydmFsLT5kZW5vbWluYXRvciA9IDYwMDAw Owo+ICsJCWJyZWFrOwo+ICsJY2FzZSBYU0RJUlhfVFNfREVUX1NUQVRfUkFURV82MEhaOgo+ICsJ CWZyYW1lX2ludGVydmFsLT5udW1lcmF0b3IgPSAxMDAwOwo+ICsJCWZyYW1lX2ludGVydmFsLT5k ZW5vbWluYXRvciA9IDYwMDAwOwo+ICsJCWJyZWFrOwo+ICsJZGVmYXVsdDoKPiArCQlmcmFtZV9p bnRlcnZhbC0+bnVtZXJhdG9yID0gMTsKPiArCQlmcmFtZV9pbnRlcnZhbC0+ZGVub21pbmF0b3Ig PSAxOwoKVGhpcyBzaG91bGRuJ3QgaGFwcGVuLCBzbyB3b3VsZCBpdCBtYWtlIHNlbnNlIHRvIGhh dmUgYW4gZXJyb3IgaGVyZT8KCj4gKwl9Cj4gK30KPiArCj4gK3N0YXRpYyB2b2lkIHhzZGlyeHNz X3NldF9ndGNsayhzdHJ1Y3QgeHNkaXJ4c3Nfc3RhdGUgKnN0YXRlKQo+ICt7Cj4gKwlzdHJ1Y3Qg Y2xrICpndGNsazsKClRoaXMgdmFyaWFibGUgaXMgbm90IG5lZWRlZC4gVXAgdG8geW91LgoKPiAr CXVuc2lnbmVkIGxvbmcgY2xrcmF0ZTsKPiArCWludCByZXQsIGlzX2ZyYWM7Cj4gKwl1MzIgbW9k ZTsKPiArCj4gKwltb2RlID0geHNkaXJ4c3NfcmVhZChzdGF0ZSwgWFNESVJYX01PREVfREVUX1NU QVRfUkVHKTsKPiArCW1vZGUgJj0gWFNESVJYX01PREVfREVUX1NUQVRfUlhfTU9ERV9NQVNLOwo+ ICsKPiArCS8qCj4gKwkgKiBUT0RPOiBGb3Igbm93LCBkb24ndCBjaGFuZ2UgdGhlIGNsb2NrIHJh dGUgZm9yIGFueSBtb2RlIGV4Y2VwdCAxMkcuCj4gKwkgKiBJbiBmdXR1cmUsIGNvbmZpZ3VyZSBn dCBjbG9jayBmb3IgYWxsIG1vZGVzIGFuZCBlbmFibGUgY2xvY2sgb25seQo+ICsJICogd2hlbiBu ZWVkZWQgKHN0cmVhbSBvbi9vZmYpLgo+ICsJICovCj4gKwlpZiAobW9kZSAhPSBYU0RJUlhfTU9E RV8xMkdJX01BU0sgJiYgbW9kZSAhPSBYU0RJUlhfTU9ERV8xMkdGX01BU0spCj4gKwkJcmV0dXJu Owo+ICsKPiArCS8qIFdoZW4gbnVtZXJhdG9yIGlzIDEwMDEgdGhlbiBmcmFtZSByYXRlIGlzIGZy YWN0aW9uYWwgZWxzZSBpbnRlZ2VyICovCj4gKwlpc19mcmFjID0gc3RhdGUtPmZyYW1lX2ludGVy dmFsLm51bWVyYXRvciA9PSAxMDAxID8gMSA6IDA7Cj4gKwo+ICsJaWYgKHN0YXRlLT5wcmV2X2lz X2ZyYWMgPT0gaXNfZnJhYykKPiArCQlyZXR1cm47Cj4gKwo+ICsJWFNESVJYX0dMT0JBTF9JTlRS X0RJU0FCTEUoc3RhdGUpOwo+ICsJeHNkaXJ4c3NfY2xyKHN0YXRlLCBYU0RJUlhfSUVSX1JFRywg WFNESVJYX0lOVFJfQUxMX01BU0spOwo+ICsJWFNESVJYX0NPUkVfRElTQUJMRShzdGF0ZSk7Cj4g Kwo+ICsJLyogZ2V0IHNkaV9yeF9jbGsgKi8KCkknZCByZW1vdmUgdGhpcyBjb21tZW50LAoKPiAr CWd0Y2xrID0gc3RhdGUtPmNsa3NbMV0uY2xrOwo+ICsKPiArCS8qIGNhbGN1bGF0ZSBjbGtyYXRl ICovCgphbmQgdGhpcy4gVXAgdG8geW91LgoKPiArCWlmICghaXNfZnJhYykKPiArCQljbGtyYXRl ID0gQ0xLX0lOVDsKPiArCWVsc2UKPiArCQljbGtyYXRlID0gKENMS19JTlQgKiAxMDAwKSAvIDEw MDE7Cj4gKwo+ICsJcmV0ID0gY2xrX3NldF9yYXRlKGd0Y2xrLCBjbGtyYXRlKTsKPiArCWlmIChy ZXQpCj4gKwkJZGV2X2VycihzdGF0ZS0+ZGV2LCAiZmFpbGVkIHRvIHNldCBjbGsgcmF0ZSA9ICVk XG4iLCByZXQpOwo+ICsKPiArCXN0YXRlLT5wcmV2X2lzX2ZyYWMgPSBpc19mcmFjOwo+ICsJY2xr cmF0ZSA9IGNsa19nZXRfcmF0ZShndGNsayk7CgpTaG91bGRuJ3QgdGhlIHJldHVybmVkIHJhdGUg YmUgY2hlY2tlZCBhbmQgd2FybiBpZiBkaWZmIGlzIHRvbyBtdWNoPyBBYm92ZQpjaGFuZ2VzIHRo ZSByYXRlIGJ5IDAuMSUgd2hpY2ggbWVhbnMgdGhlIHJhdGUgc2hvdWxkIGJlIHF1aXRlIHByZWNp c2UuIFNvIGl0CmJldHRlciBiZSBjaGVja2VkLgoKPiArCj4gKwlkZXZfZGJnKHN0YXRlLT5kZXYs ICJjbGtyYXRlID0gJWx1IGlzX2ZyYWMgPSAlZFxuIiwKPiArCQljbGtyYXRlLCBpc19mcmFjKTsK PiArCj4gKwlpZiAoc3RhdGUtPmZyYW1lcl9lbmFibGUpIHsKPiArCQl4c2Rpcnhzc19zZXQoc3Rh dGUsIFhTRElSWF9NRExfQ1RSTF9SRUcsCj4gKwkJCSAgICAgWFNESVJYX01ETF9DVFJMX0ZSTV9F Tl9NQVNLKTsKPiArCX0gZWxzZSB7Cj4gKwkJeHNkaXJ4c3NfY2xyKHN0YXRlLCBYU0RJUlhfTURM X0NUUkxfUkVHLAo+ICsJCQkgICAgIFhTRElSWF9NRExfQ1RSTF9GUk1fRU5fTUFTSyk7Cj4gKwl9 Cj4gKwl4c2Rpcnhzc193cml0ZShzdGF0ZSwgWFNESVJYX0VESF9FUlJDTlRfRU5fUkVHLAo+ICsJ CSAgICAgICBzdGF0ZS0+ZWRobWFzayAmIFhTRElSWF9FREhfQUxMRVJSX01BU0spOwo+ICsJeHNk aXJ4c3Nfd3JpdGUoc3RhdGUsIFhTRElSWF9WSURfTE9DS19XSU5ET1dfUkVHLCBzdGF0ZS0+dmlk bG9ja2VkKTsKPiArCXhzZGlyeF9zZXRfbW9kZWRldGVjdChzdGF0ZSwgc3RhdGUtPnNlYXJjaG1h c2spOwo+ICsJWFNESVJYX0NPUkVfRU5BQkxFKHN0YXRlKTsKPiArCXhzZGlyeHNzX3NldChzdGF0 ZSwgWFNESVJYX0lFUl9SRUcsIFhTRElSWF9JTlRSX0FMTF9NQVNLKTsKPiArCVhTRElSWF9HTE9C QUxfSU5UUl9FTkFCTEUoc3RhdGUpOwo+ICt9Cj4gKwo+ICsvKioKPiArICogeHNkaXJ4X2dldF9z dHJlYW1fcHJvcGVydGllcyAtIEdldCBTREkgUnggc3RyZWFtIHByb3BlcnRpZXMKPiArICogQHN0 YXRlOiBwb2ludGVyIHRvIGRyaXZlciBzdGF0ZQo+ICsgKgo+ICsgKiBUaGlzIGZ1bmN0aW9uIGRl Y29kZXMgdGhlIHN0cmVhbSdzIFNUMzUyIHBheWxvYWQgKGlmIGF2YWlsYWJsZSkgdG8gZ2V0Cj4g KyAqIHN0cmVhbSBwcm9wZXJ0aWVzIGxpa2Ugd2lkdGgsIGhlaWdodCwgcGljdHVyZSB0eXBlIChp bnRlcmxhY2VkL3Byb2dyZXNzaXZlKSwKPiArICogZXRjLgo+ICsgKgo+ICsgKiBSZXR1cm46IDAg Zm9yIHN1Y2Nlc3MgZWxzZSBlcnJvcnMKPiArICovCj4gK3N0YXRpYyBpbnQgeHNkaXJ4X2dldF9z dHJlYW1fcHJvcGVydGllcyhzdHJ1Y3QgeHNkaXJ4c3Nfc3RhdGUgKnN0YXRlKQo+ICt7Cj4gKwlz dHJ1Y3QgZGV2aWNlICpkZXYgPSBzdGF0ZS0+ZGV2Owo+ICsJdTMyIG1vZGUsIHBheWxvYWQgPSAw LCB2YWwsIGZhbWlseSwgdmFsaWQsIHRzY2FuOwo+ICsJdTggYnl0ZTEgPSAwLCBhY3RpdmVfbHVt YSA9IDAsIHBpY190eXBlID0gMCwgZnJhbWVyYXRlID0gMDsKPiArCXU4IHNhbXBsaW5nID0gWFNU MzUyX0JZVEUzX0NPTE9SX0ZPUk1BVF80MjI7Cj4gKwlzdHJ1Y3QgdjRsMl9tYnVzX2ZyYW1lZm10 ICpmb3JtYXQgPSAmc3RhdGUtPmZvcm1hdDsKPiArCXUzMiBicGMgPSBYU1QzNTJfQllURTRfQklU X0RFUFRIXzEwOwo+ICsJdTMyIGNvbG9yaW1ldHJ5ID0gWFNUMzUyX0JZVEUzX0NPTE9SSU1FVFJZ X0JUNzA5Owo+ICsKPiArCW1vZGUgPSB4c2Rpcnhzc19yZWFkKHN0YXRlLCBYU0RJUlhfTU9ERV9E RVRfU1RBVF9SRUcpOwo+ICsJbW9kZSAmPSBYU0RJUlhfTU9ERV9ERVRfU1RBVF9SWF9NT0RFX01B U0s7Cj4gKwo+ICsJdmFsaWQgPSB4c2Rpcnhzc19yZWFkKHN0YXRlLCBYU0RJUlhfU1QzNTJfVkFM SURfUkVHKTsKPiArCj4gKwlpZiAobW9kZSA+PSBYU0RJUlhfTU9ERV8zR19NQVNLICYmICF2YWxp ZCkgewo+ICsJCWRldl9lcnIoZGV2LCAiTm8gdmFsaWQgU1QzNTIgcGF5bG9hZCBwcmVzZW50IGV2 ZW4gZm9yIDNHIG1vZGUgYW5kIGFib3ZlXG4iKTsKPiArCQlyZXR1cm4gLUVJTlZBTDsKPiArCX0K PiArCj4gKwl2YWwgPSB4c2Rpcnhzc19yZWFkKHN0YXRlLCBYU0RJUlhfVFNfREVUX1NUQVRfUkVH KTsKPiArCWlmICh2YWxpZCAmIFhTRElSWF9TVDM1Ml9WQUxJRF9EUzFfTUFTSykgewo+ICsJCXBh eWxvYWQgPSB4c2Rpcnhzc19yZWFkKHN0YXRlLCBYU0RJUlhfU1QzNTJfRFMxX1JFRyk7Cj4gKwkJ Ynl0ZTEgPSBGSUVMRF9HRVQoWFNUMzUyX1BBWUxPQURfQllURTFfTUFTSywgcGF5bG9hZCk7Cj4g KwkJYWN0aXZlX2x1bWEgPSBGSUVMRF9HRVQoWFNUMzUyX0JZVEUzX0FDVF9MVU1BX0NPVU5UX01B U0ssCj4gKwkJCQkJcGF5bG9hZCk7Cj4gKwkJcGljX3R5cGUgPSBGSUVMRF9HRVQoWFNUMzUyX0JZ VEUyX1BJQ19UWVBFX01BU0ssIHBheWxvYWQpOwo+ICsJCWZyYW1lcmF0ZSA9IEZJRUxEX0dFVChY U1QzNTJfQllURTJfRlBTX01BU0ssIHBheWxvYWQpOwo+ICsJCXRzY2FuID0gRklFTERfR0VUKFhT VDM1Ml9CWVRFMl9UU19UWVBFX01BU0ssIHBheWxvYWQpOwo+ICsJCXNhbXBsaW5nID0gRklFTERf R0VUKFhTVDM1Ml9CWVRFM19DT0xPUl9GT1JNQVRfTUFTSywgcGF5bG9hZCk7Cj4gKwkJYnBjID0g RklFTERfR0VUKFhTVDM1Ml9CWVRFNF9CSVRfREVQVEhfTUFTSywgcGF5bG9hZCk7Cj4gKwkJY29s b3JpbWV0cnkgPSBGSUVMRF9HRVQoWFNUMzUyX0JZVEUzX0NPTE9SSU1FVFJZX01BU0ssIHBheWxv YWQpOwo+ICsJfSBlbHNlIHsKPiArCQlkZXZfZGJnKGRldiwgIk5vIFNUMzUyIHBheWxvYWQgYXZh aWxhYmxlIDogTW9kZSA9ICVkXG4iLCBtb2RlKTsKPiArCQlmcmFtZXJhdGUgPSBGSUVMRF9HRVQo WFNESVJYX1RTX0RFVF9TVEFUX1JBVEVfTUFTSywgdmFsKTsKPiArCQl0c2NhbiA9IEZJRUxEX0dF VChYU0RJUlhfVFNfREVUX1NUQVRfU0NBTl9NQVNLLCB2YWwpOwo+ICsJfQo+ICsKPiArCWlmICgo YnBjID09IFhTVDM1Ml9CWVRFNF9CSVRfREVQVEhfMTAgJiYgc3RhdGUtPmJwYyAhPSAxMCkgfHwK PiArCSAgICAoYnBjID09IFhTVDM1Ml9CWVRFNF9CSVRfREVQVEhfMTIgJiYgc3RhdGUtPmJwYyAh PSAxMikpIHsKPiArCQlkZXZfZGJnKGRldiwgIkJpdCBkZXB0aCBub3Qgc3VwcG9ydGVkLiBicGMg PSAlZCBzdGF0ZS0+YnBjID0gJWRcbiIsCj4gKwkJCWJwYywgc3RhdGUtPmJwYyk7Cj4gKwkJcmV0 dXJuIC1FSU5WQUw7Cj4gKwl9Cj4gKwo+ICsJZmFtaWx5ID0gRklFTERfR0VUKFhTRElSWF9UU19E RVRfU1RBVF9GQU1JTFlfTUFTSywgdmFsKTsKPiArCXN0YXRlLT50c19pc19pbnRlcmxhY2VkID0g dHNjYW4gPyBmYWxzZSA6IHRydWU7Cj4gKwo+ICsJZGV2X2RiZyhkZXYsICJ0c19pc19pbnRlcmxh Y2VkID0gJWQsIGZhbWlseSA9ICVkXG4iLAo+ICsJCXN0YXRlLT50c19pc19pbnRlcmxhY2VkLCBm YW1pbHkpOwo+ICsKPiArCXN3aXRjaCAobW9kZSkgewo+ICsJY2FzZSBYU0RJUlhfTU9ERV9IRF9N QVNLOgo+ICsJCWlmICghdmFsaWQpIHsKPiArCQkJLyogTm8gcGF5bG9hZCBvYnRhaW5lZCAqLwo+ ICsJCQlkZXZfZGJnKGRldiwgImZyYW1lIHJhdGUgOiAlZCwgdHNjYW4gPSAlZFxuIiwKPiArCQkJ CWZyYW1lcmF0ZSwgdHNjYW4pOwo+ICsJCQkvKgo+ICsJCQkgKiBOT1RFIDogQSBwcm9ncmVzc2l2 ZSBzZWdtZW50ZWQgZnJhbWUgcFNGIHdpbGwgYmUKPiArCQkJICogcmVwb3J0ZWQgaW5jb3JyZWN0 bHkgYXMgSW50ZXJsYWNlZCBhcyB3ZSByZWx5IG9uIElQJ3MKPiArCQkJICogdHJhbnNwb3J0IHNj YW4gbG9ja2VkIGJpdC4KPiArCQkJICovCj4gKwkJCWRldl93YXJuKGRldiwgInBTRiB3aWxsIGJl IGluY29ycmVjdGx5IHJlcG9ydGVkIGFzIEludGVybGFjZWRcbiIpOwo+ICsKPiArCQkJc3dpdGNo IChmcmFtZXJhdGUpIHsKPiArCQkJY2FzZSBYU0RJUlhfVFNfREVUX1NUQVRfUkFURV8yM185OEha Ogo+ICsJCQljYXNlIFhTRElSWF9UU19ERVRfU1RBVF9SQVRFXzI0SFo6Cj4gKwkJCWNhc2UgWFNE SVJYX1RTX0RFVF9TVEFUX1JBVEVfMjVIWjoKPiArCQkJY2FzZSBYU0RJUlhfVFNfREVUX1NUQVRf UkFURV8yOV85N0haOgo+ICsJCQljYXNlIFhTRElSWF9UU19ERVRfU1RBVF9SQVRFXzMwSFo6Cj4g KwkJCQlpZiAoZmFtaWx5ID09IFhTRElSWF9TTVBURV9TVF8yOTYpIHsKPiArCQkJCQlmb3JtYXQt PndpZHRoID0gMTI4MDsKPiArCQkJCQlmb3JtYXQtPmhlaWdodCA9IDcyMDsKPiArCQkJCQlmb3Jt YXQtPmZpZWxkID0gVjRMMl9GSUVMRF9OT05FOwo+ICsJCQkJfSBlbHNlIGlmIChmYW1pbHkgPT0g WFNESVJYX1NNUFRFX1NUXzIwNDhfMikgewo+ICsJCQkJCWZvcm1hdC0+d2lkdGggPSAyMDQ4Owo+ ICsJCQkJCWZvcm1hdC0+aGVpZ2h0ID0gMTA4MDsKPiArCQkJCQlpZiAodHNjYW4pCj4gKwkJCQkJ CWZvcm1hdC0+ZmllbGQgPSBWNEwyX0ZJRUxEX05PTkU7Cj4gKwkJCQkJZWxzZQo+ICsJCQkJCQlm b3JtYXQtPmZpZWxkID0KPiArCQkJCQkJCVY0TDJfRklFTERfQUxURVJOQVRFOwo+ICsJCQkJfSBl bHNlIHsKPiArCQkJCQlmb3JtYXQtPndpZHRoID0gMTkyMDsKPiArCQkJCQlmb3JtYXQtPmhlaWdo dCA9IDEwODA7Cj4gKwkJCQkJaWYgKHRzY2FuKQo+ICsJCQkJCQlmb3JtYXQtPmZpZWxkID0gVjRM Ml9GSUVMRF9OT05FOwo+ICsJCQkJCWVsc2UKPiArCQkJCQkJZm9ybWF0LT5maWVsZCA9Cj4gKwkJ CQkJCQlWNEwyX0ZJRUxEX0FMVEVSTkFURTsKPiArCQkJCX0KPiArCQkJCWJyZWFrOwo+ICsJCQlj YXNlIFhTRElSWF9UU19ERVRfU1RBVF9SQVRFXzUwSFo6Cj4gKwkJCWNhc2UgWFNESVJYX1RTX0RF VF9TVEFUX1JBVEVfNTlfOTRIWjoKPiArCQkJY2FzZSBYU0RJUlhfVFNfREVUX1NUQVRfUkFURV82 MEhaOgo+ICsJCQkJaWYgKGZhbWlseSA9PSBYU0RJUlhfU01QVEVfU1RfMjc0KSB7Cj4gKwkJCQkJ Zm9ybWF0LT53aWR0aCA9IDE5MjA7Cj4gKwkJCQkJZm9ybWF0LT5oZWlnaHQgPSAxMDgwOwo+ICsJ CQkJfSBlbHNlIHsKPiArCQkJCQlmb3JtYXQtPndpZHRoID0gMTI4MDsKPiArCQkJCQlmb3JtYXQt PmhlaWdodCA9IDcyMDsKPiArCQkJCX0KPiArCQkJCWZvcm1hdC0+ZmllbGQgPSBWNEwyX0ZJRUxE X05PTkU7Cj4gKwkJCQlicmVhazsKPiArCQkJZGVmYXVsdDoKPiArCQkJCWZvcm1hdC0+d2lkdGgg PSAxOTIwOwo+ICsJCQkJZm9ybWF0LT5oZWlnaHQgPSAxMDgwOwo+ICsJCQkJZm9ybWF0LT5maWVs ZCA9IFY0TDJfRklFTERfTk9ORTsKPiArCQkJfQo+ICsJCX0gZWxzZSB7Cj4gKwkJCWRldl9kYmco ZGV2LCAiR290IHRoZSBwYXlsb2FkXG4iKTsKPiArCQkJc3dpdGNoIChieXRlMSkgewo+ICsJCQlj YXNlIFhTVDM1Ml9CWVRFMV9TVDI5Ml8xeDcyMExfMV81RzoKPiArCQkJCS8qIFNNUFRFIFNUIDI5 Mi0xIGZvciA3MjAgbGluZSBwYXlsb2FkcyAqLwo+ICsJCQkJZm9ybWF0LT53aWR0aCA9IDEyODA7 Cj4gKwkJCQlmb3JtYXQtPmhlaWdodCA9IDcyMDsKPiArCQkJCWJyZWFrOwo+ICsJCQljYXNlIFhT VDM1Ml9CWVRFMV9TVDI5Ml8xeDEwODBMXzFfNUc6Cj4gKwkJCQkvKiBTTVBURSBTVCAyOTItMSBm b3IgMTA4MCBsaW5lIHBheWxvYWRzICovCj4gKwkJCQlmb3JtYXQtPmhlaWdodCA9IDEwODA7Cj4g KwkJCQlpZiAoYWN0aXZlX2x1bWEpCj4gKwkJCQkJZm9ybWF0LT53aWR0aCA9IDIwNDg7Cj4gKwkJ CQllbHNlCj4gKwkJCQkJZm9ybWF0LT53aWR0aCA9IDE5MjA7Cj4gKwkJCQlicmVhazsKPiArCQkJ ZGVmYXVsdDoKPiArCQkJCWRldl9kYmcoZGV2LCAiVW5rbm93biBIRCBNb2RlIFNNUFRFIHN0YW5k YXJkXG4iKTsKPiArCQkJCXJldHVybiAtRUlOVkFMOwo+ICsJCQl9Cj4gKwkJfQo+ICsJCWJyZWFr Owo+ICsJY2FzZSBYU0RJUlhfTU9ERV9TRF9NQVNLOgo+ICsJCWZvcm1hdC0+ZmllbGQgPSBWNEwy X0ZJRUxEX0FMVEVSTkFURTsKPiArCj4gKwkJc3dpdGNoIChmYW1pbHkpIHsKPiArCQljYXNlIFhT RElSWF9OVFNDOgo+ICsJCQlmb3JtYXQtPndpZHRoID0gNzIwOwo+ICsJCQlmb3JtYXQtPmhlaWdo dCA9IDQ4NjsKPiArCQkJYnJlYWs7Cj4gKwkJY2FzZSBYU0RJUlhfUEFMOgo+ICsJCQlmb3JtYXQt PndpZHRoID0gNzIwOwo+ICsJCQlmb3JtYXQtPmhlaWdodCA9IDU3NjsKPiArCQkJYnJlYWs7Cj4g KwkJZGVmYXVsdDoKPiArCQkJZGV2X2RiZyhkZXYsICJVbmtub3duIFNEIE1vZGUgU01QVEUgc3Rh bmRhcmRcbiIpOwo+ICsJCQlyZXR1cm4gLUVJTlZBTDsKPiArCQl9Cj4gKwkJYnJlYWs7Cj4gKwlj YXNlIFhTRElSWF9NT0RFXzNHX01BU0s6Cj4gKwkJc3dpdGNoIChieXRlMSkgewo+ICsJCWNhc2Ug WFNUMzUyX0JZVEUxX1NUNDI1XzIwMDhfNzUwTF8zR0I6Cj4gKwkJCS8qIFNlYyA0LjEuNi4xIFNN UFRFIDQyNS0yMDA4ICovCj4gKwkJY2FzZSBYU1QzNTJfQllURTFfU1QzNzJfMng3MjBMXzNHQjoK PiArCQkJLyogVGFibGUgMTMgU01QVEUgNDI1LTIwMDggKi8KPiArCQkJZm9ybWF0LT53aWR0aCA9 IDEyODA7Cj4gKwkJCWZvcm1hdC0+aGVpZ2h0ID0gNzIwOwo+ICsJCQlicmVhazsKPiArCQljYXNl IFhTVDM1Ml9CWVRFMV9TVDQyNV8yMDA4XzExMjVMXzNHQToKPiArCQkJLyogU1QzNTIgVGFibGUg U01QVEUgNDI1LTEgKi8KPiArCQljYXNlIFhTVDM1Ml9CWVRFMV9TVDM3Ml9ETF8zR0I6Cj4gKwkJ CS8qIFRhYmxlIDEzIFNNUFRFIDQyNS0yMDA4ICovCj4gKwkJY2FzZSBYU1QzNTJfQllURTFfU1Qz NzJfMngxMDgwTF8zR0I6Cj4gKwkJCS8qIFRhYmxlIDEzIFNNUFRFIDQyNS0yMDA4ICovCj4gKwkJ CWZvcm1hdC0+aGVpZ2h0ID0gMTA4MDsKPiArCQkJaWYgKGFjdGl2ZV9sdW1hKQo+ICsJCQkJZm9y bWF0LT53aWR0aCA9IDIwNDg7Cj4gKwkJCWVsc2UKPiArCQkJCWZvcm1hdC0+d2lkdGggPSAxOTIw Owo+ICsJCQlicmVhazsKPiArCQlkZWZhdWx0Ogo+ICsJCQlkZXZfZGJnKGRldiwgIlVua25vd24g M0cgTW9kZSBTTVBURSBzdGFuZGFyZFxuIik7Cj4gKwkJCXJldHVybiAtRUlOVkFMOwo+ICsJCX0K PiArCQlicmVhazsKPiArCWNhc2UgWFNESVJYX01PREVfNkdfTUFTSzoKPiArCQlzd2l0Y2ggKGJ5 dGUxKSB7Cj4gKwkJY2FzZSBYU1QzNTJfQllURTFfU1QyMDgxXzEwX0RMXzIxNjBMXzZHOgo+ICsJ CQkvKiBEdWFsIGxpbmsgNkcgKi8KPiArCQljYXNlIFhTVDM1Ml9CWVRFMV9TVDIwODFfMTBfMjE2 MExfNkc6Cj4gKwkJCS8qIFRhYmxlIDMgU01QVEUgU1QgMjA4MS0xMCAqLwo+ICsJCQlmb3JtYXQt PmhlaWdodCA9IDIxNjA7Cj4gKwkJCWlmIChhY3RpdmVfbHVtYSkKPiArCQkJCWZvcm1hdC0+d2lk dGggPSA0MDk2Owo+ICsJCQllbHNlCj4gKwkJCQlmb3JtYXQtPndpZHRoID0gMzg0MDsKPiArCQkJ YnJlYWs7Cj4gKwkJY2FzZSBYU1QzNTJfQllURTFfU1QyMDgxXzEwXzJfMTA4MExfNkc6Cj4gKwkJ CWZvcm1hdC0+aGVpZ2h0ID0gMTA4MDsKPiArCQkJaWYgKGFjdGl2ZV9sdW1hKQo+ICsJCQkJZm9y bWF0LT53aWR0aCA9IDIwNDg7Cj4gKwkJCWVsc2UKPiArCQkJCWZvcm1hdC0+d2lkdGggPSAxOTIw Owo+ICsJCQlicmVhazsKPiArCQlkZWZhdWx0Ogo+ICsJCQlkZXZfZGJnKGRldiwgIlVua25vd24g NkcgTW9kZSBTTVBURSBzdGFuZGFyZFxuIik7Cj4gKwkJCXJldHVybiAtRUlOVkFMOwo+ICsJCX0K PiArCQlicmVhazsKPiArCWNhc2UgWFNESVJYX01PREVfMTJHSV9NQVNLOgo+ICsJY2FzZSBYU0RJ UlhfTU9ERV8xMkdGX01BU0s6Cj4gKwkJc3dpdGNoIChieXRlMSkgewo+ICsJCWNhc2UgWFNUMzUy X0JZVEUxX1NUMjA4Ml8xMF8yMTYwTF8xMkc6Cj4gKwkJCS8qIFNlY3Rpb24gNC4zLjEgU01QVEUg U1QgMjA4Mi0xMCAqLwo+ICsJCQlmb3JtYXQtPmhlaWdodCA9IDIxNjA7Cj4gKwkJCWlmIChhY3Rp dmVfbHVtYSkKPiArCQkJCWZvcm1hdC0+d2lkdGggPSA0MDk2Owo+ICsJCQllbHNlCj4gKwkJCQlm b3JtYXQtPndpZHRoID0gMzg0MDsKPiArCQkJYnJlYWs7Cj4gKwkJZGVmYXVsdDoKPiArCQkJZGV2 X2RiZyhkZXYsICJVbmtub3duIDEyRyBNb2RlIFNNUFRFIHN0YW5kYXJkXG4iKTsKPiArCQkJcmV0 dXJuIC1FSU5WQUw7Cj4gKwkJfQo+ICsJCWJyZWFrOwo+ICsJZGVmYXVsdDoKPiArCQlkZXZfZXJy KGRldiwgIkludmFsaWQgTW9kZVxuIik7Cj4gKwkJcmV0dXJuIC1FSU5WQUw7Cj4gKwl9Cj4gKwo+ ICsJaWYgKHZhbGlkKSB7Cj4gKwkJaWYgKHBpY190eXBlKQo+ICsJCQlmb3JtYXQtPmZpZWxkID0g VjRMMl9GSUVMRF9OT05FOwo+ICsJCWVsc2UKPiArCQkJZm9ybWF0LT5maWVsZCA9IFY0TDJfRklF TERfQUxURVJOQVRFOwo+ICsKPiArCQlpZiAoZm9ybWF0LT5oZWlnaHQgPT0gMTA4MCAmJiBwaWNf dHlwZSAmJiAhdHNjYW4pCj4gKwkJCWZvcm1hdC0+ZmllbGQgPSBWNEwyX0ZJRUxEX0FMVEVSTkFU RTsKPiArCj4gKwkJLyoKPiArCQkgKiBJbiAzR0IgREwgcFNGIG1vZGUgdGhlIHZpZGVvIGlzIHNp bWlsYXIgdG8gaW50ZXJsYWNlZC4KPiArCQkgKiBTbyB0aG91Z2ggaXQgaXMgYSBwcm9ncmVzc2l2 ZSB2aWRlbywgaXRzIHRyYW5zcG9ydCBpcwo+ICsJCSAqIGludGVybGFjZWQgYW5kIGlzIHNlbnQg YXMgdHdvIHdpZHRoIHggKGhlaWdodC8yKSBidWZmZXJzLgo+ICsJCSAqLwo+ICsJCWlmIChieXRl MSA9PSBYU1QzNTJfQllURTFfU1QzNzJfRExfM0dCKSB7Cj4gKwkJCWlmIChzdGF0ZS0+dHNfaXNf aW50ZXJsYWNlZCkKPiArCQkJCWZvcm1hdC0+ZmllbGQgPSBWNEwyX0ZJRUxEX0FMVEVSTkFURTsK PiArCQkJZWxzZQo+ICsJCQkJZm9ybWF0LT5maWVsZCA9IFY0TDJfRklFTERfTk9ORTsKPiArCQl9 Cj4gKwl9Cj4gKwo+ICsJaWYgKGZvcm1hdC0+ZmllbGQgPT0gVjRMMl9GSUVMRF9BTFRFUk5BVEUp Cj4gKwkJZm9ybWF0LT5oZWlnaHQgPSBmb3JtYXQtPmhlaWdodCAvIDI7Cj4gKwo+ICsJc3dpdGNo IChzYW1wbGluZykgewo+ICsJY2FzZSBYU1QzNTJfQllURTNfQ09MT1JfRk9STUFUXzQyMjoKPiAr CQlpZiAoc3RhdGUtPmJwYyA9PSAxMCkKPiArCQkJZm9ybWF0LT5jb2RlID0gTUVESUFfQlVTX0ZN VF9VWVZZMTBfMVgyMDsKPiArCQllbHNlCj4gKwkJCWZvcm1hdC0+Y29kZSA9IE1FRElBX0JVU19G TVRfVVlWWTEyXzFYMjQ7Cj4gKwkJYnJlYWs7Cj4gKwljYXNlIFhTVDM1Ml9CWVRFM19DT0xPUl9G T1JNQVRfNDIwOgo+ICsJY2FzZSBYU1QzNTJfQllURTNfQ09MT1JfRk9STUFUX1lVVjQ0NDoKPiAr CWNhc2UgWFNUMzUyX0JZVEUzX0NPTE9SX0ZPUk1BVF9HQlI6Cj4gKwkJZm9ybWF0LT5jb2RlID0g MDsKPiArCQlkZXZfZGJnKGRldiwgIk5vIGNvcnJlc3BvbmRpbmcgbWVkaWEgYnVzIGZvcm1hdHNc biIpOwo+ICsJCWJyZWFrOwo+ICsJZGVmYXVsdDoKPiArCQlkZXZfZXJyKGRldiwgIlVuc3VwcG9y dGVkIGNvbG9yIGZvcm1hdCA6ICVkXG4iLCBzYW1wbGluZyk7Cj4gKwkJcmV0dXJuIC1FSU5WQUw7 Cj4gKwl9Cj4gKwo+ICsJLyogUmVmZXIgVGFibGUgMyBTTVBURSBTVCAyMDgxLTEwOjIwMTggKi8K PiArCXN3aXRjaCAoY29sb3JpbWV0cnkpIHsKPiArCWNhc2UgWFNUMzUyX0JZVEUzX0NPTE9SSU1F VFJZX0JUNzA5Ogo+ICsJCWZvcm1hdC0+Y29sb3JzcGFjZSA9IFY0TDJfQ09MT1JTUEFDRV9SRUM3 MDk7Cj4gKwkJYnJlYWs7Cj4gKwkvKiBXaGVuIEhEUiBzdXBwb3J0IGlzIGFkZGVkIFVIRFRWIHdp bGwgaGF2ZSBCVDIwMjAgY29sb3JzcGFjZSAqLwo+ICsJY2FzZSBYU1QzNTJfQllURTNfQ09MT1JJ TUVUUllfVUhEVFY6Cj4gKwljYXNlIFhTVDM1Ml9CWVRFM19DT0xPUklNRVRSWV9DT0xPUl9WQU5D Ogo+ICsJY2FzZSBYU1QzNTJfQllURTNfQ09MT1JJTUVUUllfVU5LTk9XTjoKPiArCWRlZmF1bHQ6 Cj4gKwkJZGV2X2VycihkZXYsICJVbmtub3duIGNvbG9yaW1ldHJ5IDogJWRcbiIsIGNvbG9yaW1l dHJ5KTsKPiArCQlyZXR1cm4gLUVJTlZBTDsKPiArCX0KPiArCj4gKwl4c2Rpcnhzc19nZXRfZnJh bWVyYXRlKCZzdGF0ZS0+ZnJhbWVfaW50ZXJ2YWwsIGZyYW1lcmF0ZSk7Cj4gKwo+ICsJZGV2X2Ri ZyhkZXYsICJTdHJlYW0gd2lkdGggPSAlZCBoZWlnaHQgPSAlZCBGaWVsZCA9ICVkIHBheWxvYWQg PSAweCUwOHggdHMgPSAweCUwOHhcbiIsCj4gKwkJZm9ybWF0LT53aWR0aCwgZm9ybWF0LT5oZWln aHQsIGZvcm1hdC0+ZmllbGQsIHBheWxvYWQsIHZhbCk7Cj4gKwlkZXZfZGJnKGRldiwgImZyYW1l IHJhdGUgbnVtZXJhdG9yID0gJWQgZGVub21pbmF0b3IgPSAlZFxuIiwKPiArCQlzdGF0ZS0+ZnJh bWVfaW50ZXJ2YWwubnVtZXJhdG9yLAo+ICsJCXN0YXRlLT5mcmFtZV9pbnRlcnZhbC5kZW5vbWlu YXRvcik7Cj4gKwlkZXZfZGJnKGRldiwgIlN0cmVhbSBjb2RlID0gMHgleFxuIiwgZm9ybWF0LT5j b2RlKTsKPiArCXJldHVybiAwOwo+ICt9Cj4gKwo+ICsvKioKPiArICogeHNkaXJ4c3NfaXJxX2hh bmRsZXIgLSBJbnRlcnJ1cHQgaGFuZGxlciBmb3IgU0RJIFJ4Cj4gKyAqIEBpcnE6IElSUSBudW1i ZXIKPiArICogQGRldl9pZDogUG9pbnRlciB0byBkZXZpY2Ugc3RhdGUKPiArICoKPiArICogVGhl IFNESSBSeCBpbnRlcnJ1cHRzIGFyZSBjbGVhcmVkIGJ5IHdyaXRpbmcgMSB0byBjb3JyZXNwb25k aW5nIGJpdC4KPiArICoKPiArICogUmV0dXJuOiBJUlFfSEFORExFRCBhZnRlciBoYW5kbGluZyBp bnRlcnJ1cHRzCj4gKyAqLwo+ICtzdGF0aWMgaXJxcmV0dXJuX3QgeHNkaXJ4c3NfaXJxX2hhbmRs ZXIoaW50IGlycSwgdm9pZCAqZGV2X2lkKQo+ICt7Cj4gKwlzdHJ1Y3QgeHNkaXJ4c3Nfc3RhdGUg KnN0YXRlID0gKHN0cnVjdCB4c2Rpcnhzc19zdGF0ZSAqKWRldl9pZDsKPiArCXN0cnVjdCBkZXZp Y2UgKmRldiA9IHN0YXRlLT5kZXY7Cj4gKwl1MzIgc3RhdHVzOwo+ICsKPiArCXN0YXR1cyA9IHhz ZGlyeHNzX3JlYWQoc3RhdGUsIFhTRElSWF9JU1JfUkVHKTsKPiArCXhzZGlyeHNzX3dyaXRlKHN0 YXRlLCBYU0RJUlhfSVNSX1JFRywgc3RhdHVzKTsKClRoaXMgY2FuIGJlIGRvbmUgYWZ0ZXIgY2hl Y2sgYmVsb3csIHNvIElPIGlzIHNraXBwZWQgd2hlbiBub3QgbmVlZGVkLgoKPiArCWRldl9kYmco ZGV2LCAiaW50ZXJydXB0IHN0YXR1cyA9IDB4JTA4eFxuIiwgc3RhdHVzKTsKPiArCj4gKwlpZiAo IXN0YXR1cykKPiArCQlyZXR1cm4gSVJRX05PTkU7Cj4gKwo+ICsJaWYgKHN0YXR1cyAmIFhTRElS WF9JTlRSX1ZJRExPQ0tfTUFTSyB8fAo+ICsJICAgIHN0YXR1cyAmIFhTRElSWF9JTlRSX1ZJRFVO TE9DS19NQVNLKSB7Cj4gKwkJdTMyIHZhbDEsIHZhbDI7Cj4gKwkJc3RydWN0IHY0bDJfZXZlbnQg ZXZlbnQgPSB7IDAgfTsKPiArCQl1bnNpZ25lZCBsb25nIGZsYWdzOwo+ICsKPiArCQlkZXZfZGJn KGRldiwgInZpZGVvIGxvY2svdW5sb2NrIGludGVycnVwdFxuIik7Cj4gKwo+ICsJCXNwaW5fbG9j a19pcnFzYXZlKCZzdGF0ZS0+c2xvY2ssIGZsYWdzKTsKPiArCQl4c2Rpcnhfc3RyZWFtZmxvd19j b250cm9sKHN0YXRlLCBmYWxzZSk7Cj4gKwo+ICsJCXZhbDEgPSB4c2Rpcnhzc19yZWFkKHN0YXRl LCBYU0RJUlhfTU9ERV9ERVRfU1RBVF9SRUcpOwo+ICsJCXZhbDIgPSB4c2Rpcnhzc19yZWFkKHN0 YXRlLCBYU0RJUlhfVFNfREVUX1NUQVRfUkVHKTsKPiArCj4gKwkJaWYgKCh2YWwxICYgWFNESVJY X01PREVfREVUX1NUQVRfTU9ERV9MT0NLX01BU0spICYmCj4gKwkJICAgICh2YWwyICYgWFNESVJY X1RTX0RFVF9TVEFUX0xPQ0tFRF9NQVNLKSkgewo+ICsJCQl1MzIgbWFzayA9IFhTRElSWF9SU1Rf Q1RSTF9SU1RfQ1JDX0VSUkNOVF9NQVNLIHwKPiArCQkJCSAgIFhTRElSWF9SU1RfQ1RSTF9SU1Rf RURIX0VSUkNOVF9NQVNLOwo+ICsKPiArCQkJZGV2X2RiZyhkZXYsICJ2aWRlbyBsb2NrIGludGVy cnVwdFxuIik7Cj4gKwo+ICsJCQl4c2Rpcnhzc19zZXQoc3RhdGUsIFhTRElSWF9SU1RfQ1RSTF9S RUcsIG1hc2spOwo+ICsJCQl4c2Rpcnhzc19jbHIoc3RhdGUsIFhTRElSWF9SU1RfQ1RSTF9SRUcs IG1hc2spOwo+ICsKPiArCQkJdmFsMSA9IHhzZGlyeHNzX3JlYWQoc3RhdGUsIFhTRElSWF9TVDM1 Ml9WQUxJRF9SRUcpOwo+ICsJCQl2YWwyID0geHNkaXJ4c3NfcmVhZChzdGF0ZSwgWFNESVJYX1NU MzUyX0RTMV9SRUcpOwo+ICsKPiArCQkJZGV2X2RiZyhkZXYsICJ2YWxpZCBzdDM1MiBtYXNrID0g MHglMDh4XG4iLCB2YWwxKTsKPiArCQkJZGV2X2RiZyhkZXYsICJzdDM1MiBwYXlsb2FkID0gMHgl MDh4XG4iLCB2YWwyKTsKPiArCj4gKwkJCWlmICgheHNkaXJ4X2dldF9zdHJlYW1fcHJvcGVydGll cyhzdGF0ZSkpIHsKPiArCQkJCXN0YXRlLT52aWRsb2NrZWQgPSB0cnVlOwo+ICsJCQkJeHNkaXJ4 c3Nfc2V0X2d0Y2xrKHN0YXRlKTsKPiArCQkJfSBlbHNlIHsKPiArCQkJCWRldl9lcnIoZGV2LCAi VW5hYmxlIHRvIGdldCBzdHJlYW0gcHJvcGVydGllcyFcbiIpOwo+ICsJCQkJc3RhdGUtPnZpZGxv Y2tlZCA9IGZhbHNlOwo+ICsJCQl9Cj4gKwkJfSBlbHNlIHsKPiArCQkJZGV2X2RiZyhkZXYsICJ2 aWRlbyB1bmxvY2sgaW50ZXJydXB0XG4iKTsKPiArCQkJc3RhdGUtPnZpZGxvY2tlZCA9IGZhbHNl Owo+ICsJCX0KPiArCQlzcGluX3VubG9ja19pcnFyZXN0b3JlKCZzdGF0ZS0+c2xvY2ssIGZsYWdz KTsKPiArCj4gKwkJZXZlbnQudHlwZSA9IFY0TDJfRVZFTlRfU09VUkNFX0NIQU5HRTsKPiArCQll dmVudC51LnNyY19jaGFuZ2UuY2hhbmdlcyA9IFY0TDJfRVZFTlRfU1JDX0NIX1JFU09MVVRJT047 Cj4gKwkJdjRsMl9zdWJkZXZfbm90aWZ5X2V2ZW50KCZzdGF0ZS0+c3ViZGV2LCAmZXZlbnQpOwo+ ICsJfQo+ICsKPiArCWlmIChzdGF0dXMgJiAoWFNESVJYX0lOVFJfVU5ERVJGTE9XX01BU0sgfCBY U0RJUlhfSU5UUl9PVkVSRkxPV19NQVNLKSkgewo+ICsJCXN0cnVjdCB2NGwyX2V2ZW50IGV2ZW50 ID0geyAwIH07Cj4gKwo+ICsJCWRldl9kYmcoZGV2LCAiVmlkZW8gaW4gdG8gQVhJNCBTdHJlYW0g Y29yZSB1bmRlci9vdmVyZmxvdyBpbnRlcnJ1cHRcbiIpOwo+ICsKPiArCQlldmVudC50eXBlID0g VjRMMl9FVkVOVF9YSUxJTlhfU0RJUlhfVU5EX09WUl9GTE9XOwo+ICsJCWlmIChzdGF0dXMgJiBY U0RJUlhfSU5UUl9VTkRFUkZMT1dfTUFTSykKPiArCQkJZXZlbnQudS5kYXRhWzBdID0gWElMSU5Y X1NESVJYX1VOREVSRkxPV19FVkVOVDsKPiArCQlpZiAoc3RhdHVzICYgWFNESVJYX0lOVFJfT1ZF UkZMT1dfTUFTSykKPiArCQkJZXZlbnQudS5kYXRhWzBdID0gWElMSU5YX1NESVJYX09WRVJGTE9X X0VWRU5UOwoKU2hvdWxkIGJlIE9SZWQ/Cgo+ICsKPiArCQl2NGwyX3N1YmRldl9ub3RpZnlfZXZl bnQoJnN0YXRlLT5zdWJkZXYsICZldmVudCk7Cj4gKwl9Cj4gKwlyZXR1cm4gSVJRX0hBTkRMRUQ7 Cj4gK30KPiArCj4gKy8qKgo+ICsgKiB4c2Rpcnhzc19zdWJzY3JpYmVfZXZlbnQgLSBTdWJzY3Jp YmUgdG8gdmlkZW8gbG9jayBhbmQgdW5sb2NrIGV2ZW50Cj4gKyAqIEBzZDogVjRMMiBTdWIgZGV2 aWNlCj4gKyAqIEBmaDogVjRMMiBGaWxlIEhhbmRsZQo+ICsgKiBAc3ViOiBTdWJjcmliZSBldmVu dCBzdHJ1Y3R1cmUKPiArICoKPiArICogUmV0dXJuOiAwIG9uIHN1Y2Nlc3MsIGVycm9ycyBvdGhl cndpc2UKPiArICovCj4gK3N0YXRpYyBpbnQgeHNkaXJ4c3Nfc3Vic2NyaWJlX2V2ZW50KHN0cnVj dCB2NGwyX3N1YmRldiAqc2QsCj4gKwkJCQkgICAgc3RydWN0IHY0bDJfZmggKmZoLAo+ICsJCQkJ ICAgIHN0cnVjdCB2NGwyX2V2ZW50X3N1YnNjcmlwdGlvbiAqc3ViKQo+ICt7Cj4gKwlpbnQgcmV0 Owo+ICsJc3RydWN0IHhzZGlyeHNzX3N0YXRlICp4c2RpcnhzcyA9IHRvX3hzZGlyeHNzc3RhdGUo c2QpOwo+ICsKPiArCWRldl9kYmcoeHNkaXJ4c3MtPmRldiwgIkV2ZW50IHN1YnNjcmliZWQgOiAw eCUwOHhcbiIsIHN1Yi0+dHlwZSk7Cj4gKwlzd2l0Y2ggKHN1Yi0+dHlwZSkgewo+ICsJY2FzZSBW NEwyX0VWRU5UX1hJTElOWF9TRElSWF9VTkRfT1ZSX0ZMT1c6Cj4gKwkJcmV0ID0gdjRsMl9ldmVu dF9zdWJzY3JpYmUoZmgsIHN1YiwgWFNESVJYX01BWF9FVkVOVFMsIE5VTEwpOwo+ICsJCWJyZWFr Owo+ICsJY2FzZSBWNEwyX0VWRU5UX1NPVVJDRV9DSEFOR0U6Cj4gKwkJcmV0ID0gdjRsMl9zcmNf Y2hhbmdlX2V2ZW50X3N1YnNjcmliZShmaCwgc3ViKTsKPiArCQlicmVhazsKPiArCWRlZmF1bHQ6 Cj4gKwkJcmV0ID0gdjRsMl9jdHJsX3N1YnNjcmliZV9ldmVudChmaCwgc3ViKTsKPiArCX0KPiAr CXJldHVybiByZXQ7Cj4gK30KPiArCj4gKy8qKgo+ICsgKiB4c2Rpcnhzc19zX2N0cmwgLSBUaGlz IGlzIHVzZWQgdG8gc2V0IHRoZSBYaWxpbnggU0RJIFJ4IFY0TDIgY29udHJvbHMKPiArICogQGN0 cmw6IFY0TDIgY29udHJvbCB0byBiZSBzZXQKPiArICoKPiArICogVGhpcyBmdW5jdGlvbiBpcyB1 c2VkIHRvIHNldCB0aGUgVjRMMiBjb250cm9scyBmb3IgdGhlIFhpbGlueCBTREkgUngKPiArICog U3Vic3lzdGVtLgo+ICsgKgo+ICsgKiBSZXR1cm46IDAgb24gc3VjY2VzcywgZXJyb3JzIG90aGVy d2lzZQo+ICsgKi8KPiArc3RhdGljIGludCB4c2Rpcnhzc19zX2N0cmwoc3RydWN0IHY0bDJfY3Ry bCAqY3RybCkKPiArewo+ICsJaW50IHJldCA9IDA7CgpObyBuZWVkIHRvIGluaXRpYWxpemUgdGhp cy4KCj4gKwlzdHJ1Y3QgeHNkaXJ4c3Nfc3RhdGUgKnhzZGlyeHNzID0KPiArCQljb250YWluZXJf b2YoY3RybC0+aGFuZGxlciwgc3RydWN0IHhzZGlyeHNzX3N0YXRlLAo+ICsJCQkgICAgIGN0cmxf aGFuZGxlcik7Cj4gKwlzdHJ1Y3QgZGV2aWNlICpkZXYgPSB4c2Rpcnhzcy0+ZGV2Owo+ICsJdW5z aWduZWQgbG9uZyBmbGFnczsKPiArCj4gKwlkZXZfZGJnKGRldiwgInNldCBjdHJsIGlkID0gMHgl MDh4IHZhbCA9IDB4JTA4eFxuIiwKPiArCQljdHJsLT5pZCwgY3RybC0+dmFsKTsKPiArCj4gKwlz cGluX2xvY2tfaXJxc2F2ZSgmeHNkaXJ4c3MtPnNsb2NrLCBmbGFncyk7Cj4gKwo+ICsJaWYgKHhz ZGlyeHNzLT5zdHJlYW1pbmcpIHsKPiArCQlzcGluX3VubG9ja19pcnFyZXN0b3JlKCZ4c2Rpcnhz cy0+c2xvY2ssIGZsYWdzKTsKPiArCQlkZXZfZXJyKGRldiwgIkNhbm5vdCBzZXQgY29udHJvbHMg d2hpbGUgc3RyZWFtaW5nXG4iKTsKPiArCQlyZXR1cm4gLUVJTlZBTDsKPiArCX0KPiArCj4gKwlY U0RJUlhfQ09SRV9ESVNBQkxFKHhzZGlyeHNzKTsKPiArCXN3aXRjaCAoY3RybC0+aWQpIHsKPiAr CWNhc2UgVjRMMl9DSURfWElMSU5YX1NESVJYX0ZSQU1FUjoKPiArCQl4c2Rpcnhzcy0+ZnJhbWVy X2VuYWJsZSA9IGN0cmwtPnZhbDsKPiArCQlpZiAoeHNkaXJ4c3MtPmZyYW1lcl9lbmFibGUpIHsK PiArCQkJeHNkaXJ4c3Nfc2V0KHhzZGlyeHNzLCBYU0RJUlhfTURMX0NUUkxfUkVHLAo+ICsJCQkJ ICAgICBYU0RJUlhfTURMX0NUUkxfRlJNX0VOX01BU0spOwo+ICsJCX0gZWxzZSB7Cj4gKwkJCXhz ZGlyeHNzX2Nscih4c2RpcnhzcywgWFNESVJYX01ETF9DVFJMX1JFRywKPiArCQkJCSAgICAgWFNE SVJYX01ETF9DVFJMX0ZSTV9FTl9NQVNLKTsKPiArCQl9Cj4gKwkJYnJlYWs7Cj4gKwljYXNlIFY0 TDJfQ0lEX1hJTElOWF9TRElSWF9WSURMT0NLX1dJTkRPVzoKPiArCQkvKgo+ICsJCSAqIFRoZSB2 aWRlbyBsb2NrIHdpbmRvdyBpcyB0aGUgYW1vdW50IG9mIHRpbWUgZm9yIHdoaWNoIHRoZQo+ICsJ CSAqIHRoZSBtb2RlIGFuZCB0cmFuc3BvcnQgc3RyZWFtIHNob3VsZCBiZSBsb2NrZWQgdG8gZ2V0 IHRoZQo+ICsJCSAqIHZpZGVvIGxvY2sgaW50ZXJydXB0Lgo+ICsJCSAqLwo+ICsJCXhzZGlyeHNz LT52aWRsb2Nrd2luID0gY3RybC0+dmFsOwo+ICsJCXhzZGlyeHNzX3dyaXRlKHhzZGlyeHNzLCBY U0RJUlhfVklEX0xPQ0tfV0lORE9XX1JFRywKPiArCQkJICAgICAgIHhzZGlyeHNzLT52aWRsb2Nr d2luKTsKPiArCQlicmVhazsKPiArCWNhc2UgVjRMMl9DSURfWElMSU5YX1NESVJYX0VESF9FUlJP Ul9TT1VSQ0VTOgo+ICsJCXhzZGlyeHNzLT5lZGhtYXNrID0gY3RybC0+dmFsICYgWFNESVJYX0VE SF9BTExFUlJfTUFTSzsKPiArCQl4c2Rpcnhzc193cml0ZSh4c2RpcnhzcywgWFNESVJYX0VESF9F UlJDTlRfRU5fUkVHLAo+ICsJCQkgICAgICAgeHNkaXJ4c3MtPmVkaG1hc2spOwo+ICsJCWJyZWFr Owo+ICsJY2FzZSBWNEwyX0NJRF9YSUxJTlhfU0RJUlhfU0VBUkNIX01PREVTOgo+ICsJCWlmICgh Y3RybC0+dmFsKSB7Cj4gKwkJCXNwaW5fdW5sb2NrX2lycXJlc3RvcmUoJnhzZGlyeHNzLT5zbG9j aywgZmxhZ3MpOwo+ICsJCQlkZXZfZXJyKGRldiwgIlNlbGVjdCBhdCBsZWFzdCBvbmUgbW9kZSFc biIpOwo+ICsJCQlyZXR1cm4gLUVJTlZBTDsKPiArCQl9Cj4gKwo+ICsJCWlmICh4c2Rpcnhzcy0+ bW9kZSA9PSBYU0RJX1NURF8zRykgewo+ICsJCQlkZXZfZGJnKGRldiwgIlVwdG8gM0cgc3VwcG9y dGVkXG4iKTsKPiArCQkJY3RybC0+dmFsICY9IH4oQklUKFhTRElSWF9NT0RFXzZHX09GRlNFVCkg fAo+ICsJCQkJICAgICAgIEJJVChYU0RJUlhfTU9ERV8xMkdJX09GRlNFVCkgfAo+ICsJCQkJICAg ICAgIEJJVChYU0RJUlhfTU9ERV8xMkdGX09GRlNFVCkpOwo+ICsJCX0KPiArCj4gKwkJaWYgKHhz ZGlyeHNzLT5tb2RlID09IFhTRElfU1REXzZHKSB7Cj4gKwkJCWRldl9kYmcoZGV2LCAiVXB0byA2 RyBzdXBwb3J0ZWRcbiIpOwo+ICsJCQljdHJsLT52YWwgJj0gfihCSVQoWFNESVJYX01PREVfMTJH SV9PRkZTRVQpIHwKPiArCQkJCSAgICAgICBCSVQoWFNESVJYX01PREVfMTJHRl9PRkZTRVQpKTsK PiArCQl9Cj4gKwo+ICsJCXJldCA9IHhzZGlyeF9zZXRfbW9kZWRldGVjdCh4c2RpcnhzcywgY3Ry bC0+dmFsKTsKPiArCQlpZiAoIXJldCkKPiArCQkJeHNkaXJ4c3MtPnNlYXJjaG1hc2sgPSBjdHJs LT52YWw7Cj4gKwkJYnJlYWs7Cj4gKwlkZWZhdWx0Ogo+ICsJCXJldCA9IC1FSU5WQUw7Cj4gKwkJ YnJlYWs7Cj4gKwl9Cj4gKwlYU0RJUlhfQ09SRV9FTkFCTEUoeHNkaXJ4c3MpOwo+ICsKPiArCXNw aW5fdW5sb2NrX2lycXJlc3RvcmUoJnhzZGlyeHNzLT5zbG9jaywgZmxhZ3MpOwo+ICsJcmV0dXJu IHJldDsKPiArfQo+ICsKPiArLyoqCj4gKyAqIHhzZGlyeHNzX2dfdm9sYXRpbGVfY3RybCAtIGdl dCB0aGUgWGlsaW54IFNESSBSeCBjb250cm9scwo+ICsgKiBAY3RybDogUG9pbnRlciB0byBWNEwy IGNvbnRyb2wKPiArICoKPiArICogUmV0dXJuOiAwIG9uIHN1Y2Nlc3MsIGVycm9ycyBvdGhlcndp c2UKPiArICovCj4gK3N0YXRpYyBpbnQgeHNkaXJ4c3NfZ192b2xhdGlsZV9jdHJsKHN0cnVjdCB2 NGwyX2N0cmwgKmN0cmwpCj4gK3sKPiArCXUzMiB2YWw7Cj4gKwlzdHJ1Y3QgeHNkaXJ4c3Nfc3Rh dGUgKnhzZGlyeHNzID0KPiArCQljb250YWluZXJfb2YoY3RybC0+aGFuZGxlciwKPiArCQkJICAg ICBzdHJ1Y3QgeHNkaXJ4c3Nfc3RhdGUsIGN0cmxfaGFuZGxlcik7Cj4gKwlzdHJ1Y3QgZGV2aWNl ICpkZXYgPSB4c2Rpcnhzcy0+ZGV2Owo+ICsJdW5zaWduZWQgbG9uZyBmbGFnczsKPiArCj4gKwlz cGluX2xvY2tfaXJxc2F2ZSgmeHNkaXJ4c3MtPnNsb2NrLCBmbGFncyk7Cj4gKwlpZiAoIXhzZGly eHNzLT52aWRsb2NrZWQpIHsKPiArCQlzcGluX3VubG9ja19pcnFyZXN0b3JlKCZ4c2Rpcnhzcy0+ c2xvY2ssIGZsYWdzKTsKPiArCQlkZXZfZXJyKGRldiwgIkNhbid0IGdldCB2YWx1ZXMgd2hlbiB2 aWRlbyBub3QgbG9ja2VkIVxuIik7Cj4gKwkJcmV0dXJuIC1FSU5WQUw7Cj4gKwl9Cj4gKwlzd2l0 Y2ggKGN0cmwtPmlkKSB7Cj4gKwljYXNlIFY0TDJfQ0lEX1hJTElOWF9TRElSWF9NT0RFX0RFVEVD VDoKPiArCQl2YWwgPSB4c2Rpcnhzc19yZWFkKHhzZGlyeHNzLCBYU0RJUlhfTU9ERV9ERVRfU1RB VF9SRUcpOwo+ICsJCXZhbCAmPSBYU0RJUlhfTU9ERV9ERVRfU1RBVF9SWF9NT0RFX01BU0s7Cj4g Kwo+ICsJCXN3aXRjaCAodmFsKSB7Cj4gKwkJY2FzZSBYU0RJUlhfTU9ERV9TRF9NQVNLOgo+ICsJ CQljdHJsLT52YWwgPSBYU0RJUlhfTU9ERV9TRF9PRkZTRVQ7Cj4gKwkJCWJyZWFrOwo+ICsJCWNh c2UgWFNESVJYX01PREVfSERfTUFTSzoKPiArCQkJY3RybC0+dmFsID0gWFNESVJYX01PREVfSERf T0ZGU0VUOwo+ICsJCQlicmVhazsKPiArCQljYXNlIFhTRElSWF9NT0RFXzNHX01BU0s6Cj4gKwkJ CXZhbCA9IHhzZGlyeHNzX3JlYWQoeHNkaXJ4c3MsIFhTRElSWF9NT0RFX0RFVF9TVEFUX1JFRyk7 Cj4gKwkJCXZhbCAmPSBYU0RJUlhfTU9ERV9ERVRfU1RBVF9MVkxCXzNHX01BU0s7Cj4gKwkJCWN0 cmwtPnZhbCA9IHZhbCA/IFhTRElSWF9NT0RFXzNHQl9PRkZTRVQgOgo+ICsJCQkJWFNESVJYX01P REVfM0dBX09GRlNFVDsKPiArCQkJYnJlYWs7Cj4gKwkJY2FzZSBYU0RJUlhfTU9ERV82R19NQVNL Ogo+ICsJCQljdHJsLT52YWwgPSBYU0RJUlhfTU9ERV82R19PRkZTRVQ7Cj4gKwkJCWJyZWFrOwo+ ICsJCWNhc2UgWFNESVJYX01PREVfMTJHSV9NQVNLOgo+ICsJCQljdHJsLT52YWwgPSBYU0RJUlhf TU9ERV8xMkdJX09GRlNFVDsKPiArCQkJYnJlYWs7Cj4gKwkJY2FzZSBYU0RJUlhfTU9ERV8xMkdG X01BU0s6Cj4gKwkJCWN0cmwtPnZhbCA9IFhTRElSWF9NT0RFXzEyR0ZfT0ZGU0VUOwo+ICsJCQli cmVhazsKPiArCQl9Cj4gKwkJYnJlYWs7Cj4gKwljYXNlIFY0TDJfQ0lEX1hJTElOWF9TRElSWF9D UkM6Cj4gKwkJY3RybC0+dmFsID0geHNkaXJ4c3NfcmVhZCh4c2RpcnhzcywgWFNESVJYX0NSQ19F UlJDTlRfUkVHKTsKPiArCQl4c2Rpcnhzc193cml0ZSh4c2RpcnhzcywgWFNESVJYX0NSQ19FUlJD TlRfUkVHLCAweGZmZmYpOwo+ICsJCWJyZWFrOwo+ICsJY2FzZSBWNEwyX0NJRF9YSUxJTlhfU0RJ UlhfRURIX0VSUkNOVDoKPiArCQl2YWwgPSB4c2Rpcnhzc19yZWFkKHhzZGlyeHNzLCBYU0RJUlhf TU9ERV9ERVRfU1RBVF9SRUcpOwo+ICsJCXZhbCAmPSBYU0RJUlhfTU9ERV9ERVRfU1RBVF9SWF9N T0RFX01BU0s7Cj4gKwkJaWYgKHZhbCA9PSBYU0RJUlhfTU9ERV9TRF9NQVNLKSB7Cj4gKwkJCWN0 cmwtPnZhbCA9IHhzZGlyeHNzX3JlYWQoeHNkaXJ4c3MsCj4gKwkJCQkJCSAgWFNESVJYX0VESF9F UlJDTlRfUkVHKTsKPiArCQl9IGVsc2Ugewo+ICsJCQlzcGluX3VubG9ja19pcnFyZXN0b3JlKCZ4 c2Rpcnhzcy0+c2xvY2ssIGZsYWdzKTsKPiArCQkJZGV2X2RiZyhkZXYsICIlZCAtIG5vdCBpbiBT RCBtb2RlXG4iLCBjdHJsLT5pZCk7Cj4gKwkJCXJldHVybiAtRUlOVkFMOwo+ICsJCX0KPiArCQli cmVhazsKPiArCWNhc2UgVjRMMl9DSURfWElMSU5YX1NESVJYX0VESF9TVEFUVVM6Cj4gKwkJdmFs ID0geHNkaXJ4c3NfcmVhZCh4c2RpcnhzcywgWFNESVJYX01PREVfREVUX1NUQVRfUkVHKTsKPiAr CQl2YWwgJj0gWFNESVJYX01PREVfREVUX1NUQVRfUlhfTU9ERV9NQVNLOwo+ICsJCWlmICh2YWwg PT0gWFNESVJYX01PREVfU0RfTUFTSykgewo+ICsJCQljdHJsLT52YWwgPSB4c2Rpcnhzc19yZWFk KHhzZGlyeHNzLAo+ICsJCQkJCQkgIFhTRElSWF9FREhfU1RBVF9SRUcpOwo+ICsJCX0gZWxzZSB7 Cj4gKwkJCXNwaW5fdW5sb2NrX2lycXJlc3RvcmUoJnhzZGlyeHNzLT5zbG9jaywgZmxhZ3MpOwo+ ICsJCQlkZXZfZGJnKGRldiwgIiVkIC0gbm90IGluIFNEIG1vZGVcbiIsIGN0cmwtPmlkKTsKPiAr CQkJcmV0dXJuIC1FSU5WQUw7Cj4gKwkJfQo+ICsJCWJyZWFrOwo+ICsJY2FzZSBWNEwyX0NJRF9Y SUxJTlhfU0RJUlhfVFNfSVNfSU5URVJMQUNFRDoKPiArCQljdHJsLT52YWwgPSB4c2Rpcnhzcy0+ dHNfaXNfaW50ZXJsYWNlZDsKPiArCQlicmVhazsKPiArCWRlZmF1bHQ6Cj4gKwkJc3Bpbl91bmxv Y2tfaXJxcmVzdG9yZSgmeHNkaXJ4c3MtPnNsb2NrLCBmbGFncyk7Cj4gKwkJZGV2X2VycihkZXYs ICJHZXQgSW52YWxpZCBjb250cm9sIGlkIDB4JTB4XG4iLCBjdHJsLT5pZCk7Cj4gKwkJcmV0dXJu IC1FSU5WQUw7Cj4gKwl9Cj4gKwo+ICsJc3Bpbl91bmxvY2tfaXJxcmVzdG9yZSgmeHNkaXJ4c3Mt PnNsb2NrLCBmbGFncyk7Cj4gKwlyZXR1cm4gMDsKPiArfQo+ICsKPiArLyoqCj4gKyAqIHhzZGly eHNzX2xvZ19zdGF0dXMgLSBMb2dzIHRoZSBzdGF0dXMgb2YgdGhlIFNESSBSeCBTdWJzeXN0ZW0K PiArICogQHNkOiBQb2ludGVyIHRvIFY0TDIgc3ViZGV2aWNlIHN0cnVjdHVyZQo+ICsgKgo+ICsg KiBUaGlzIGZ1bmN0aW9uIHByaW50cyB0aGUgY3VycmVudCBzdGF0dXMgb2YgWGlsaW54IFNESSBS eCBTdWJzeXN0ZW0KPiArICoKPiArICogUmV0dXJuOiAwIG9uIHN1Y2Nlc3MKPiArICovCj4gK3N0 YXRpYyBpbnQgeHNkaXJ4c3NfbG9nX3N0YXR1cyhzdHJ1Y3QgdjRsMl9zdWJkZXYgKnNkKQo+ICt7 Cj4gKwlzdHJ1Y3QgeHNkaXJ4c3Nfc3RhdGUgKnhzZGlyeHNzID0gdG9feHNkaXJ4c3NzdGF0ZShz ZCk7Cj4gKwl1MzIgaTsKPiArCj4gKwl2NGwyX2luZm8oc2QsICIqKioqKiBTREkgUnggc3Vic3lz dGVtIHJlZyBkdW1wIHN0YXJ0ICoqKioqXG4iKTsKPiArCXY0bDJfaW5mbyhzZCwgIk5vIDogUmVn aXN0ZXIgTmFtZSA6IFZhbHVlXG4iKTsKPiArCWZvciAoaSA9IDA7IGkgPCBBUlJBWV9TSVpFKHhz ZGlyeHNzX3JlZ21hcCk7IGkrKykgewo+ICsJCXY0bDJfaW5mbyhzZCwgIiUwMmQgOiAlcyByZWdp c3RlciA6IDB4JTA4eFxuIiwgaSwKPiArCQkJICB4c2Rpcnhzc19yZWdtYXBbaV0ubmFtZSwKPiAr CQkJICB4c2Rpcnhzc19yZWFkKHhzZGlyeHNzLCB4c2Rpcnhzc19yZWdtYXBbaV0ub2Zmc2V0KSk7 Cj4gKwl9Cj4gKwl2NGwyX2luZm8oc2QsICIqKioqKiBTREkgUnggc3Vic3lzdGVtIHJlZyBkdW1w IGVuZCAqKioqKlxuIik7Cj4gKwo+ICsJdjRsMl9jdHJsX3N1YmRldl9sb2dfc3RhdHVzKHNkKTsK PiArCj4gKwlyZXR1cm4gMDsKPiArfQo+ICsKPiArLyoqCj4gKyAqIHhzZGlyeHNzX2dfZnJhbWVf aW50ZXJ2YWwgLSBHZXQgdGhlIGZyYW1lIGludGVydmFsCj4gKyAqIEBzZDogVjRMMiBTdWIgZGV2 aWNlCj4gKyAqIEBmaTogUG9pbnRlciB0byBWNGwyIFN1YiBkZXZpY2UgZnJhbWUgaW50ZXJ2YWwg c3RydWN0dXJlCj4gKyAqCj4gKyAqIFRoaXMgZnVuY3Rpb24gaXMgdXNlZCB0byBnZXQgdGhlIGZy YW1lIGludGVydmFsLgo+ICsgKiBUaGUgZnJhbWUgcmF0ZSBjYW4gYmUgaW50ZWdyYWwgb3IgZnJh Y3Rpb25hbC4KPiArICogSW50ZWdyYWwgZnJhbWUgcmF0ZSBlLmcuIG51bWVyYXRvciA9IDEwMDAs IGRlbm9taW5hdG9yID0gMjQwMDAgPT4gMjQgZnBzCj4gKyAqIEZyYWN0aW9uYWwgZnJhbWUgcmF0 ZSBlLmcuIG51bWVyYXRvciA9IDEwMDEsIGRlbm9taW5hdG9yID0gMjQwMDAgPT4gMjMuOTcgZnBz Cj4gKyAqCj4gKyAqIFJldHVybjogMCBvbiBzdWNjZXNzCj4gKyAqLwo+ICtzdGF0aWMgaW50IHhz ZGlyeHNzX2dfZnJhbWVfaW50ZXJ2YWwoc3RydWN0IHY0bDJfc3ViZGV2ICpzZCwKPiArCQkJCSAg ICAgc3RydWN0IHY0bDJfc3ViZGV2X2ZyYW1lX2ludGVydmFsICpmaSkKPiArewo+ICsJc3RydWN0 IHhzZGlyeHNzX3N0YXRlICp4c2RpcnhzcyA9IHRvX3hzZGlyeHNzc3RhdGUoc2QpOwo+ICsJdW5z aWduZWQgbG9uZyBmbGFnczsKPiArCj4gKwlpZiAoIXhzZGlyeHNzLT52aWRsb2NrZWQpIHsKClNo b3VsZG4ndCB0aGlzIGJlIGFjY2Vzc2VkIHVuZGVyIHNwaW5sb2NrPwoKPiArCQlkZXZfZXJyKHhz ZGlyeHNzLT5kZXYsICJWaWRlbyBub3QgbG9ja2VkIVxuIik7Cj4gKwkJcmV0dXJuIC1FSU5WQUw7 Cj4gKwl9Cj4gKwo+ICsJc3Bpbl9sb2NrX2lycXNhdmUoJnhzZGlyeHNzLT5zbG9jaywgZmxhZ3Mp Owo+ICsJZmktPmludGVydmFsID0geHNkaXJ4c3MtPmZyYW1lX2ludGVydmFsOwo+ICsJc3Bpbl91 bmxvY2tfaXJxcmVzdG9yZSgmeHNkaXJ4c3MtPnNsb2NrLCBmbGFncyk7Cj4gKwo+ICsJZGV2X2Ri Zyh4c2Rpcnhzcy0+ZGV2LCAiZnJhbWUgcmF0ZSBudW1lcmF0b3IgPSAlZCBkZW5vbWluYXRvciA9 ICVkXG4iLAo+ICsJCXhzZGlyeHNzLT5mcmFtZV9pbnRlcnZhbC5udW1lcmF0b3IsCj4gKwkJeHNk aXJ4c3MtPmZyYW1lX2ludGVydmFsLmRlbm9taW5hdG9yKTsKClRoaXMgdG9vLgoKPiArCXJldHVy biAwOwo+ICt9Cj4gKwo+ICsvKioKPiArICogeHNkaXJ4c3Nfc19zdHJlYW0gLSBJdCBpcyB1c2Vk IHRvIHN0YXJ0L3N0b3AgdGhlIHN0cmVhbWluZy4KPiArICogQHNkOiBWNEwyIFN1YiBkZXZpY2UK PiArICogQGVuYWJsZTogRmxhZyAoVHJ1ZSAvIEZhbHNlKQo+ICsgKgo+ICsgKiBUaGlzIGZ1bmN0 aW9uIGNvbnRyb2xzIHRoZSBzdGFydCBvciBzdG9wIG9mIHN0cmVhbWluZyBmb3IgdGhlCj4gKyAq IFhpbGlueCBTREkgUnggU3Vic3lzdGVtLgo+ICsgKgo+ICsgKiBSZXR1cm46IDAgb24gc3VjY2Vz cywgZXJyb3JzIG90aGVyd2lzZQo+ICsgKi8KPiArc3RhdGljIGludCB4c2Rpcnhzc19zX3N0cmVh bShzdHJ1Y3QgdjRsMl9zdWJkZXYgKnNkLCBpbnQgZW5hYmxlKQo+ICt7Cj4gKwlzdHJ1Y3QgeHNk aXJ4c3Nfc3RhdGUgKnhzZGlyeHNzID0gdG9feHNkaXJ4c3NzdGF0ZShzZCk7Cj4gKwlzdHJ1Y3Qg ZGV2aWNlICpkZXYgPSB4c2Rpcnhzcy0+ZGV2Owo+ICsJdW5zaWduZWQgbG9uZyBmbGFnczsKPiAr Cj4gKwlzcGluX2xvY2tfaXJxc2F2ZSgmeHNkaXJ4c3MtPnNsb2NrLCBmbGFncyk7Cj4gKwlpZiAo ZW5hYmxlID09IHhzZGlyeHNzLT5zdHJlYW1pbmcpIHsKPiArCQlzcGluX3VubG9ja19pcnFyZXN0 b3JlKCZ4c2Rpcnhzcy0+c2xvY2ssIGZsYWdzKTsKPiArCQlkZXZfZGJnKGRldiwgImFscmVhZHkg aW4gc2FtZSBzdHJlYW1pbmcgc3RhdGUgYXMgcmVxdWVzdGVkXG4iKTsKPiArCQlyZXR1cm4gMDsK PiArCX0KPiArCj4gKwlpZiAoZW5hYmxlKSB7Cj4gKwkJaWYgKCF4c2Rpcnhzcy0+dmlkbG9ja2Vk KSB7Cj4gKwkJCXNwaW5fdW5sb2NrX2lycXJlc3RvcmUoJnhzZGlyeHNzLT5zbG9jaywgZmxhZ3Mp Owo+ICsJCQlkZXZfZXJyKGRldiwgIlZpZGVvIGlzIG5vdCBsb2NrZWRcbiIpOwo+ICsJCQlyZXR1 cm4gLUVJTlZBTDsKPiArCQl9Cj4gKwkJeHNkaXJ4X3N0cmVhbWZsb3dfY29udHJvbCh4c2Rpcnhz cywgdHJ1ZSk7Cj4gKwl9IGVsc2Ugewo+ICsJCXhzZGlyeF9zdHJlYW1mbG93X2NvbnRyb2woeHNk aXJ4c3MsIGZhbHNlKTsKClRoaXMgY2FuIG1vdmUgb3V0IG9mIHRoaXMgaWYgc3RhdGVtZW50LCBw YXNzaW5nIGVuYWJsZSBvciAhIWVuYWJsZSBkaXJlY3RseS4KVXAgdG8geW91LgoKPiArCX0KPiAr CXNwaW5fdW5sb2NrX2lycXJlc3RvcmUoJnhzZGlyeHNzLT5zbG9jaywgZmxhZ3MpOwo+ICsJZGV2 X2RiZyhkZXYsICJTdHJlYW1pbmcgJXNcbiIsIGVuYWJsZSA/ICJzdGFydGVkIiA6ICJzdG9wcGVk Iik7Cj4gKwlyZXR1cm4gMDsKPiArfQo+ICsKPiArLyoqCj4gKyAqIHhzZGlyeHNzX2dfaW5wdXRf c3RhdHVzIC0gSXQgaXMgdXNlZCB0byBkZXRlcm1pbmUgaWYgdGhlIHZpZGVvIHNpZ25hbAo+ICsg KiBpcyBwcmVzZW50IC8gbG9ja2VkIG9udG8gb3Igbm90Lgo+ICsgKgo+ICsgKiBAc2Q6IFY0TDIg U3ViIGRldmljZQo+ICsgKiBAc3RhdHVzOiBzdGF0dXMgb2Ygc2lnbmFsIGxvY2tlZAo+ICsgKgo+ ICsgKiBUaGlzIGlzIHVzZWQgdG8gZGV0ZXJtaW5lIGlmIHRoZSB2aWRlbyBzaWduYWwgaXMgcHJl c2VudCBhbmQgbG9ja2VkIG9udG8KPiArICogYnkgdGhlIFNESSBSeCBjb3JlIG9yIG5vdCBiYXNl ZCBvbiB2aWRsb2NrZWQgZmxhZy4KPiArICoKPiArICogUmV0dXJuOiB6ZXJvIG9uIHN1Y2Nlc3MK PiArICovCj4gK3N0YXRpYyBpbnQgeHNkaXJ4c3NfZ19pbnB1dF9zdGF0dXMoc3RydWN0IHY0bDJf c3ViZGV2ICpzZCwgdTMyICpzdGF0dXMpCj4gK3sKPiArCXN0cnVjdCB4c2Rpcnhzc19zdGF0ZSAq eHNkaXJ4c3MgPSB0b194c2Rpcnhzc3N0YXRlKHNkKTsKPiArCXVuc2lnbmVkIGxvbmcgZmxhZ3M7 Cj4gKwo+ICsJc3Bpbl9sb2NrX2lycXNhdmUoJnhzZGlyeHNzLT5zbG9jaywgZmxhZ3MpOwo+ICsJ aWYgKCF4c2Rpcnhzcy0+dmlkbG9ja2VkKQo+ICsJCSpzdGF0dXMgPSBWNEwyX0lOX1NUX05PX1NZ TkMgfCBWNEwyX0lOX1NUX05PX1NJR05BTDsKPiArCWVsc2UKPiArCQkqc3RhdHVzID0gMDsKPiAr Cj4gKwlzcGluX3VubG9ja19pcnFyZXN0b3JlKCZ4c2Rpcnhzcy0+c2xvY2ssIGZsYWdzKTsKPiAr CXJldHVybiAwOwo+ICt9Cj4gKwo+ICtzdGF0aWMgc3RydWN0IHY0bDJfbWJ1c19mcmFtZWZtdCAq Cj4gK19feHNkaXJ4c3NfZ2V0X3BhZF9mb3JtYXQoc3RydWN0IHhzZGlyeHNzX3N0YXRlICp4c2Rp cnhzcywKPiArCQkJICBzdHJ1Y3QgdjRsMl9zdWJkZXZfcGFkX2NvbmZpZyAqY2ZnLAo+ICsJCQkg IHVuc2lnbmVkIGludCBwYWQsIHUzMiB3aGljaCkKPiArewo+ICsJc3dpdGNoICh3aGljaCkgewo+ ICsJY2FzZSBWNEwyX1NVQkRFVl9GT1JNQVRfVFJZOgo+ICsJCXJldHVybiB2NGwyX3N1YmRldl9n ZXRfdHJ5X2Zvcm1hdCgmeHNkaXJ4c3MtPnN1YmRldiwgY2ZnLCBwYWQpOwo+ICsJY2FzZSBWNEwy X1NVQkRFVl9GT1JNQVRfQUNUSVZFOgo+ICsJCXJldHVybiAmeHNkaXJ4c3MtPnNyY19mb3JtYXQ7 Cj4gKwlkZWZhdWx0Ogo+ICsJCXJldHVybiBOVUxMOwo+ICsJfQo+ICt9Cj4gKwo+ICsvKioKPiAr ICogeHNkaXJ4c3NfaW5pdF9jZmcgLSBJbml0aWFsaXNlIHRoZSBwYWQgZm9ybWF0IGNvbmZpZyB0 byBkZWZhdWx0Cj4gKyAqIEBzZDogUG9pbnRlciB0byBWNEwyIFN1YiBkZXZpY2Ugc3RydWN0dXJl Cj4gKyAqIEBjZmc6IFBvaW50ZXIgdG8gc3ViIGRldmljZSBwYWQgaW5mb3JtYXRpb24gc3RydWN0 dXJlCj4gKyAqCj4gKyAqIFRoaXMgZnVuY3Rpb24gaXMgdXNlZCB0byBpbml0aWFsaXplIHRoZSBw YWQgZm9ybWF0IHdpdGggdGhlIGRlZmF1bHQKPiArICogdmFsdWVzLgo+ICsgKgo+ICsgKiBSZXR1 cm46IDAgb24gc3VjY2Vzcwo+ICsgKi8KPiArc3RhdGljIGludCB4c2Rpcnhzc19pbml0X2NmZyhz dHJ1Y3QgdjRsMl9zdWJkZXYgKnNkLAo+ICsJCQkgICAgIHN0cnVjdCB2NGwyX3N1YmRldl9wYWRf Y29uZmlnICpjZmcpCj4gK3sKPiArCXN0cnVjdCB4c2Rpcnhzc19zdGF0ZSAqeHNkaXJ4c3MgPSB0 b194c2Rpcnhzc3N0YXRlKHNkKTsKPiArCXN0cnVjdCB2NGwyX21idXNfZnJhbWVmbXQgKmZvcm1h dDsKPiArCj4gKwlmb3JtYXQgPSB2NGwyX3N1YmRldl9nZXRfdHJ5X2Zvcm1hdChzZCwgY2ZnLCAw KTsKPiArCSpmb3JtYXQgPSB4c2Rpcnhzcy0+ZGVmYXVsdF9mb3JtYXQ7Cj4gKwo+ICsJcmV0dXJu IDA7Cj4gK30KPiArCj4gKy8qKgo+ICsgKiB4c2Rpcnhzc19nZXRfc2V0X2Zvcm1hdCAtIFRoaXMg aXMgdXNlZCB0byBnZXQvc2V0IHRoZSBwYWQgZm9ybWF0Cj4gKyAqIEBzZDogUG9pbnRlciB0byBW NEwyIFN1YiBkZXZpY2Ugc3RydWN0dXJlCj4gKyAqIEBjZmc6IFBvaW50ZXIgdG8gc3ViIGRldmlj ZSBwYWQgaW5mb3JtYXRpb24gc3RydWN0dXJlCj4gKyAqIEBmbXQ6IFBvaW50ZXIgdG8gcGFkIGxl dmVsIG1lZGlhIGJ1cyBmb3JtYXQKPiArICoKPiArICogVGhpcyBmdW5jdGlvbiBpcyB1c2VkIHRv IGdldCBhbmQgc2V0IHRoZSBwYWQgZm9ybWF0Lgo+ICsgKiBTaW5jZSB0aGUgcGFkIGZvcm1hdCBp cyBmaXhlZCBpbiBoYXJkd2FyZSwgaXQgY2FuJ3QgYmUKPiArICogbW9kaWZpZWQgb24gcnVuIHRp bWUuIFNvIHNldCBhbmQgZ2V0IGFyZSBzYW1lLgo+ICsgKgo+ICsgKiBSZXR1cm46IDAgb24gc3Vj Y2Vzcwo+ICsgKi8KPiArc3RhdGljIGludCB4c2Rpcnhzc19nZXRfc2V0X2Zvcm1hdChzdHJ1Y3Qg djRsMl9zdWJkZXYgKnNkLAo+ICsJCQkJICAgc3RydWN0IHY0bDJfc3ViZGV2X3BhZF9jb25maWcg KmNmZywKPiArCQkJCSAgIHN0cnVjdCB2NGwyX3N1YmRldl9mb3JtYXQgKmZtdCkKPiArewo+ICsJ c3RydWN0IHhzZGlyeHNzX3N0YXRlICp4c2RpcnhzcyA9IHRvX3hzZGlyeHNzc3RhdGUoc2QpOwo+ ICsJdW5zaWduZWQgbG9uZyBmbGFnczsKPiArCj4gKwlzcGluX2xvY2tfaXJxc2F2ZSgmeHNkaXJ4 c3MtPnNsb2NrLCBmbGFncyk7Cj4gKwlpZiAoIXhzZGlyeHNzLT52aWRsb2NrZWQpIHsKPiArCQlz cGluX3VubG9ja19pcnFyZXN0b3JlKCZ4c2Rpcnhzcy0+c2xvY2ssIGZsYWdzKTsKPiArCQlkZXZf ZXJyKHhzZGlyeHNzLT5kZXYsICJWaWRlbyBub3QgbG9ja2VkIVxuIik7Cj4gKwkJcmV0dXJuIC1F SU5WQUw7Cj4gKwl9Cj4gKwo+ICsJZm10LT5mb3JtYXQgPSAqX194c2Rpcnhzc19nZXRfcGFkX2Zv cm1hdCh4c2RpcnhzcywgY2ZnLAo+ICsJCQkJCQkgZm10LT5wYWQsIGZtdC0+d2hpY2gpOwo+ICsK PiArCXNwaW5fdW5sb2NrX2lycXJlc3RvcmUoJnhzZGlyeHNzLT5zbG9jaywgZmxhZ3MpOwo+ICsJ ZGV2X2RiZyh4c2Rpcnhzcy0+ZGV2LAo+ICsJCSJzdHJlYW0gd2lkdGggJWQgaGVpZ2h0ICVkIGNv ZGUgJWQgZmllbGQgJWQgY29sb3JzcGFjZSAlZCB4ZmVyX2Z1bmMgJWQgcXVhbnRpemF0aW9uICVk XG4iLAo+ICsJCWZtdC0+Zm9ybWF0LndpZHRoLCBmbXQtPmZvcm1hdC5oZWlnaHQsCj4gKwkJZm10 LT5mb3JtYXQuY29kZSwgZm10LT5mb3JtYXQuZmllbGQsCj4gKwkJZm10LT5mb3JtYXQuY29sb3Jz cGFjZSwgZm10LT5mb3JtYXQueGZlcl9mdW5jLAo+ICsJCWZtdC0+Zm9ybWF0LnF1YW50aXphdGlv bik7Cj4gKwlyZXR1cm4gMDsKPiArfQo+ICsKPiArLyoqCj4gKyAqIHhzZGlyeHNzX2VudW1fbWJ1 c19jb2RlIC0gSGFuZGxlIHBpeGVsIGZvcm1hdCBlbnVtZXJhdGlvbgo+ICsgKiBAc2Q6IHBvaW50 ZXIgdG8gdjRsMiBzdWJkZXYgc3RydWN0dXJlCj4gKyAqIEBjZmc6IFY0TDIgc3ViZGV2IHBhZCBj b25maWd1cmF0aW9uCj4gKyAqIEBjb2RlOiBwb2ludGVyIHRvIHY0bDJfc3ViZGV2X21idXNfY29k ZV9lbnVtIHN0cnVjdHVyZQo+ICsgKgo+ICsgKiBSZXR1cm46IC1FSU5WQUwgb3IgemVybyBvbiBz dWNjZXNzCj4gKyAqLwo+ICtzdGF0aWMgaW50IHhzZGlyeHNzX2VudW1fbWJ1c19jb2RlKHN0cnVj dCB2NGwyX3N1YmRldiAqc2QsCj4gKwkJCQkgICBzdHJ1Y3QgdjRsMl9zdWJkZXZfcGFkX2NvbmZp ZyAqY2ZnLAo+ICsJCQkJICAgc3RydWN0IHY0bDJfc3ViZGV2X21idXNfY29kZV9lbnVtICpjb2Rl KQo+ICt7Cj4gKwlzdHJ1Y3QgeHNkaXJ4c3Nfc3RhdGUgKnhzZGlyeHNzID0gdG9feHNkaXJ4c3Nz dGF0ZShzZCk7Cj4gKwl1MzIgaW5kZXggPSBjb2RlLT5pbmRleDsKPiArCXUzMiBtYXhpbmRleDsK PiArCj4gKwlpZiAoeHNkaXJ4c3MtPmJwYyA9PSAxMCkKPiArCQltYXhpbmRleCA9IEFSUkFZX1NJ WkUoeHNkaXJ4c3NfMTBicGNfbWJ1c19mbXRzKTsKPiArCWVsc2UKPiArCQltYXhpbmRleCA9IEFS UkFZX1NJWkUoeHNkaXJ4c3NfMTJicGNfbWJ1c19mbXRzKTsKPiArCj4gKwlpZiAoY29kZS0+cGFk IHx8IGluZGV4ID49IG1heGluZGV4KQo+ICsJCXJldHVybiAtRUlOVkFMOwo+ICsKPiArCWlmICh4 c2Rpcnhzcy0+YnBjID09IDEwKQo+ICsJCWNvZGUtPmNvZGUgPSB4c2Rpcnhzc18xMGJwY19tYnVz X2ZtdHNbaW5kZXhdOwo+ICsJZWxzZQo+ICsJCWNvZGUtPmNvZGUgPSB4c2Rpcnhzc18xMmJwY19t YnVzX2ZtdHNbaW5kZXhdOwo+ICsKPiArCXJldHVybiAwOwo+ICt9Cj4gKwo+ICsvKioKPiArICog eHNkaXJ4c3NfZW51bV9kdl90aW1pbmdzIC0gRW51bWVyYXRlIGFsbCB0aGUgc3VwcG9ydGVkIERW IHRpbWluZ3MKPiArICogQHNkOiBwb2ludGVyIHRvIHY0bDIgc3ViZGV2IHN0cnVjdHVyZQo+ICsg KiBAdGltaW5nczogRFYgdGltaW5ncyBzdHJ1Y3R1cmUgdG8gYmUgcmV0dXJuZWQuCj4gKyAqCj4g KyAqIFJldHVybjogLUVJTlZBTCBpbmNhc2Ugb2YgaW52YWxpZCBpbmRleCBhbmQgcGFkIG9yIHpl cm8gb24gc3VjY2Vzcwo+ICsgKi8KPiArc3RhdGljIGludCB4c2Rpcnhzc19lbnVtX2R2X3RpbWlu Z3Moc3RydWN0IHY0bDJfc3ViZGV2ICpzZCwKPiArCQkJCSAgICBzdHJ1Y3QgdjRsMl9lbnVtX2R2 X3RpbWluZ3MgKnRpbWluZ3MpCj4gK3sKPiArCWlmICh0aW1pbmdzLT5pbmRleCA+PSBBUlJBWV9T SVpFKGZtdF9jYXApKQo+ICsJCXJldHVybiAtRUlOVkFMOwo+ICsKPiArCWlmICh0aW1pbmdzLT5w YWQgIT0gMCkKPiArCQlyZXR1cm4gLUVJTlZBTDsKPiArCj4gKwl0aW1pbmdzLT50aW1pbmdzID0g Zm10X2NhcFt0aW1pbmdzLT5pbmRleF07Cj4gKwlyZXR1cm4gMDsKPiArfQo+ICsKPiArLyoqCj4g KyAqIHhzZGlyeHNzX3F1ZXJ5X2R2X3RpbWluZ3MgLSBRdWVyeSBmb3IgdGhlIGN1cnJlbnQgRFYg dGltaW5ncwo+ICsgKiBAc2Q6IHBvaW50ZXIgdG8gdjRsMiBzdWJkZXYgc3RydWN0dXJlCj4gKyAq IEB0aW1pbmdzOiBEViB0aW1pbmdzIHN0cnVjdHVyZSB0byBiZSByZXR1cm5lZC4KPiArICoKPiAr ICogUmV0dXJuOiAtRU5PTENLIHdoZW4gdmlkZW8gaXMgbm90IGxvY2tlZCwgLUVSQU5HRSB3aGVu IGNvcnJlc3BvbmRpbmcgdGltaW5nCj4gKyAqIGVudHJ5IGlzIG5vdCBmb3VuZCBvciB6ZXJvIG9u IHN1Y2Nlc3MuCj4gKyAqLwo+ICtzdGF0aWMgaW50IHhzZGlyeHNzX3F1ZXJ5X2R2X3RpbWluZ3Mo c3RydWN0IHY0bDJfc3ViZGV2ICpzZCwKPiArCQkJCSAgICAgc3RydWN0IHY0bDJfZHZfdGltaW5n cyAqdGltaW5ncykKPiArewo+ICsJc3RydWN0IHhzZGlyeHNzX3N0YXRlICpzdGF0ZSA9IHRvX3hz ZGlyeHNzc3RhdGUoc2QpOwo+ICsJdW5zaWduZWQgaW50IGk7Cj4gKwl1bnNpZ25lZCBsb25nIGZs YWdzOwo+ICsKPiArCXNwaW5fbG9ja19pcnFzYXZlKCZzdGF0ZS0+c2xvY2ssIGZsYWdzKTsKPiAr CWlmICghc3RhdGUtPnZpZGxvY2tlZCkgewo+ICsJCXNwaW5fdW5sb2NrX2lycXJlc3RvcmUoJnN0 YXRlLT5zbG9jaywgZmxhZ3MpOwo+ICsJCXJldHVybiAtRU5PTENLOwo+ICsJfQo+ICsKPiArCWZv ciAoaSA9IDA7IGkgPCBBUlJBWV9TSVpFKHhzZGlyeHNzX2R2X3RpbWluZ3MpOyBpKyspIHsKPiAr CQlpZiAoc3RhdGUtPmZvcm1hdC53aWR0aCA9PSB4c2Rpcnhzc19kdl90aW1pbmdzW2ldLndpZHRo ICYmCj4gKwkJICAgIHN0YXRlLT5mb3JtYXQuaGVpZ2h0ID09IHhzZGlyeHNzX2R2X3RpbWluZ3Nb aV0uaGVpZ2h0ICYmCj4gKwkJICAgIHN0YXRlLT5mcmFtZV9pbnRlcnZhbC5kZW5vbWluYXRvciA9 PQo+ICsJCSAgICAoeHNkaXJ4c3NfZHZfdGltaW5nc1tpXS5mcHMgKiAxMDAwKSkgewo+ICsJCQkq dGltaW5ncyA9IHhzZGlyeHNzX2R2X3RpbWluZ3NbaV0udGltaW5nOwo+ICsJCQlzdGF0ZS0+ZGV0 ZWN0ZWRfdGltaW5nc19pbmRleCA9IGk7Cj4gKwkJCXNwaW5fdW5sb2NrX2lycXJlc3RvcmUoJnN0 YXRlLT5zbG9jaywgZmxhZ3MpOwo+ICsJCQlyZXR1cm4gMDsKPiArCQl9Cj4gKwl9Cj4gKwlzcGlu X3VubG9ja19pcnFyZXN0b3JlKCZzdGF0ZS0+c2xvY2ssIGZsYWdzKTsKPiArCj4gKwlyZXR1cm4g LUVSQU5HRTsKPiArfQo+ICsKPiArc3RhdGljIGludCB4c2Rpcnhzc19zX2R2X3RpbWluZ3Moc3Ry dWN0IHY0bDJfc3ViZGV2ICpzZCwKPiArCQkJCSBzdHJ1Y3QgdjRsMl9kdl90aW1pbmdzICp0aW1p bmdzKQo+ICt7Cj4gKwlzdHJ1Y3QgeHNkaXJ4c3Nfc3RhdGUgKnN0YXRlID0gdG9feHNkaXJ4c3Nz dGF0ZShzZCk7Cj4gKwl1MzIgaSA9IHN0YXRlLT5kZXRlY3RlZF90aW1pbmdzX2luZGV4Owo+ICsJ dW5zaWduZWQgbG9uZyBmbGFnczsKPiArCj4gKwlzcGluX2xvY2tfaXJxc2F2ZSgmc3RhdGUtPnNs b2NrLCBmbGFncyk7Cj4gKwlpZiAoIXN0YXRlLT52aWRsb2NrZWQpIHsKPiArCQlzcGluX3VubG9j a19pcnFyZXN0b3JlKCZzdGF0ZS0+c2xvY2ssIGZsYWdzKTsKPiArCQlyZXR1cm4gLUVJTlZBTDsK PiArCX0KPiArCgpJcyB0aGUgc3BpbmxvY2sgbmVlZGVkIHRvIGJlIGhlbGQgZm9yIGJlbG93PwoK PiArCS8qIGlucHV0IHRpbWluZyBzaG91bGQgbWF0Y2ggcXVlcnkgZHZfdGltaW5nICovCj4gKwlp ZiAoIXY0bDJfbWF0Y2hfZHZfdGltaW5ncyh0aW1pbmdzLAo+ICsJCQkJICAgJnhzZGlyeHNzX2R2 X3RpbWluZ3NbaV0udGltaW5nLAo+ICsJCQkJICAgMCwgZmFsc2UpKSB7Cj4gKwkJc3Bpbl91bmxv Y2tfaXJxcmVzdG9yZSgmc3RhdGUtPnNsb2NrLCBmbGFncyk7Cj4gKwkJcmV0dXJuIC1FSU5WQUw7 Cj4gKwl9Cj4gKwo+ICsJc3RhdGUtPmN1cnJlbnRfdGltaW5ncyA9ICp0aW1pbmdzOwo+ICsKPiAr CS8qIFVwZGF0ZSB0aGUgbWVkaWEgYnVzIGZvcm1hdCAqLwo+ICsJc3RhdGUtPnNyY19mb3JtYXQg PSBzdGF0ZS0+Zm9ybWF0Owo+ICsJc3Bpbl91bmxvY2tfaXJxcmVzdG9yZSgmc3RhdGUtPnNsb2Nr LCBmbGFncyk7Cj4gKwo+ICsJcmV0dXJuIDA7Cj4gK30KPiArCj4gK3N0YXRpYyBpbnQgeHNkaXJ4 c3NfZ19kdl90aW1pbmdzKHN0cnVjdCB2NGwyX3N1YmRldiAqc2QsCj4gKwkJCQkgc3RydWN0IHY0 bDJfZHZfdGltaW5ncyAqdGltaW5ncykKPiArewo+ICsJc3RydWN0IHhzZGlyeHNzX3N0YXRlICpz dGF0ZSA9IHRvX3hzZGlyeHNzc3RhdGUoc2QpOwo+ICsKPiArCSp0aW1pbmdzID0gc3RhdGUtPmN1 cnJlbnRfdGltaW5nczsKClRoaXMgbmVlZHMgdGhlIGxvY2sgaWYgYWJvdmUgZG9lc24ndCBjaGFu Z2UsIGF0IGxlYXN0IHBlciBsb2NrIGRlc2NyaXB0aW9uLgoKPiArCXJldHVybiAwOwo+ICt9Cj4g Kwo+ICtzdGF0aWMgaW50IHhzZGlyeHNzX2R2X3RpbWluZ3NfY2FwKHN0cnVjdCB2NGwyX3N1YmRl diAqc2QsCj4gKwkJCQkgICBzdHJ1Y3QgdjRsMl9kdl90aW1pbmdzX2NhcCAqY2FwKQo+ICt7Cj4g KwlpZiAoY2FwLT5wYWQgIT0gMCkKPiArCQlyZXR1cm4gLUVJTlZBTDsKPiArCj4gKwkqY2FwID0g eHNkaXJ4c3NfdGltaW5nc19jYXA7Cj4gKwlyZXR1cm4gMDsKPiArfQo+ICsKPiArLyogLS0tLS0t LS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0t LS0tLS0tLS0tLS0tLS0KPiArICogTWVkaWEgT3BlcmF0aW9ucwo+ICsgKi8KPiArCj4gK3N0YXRp YyBjb25zdCBzdHJ1Y3QgbWVkaWFfZW50aXR5X29wZXJhdGlvbnMgeHNkaXJ4c3NfbWVkaWFfb3Bz ID0gewo+ICsJLmxpbmtfdmFsaWRhdGUgPSB2NGwyX3N1YmRldl9saW5rX3ZhbGlkYXRlCj4gK307 Cj4gKwo+ICtzdGF0aWMgY29uc3Qgc3RydWN0IHY0bDJfY3RybF9vcHMgeHNkaXJ4c3NfY3RybF9v cHMgPSB7Cj4gKwkuZ192b2xhdGlsZV9jdHJsID0geHNkaXJ4c3NfZ192b2xhdGlsZV9jdHJsLAo+ ICsJLnNfY3RybAk9IHhzZGlyeHNzX3NfY3RybAo+ICt9Owo+ICsKPiArc3RhdGljIGNvbnN0IHN0 cnVjdCB2NGwyX2N0cmxfY29uZmlnIHhzZGlyeHNzX2VkaF9jdHJsc1tdID0gewo+ICsJewo+ICsJ CS5vcHMJPSAmeHNkaXJ4c3NfY3RybF9vcHMsCj4gKwkJLmlkCT0gVjRMMl9DSURfWElMSU5YX1NE SVJYX0VESF9FUlJPUl9TT1VSQ0VTLAo+ICsJCS5uYW1lCT0gIlNESSBSeCA6IEVESCBFcnJvciBD b3VudCBFbmFibGUiLAo+ICsJCS50eXBlCT0gVjRMMl9DVFJMX1RZUEVfQklUTUFTSywKPiArCQku bWluCT0gMCwKPiArCQkubWF4CT0gWFNESVJYX0VESF9BTExFUlJfTUFTSywKPiArCQkuZGVmCT0g MCwKPiArCX0sIHsKPiArCQkub3BzCT0gJnhzZGlyeHNzX2N0cmxfb3BzLAo+ICsJCS5pZAk9IFY0 TDJfQ0lEX1hJTElOWF9TRElSWF9FREhfRVJSQ05ULAo+ICsJCS5uYW1lCT0gIlNESSBSeCA6IEVE SCBFcnJvciBDb3VudCIsCj4gKwkJLnR5cGUJPSBWNEwyX0NUUkxfVFlQRV9JTlRFR0VSLAo+ICsJ CS5taW4JPSAwLAo+ICsJCS5tYXgJPSAweGZmZmYsCj4gKwkJLnN0ZXAJPSAxLAo+ICsJCS5kZWYJ PSAwLAo+ICsJCS5mbGFncyAgPSBWNEwyX0NUUkxfRkxBR19WT0xBVElMRSB8IFY0TDJfQ1RSTF9G TEFHX1JFQURfT05MWSwKPiArCX0sIHsKPiArCQkub3BzCT0gJnhzZGlyeHNzX2N0cmxfb3BzLAo+ ICsJCS5pZAk9IFY0TDJfQ0lEX1hJTElOWF9TRElSWF9FREhfU1RBVFVTLAo+ICsJCS5uYW1lCT0g IlNESSBSeCA6IEVESCBTdGF0dXMiLAo+ICsJCS50eXBlCT0gVjRMMl9DVFJMX1RZUEVfSU5URUdF UiwKPiArCQkubWluCT0gMCwKPiArCQkubWF4CT0gMHhmZmZmZmZmZiwKPiArCQkuc3RlcAk9IDEs Cj4gKwkJLmRlZgk9IDAsCj4gKwkJLmZsYWdzICA9IFY0TDJfQ1RSTF9GTEFHX1ZPTEFUSUxFIHwg VjRMMl9DVFJMX0ZMQUdfUkVBRF9PTkxZLAo+ICsJfQo+ICt9Owo+ICsKPiArc3RhdGljIGNvbnN0 IHN0cnVjdCB2NGwyX2N0cmxfY29uZmlnIHhzZGlyeHNzX2N0cmxzW10gPSB7Cj4gKwl7Cj4gKwkJ Lm9wcwk9ICZ4c2Rpcnhzc19jdHJsX29wcywKPiArCQkuaWQJPSBWNEwyX0NJRF9YSUxJTlhfU0RJ UlhfRlJBTUVSLAo+ICsJCS5uYW1lCT0gIlNESSBSeCA6IEVuYWJsZSBGcmFtZXIiLAo+ICsJCS50 eXBlCT0gVjRMMl9DVFJMX1RZUEVfQk9PTEVBTiwKPiArCQkubWluCT0gZmFsc2UsCj4gKwkJLm1h eAk9IHRydWUsCj4gKwkJLnN0ZXAJPSAxLAo+ICsJCS5kZWYJPSB0cnVlLAo+ICsJfSwgewo+ICsJ CS5vcHMJPSAmeHNkaXJ4c3NfY3RybF9vcHMsCj4gKwkJLmlkCT0gVjRMMl9DSURfWElMSU5YX1NE SVJYX1ZJRExPQ0tfV0lORE9XLAo+ICsJCS5uYW1lCT0gIlNESSBSeCA6IFZpZGVvIExvY2sgV2lu ZG93IiwKPiArCQkudHlwZQk9IFY0TDJfQ1RSTF9UWVBFX0lOVEVHRVIsCj4gKwkJLm1pbgk9IDAs Cj4gKwkJLm1heAk9IDB4ZmZmZmZmZmYsCj4gKwkJLnN0ZXAJPSAxLAo+ICsJCS5kZWYJPSBYU0RJ UlhfREVGQVVMVF9WSURFT19MT0NLX1dJTkRPVywKPiArCX0sIHsKPiArCQkub3BzCT0gJnhzZGly eHNzX2N0cmxfb3BzLAo+ICsJCS5pZAk9IFY0TDJfQ0lEX1hJTElOWF9TRElSWF9TRUFSQ0hfTU9E RVMsCj4gKwkJLm5hbWUJPSAiU0RJIFJ4IDogTW9kZXMgc2VhcmNoIE1hc2siLAo+ICsJCS50eXBl CT0gVjRMMl9DVFJMX1RZUEVfQklUTUFTSywKPiArCQkubWluCT0gMCwKPiArCQkubWF4CT0gWFNE SVJYX0RFVEVDVF9BTExfTU9ERVMsCj4gKwkJLmRlZgk9IFhTRElSWF9ERVRFQ1RfQUxMX01PREVT LAo+ICsJfSwgewo+ICsJCS5vcHMJPSAmeHNkaXJ4c3NfY3RybF9vcHMsCj4gKwkJLmlkCT0gVjRM Ml9DSURfWElMSU5YX1NESVJYX01PREVfREVURUNULAo+ICsJCS5uYW1lCT0gIlNESSBSeCA6IE1v ZGUgRGV0ZWN0IFN0YXR1cyIsCj4gKwkJLnR5cGUJPSBWNEwyX0NUUkxfVFlQRV9JTlRFR0VSLAo+ ICsJCS5taW4JPSBYU0RJUlhfTU9ERV9TRF9PRkZTRVQsCj4gKwkJLm1heAk9IFhTRElSWF9NT0RF XzEyR0ZfT0ZGU0VULAo+ICsJCS5zdGVwCT0gMSwKPiArCQkuZmxhZ3MgID0gVjRMMl9DVFJMX0ZM QUdfVk9MQVRJTEUgfCBWNEwyX0NUUkxfRkxBR19SRUFEX09OTFksCj4gKwl9LCB7Cj4gKwkJLm9w cwk9ICZ4c2Rpcnhzc19jdHJsX29wcywKPiArCQkuaWQJPSBWNEwyX0NJRF9YSUxJTlhfU0RJUlhf Q1JDLAo+ICsJCS5uYW1lCT0gIlNESSBSeCA6IENSQyBFcnJvciBzdGF0dXMiLAo+ICsJCS50eXBl CT0gVjRMMl9DVFJMX1RZUEVfSU5URUdFUiwKPiArCQkubWluCT0gMCwKPiArCQkubWF4CT0gMHhm ZmZmZmZmZiwKPiArCQkuc3RlcAk9IDEsCj4gKwkJLmRlZgk9IDAsCj4gKwkJLmZsYWdzICA9IFY0 TDJfQ1RSTF9GTEFHX1ZPTEFUSUxFIHwgVjRMMl9DVFJMX0ZMQUdfUkVBRF9PTkxZLAo+ICsJfSwg ewo+ICsJCS5vcHMJPSAmeHNkaXJ4c3NfY3RybF9vcHMsCj4gKwkJLmlkCT0gVjRMMl9DSURfWElM SU5YX1NESVJYX1RTX0lTX0lOVEVSTEFDRUQsCj4gKwkJLm5hbWUJPSAiU0RJIFJ4IDogVFMgaXMg SW50ZXJsYWNlZCIsCj4gKwkJLnR5cGUJPSBWNEwyX0NUUkxfVFlQRV9CT09MRUFOLAo+ICsJCS5t aW4JPSBmYWxzZSwKPiArCQkubWF4CT0gdHJ1ZSwKPiArCQkuZGVmCT0gZmFsc2UsCj4gKwkJLnN0 ZXAJPSAxLAo+ICsJCS5mbGFncyAgPSBWNEwyX0NUUkxfRkxBR19WT0xBVElMRSB8IFY0TDJfQ1RS TF9GTEFHX1JFQURfT05MWSwKPiArCX0sCj4gK307Cj4gKwo+ICtzdGF0aWMgY29uc3Qgc3RydWN0 IHY0bDJfc3ViZGV2X2NvcmVfb3BzIHhzZGlyeHNzX2NvcmVfb3BzID0gewo+ICsJLmxvZ19zdGF0 dXMgPSB4c2Rpcnhzc19sb2dfc3RhdHVzLAo+ICsJLnN1YnNjcmliZV9ldmVudCA9IHhzZGlyeHNz X3N1YnNjcmliZV9ldmVudCwKPiArCS51bnN1YnNjcmliZV9ldmVudCA9IHY0bDJfZXZlbnRfc3Vi ZGV2X3Vuc3Vic2NyaWJlLAo+ICt9Owo+ICsKPiArc3RhdGljIGNvbnN0IHN0cnVjdCB2NGwyX3N1 YmRldl92aWRlb19vcHMgeHNkaXJ4c3NfdmlkZW9fb3BzID0gewo+ICsJLmdfZnJhbWVfaW50ZXJ2 YWwgPSB4c2Rpcnhzc19nX2ZyYW1lX2ludGVydmFsLAo+ICsJLnNfc3RyZWFtID0geHNkaXJ4c3Nf c19zdHJlYW0sCj4gKwkuZ19pbnB1dF9zdGF0dXMgPSB4c2Rpcnhzc19nX2lucHV0X3N0YXR1cywK PiArCS5xdWVyeV9kdl90aW1pbmdzID0geHNkaXJ4c3NfcXVlcnlfZHZfdGltaW5ncywKPiArCS5n X2R2X3RpbWluZ3MgPSB4c2Rpcnhzc19nX2R2X3RpbWluZ3MsCj4gKwkuc19kdl90aW1pbmdzID0g eHNkaXJ4c3Nfc19kdl90aW1pbmdzLAo+ICt9Owo+ICsKPiArc3RhdGljIGNvbnN0IHN0cnVjdCB2 NGwyX3N1YmRldl9wYWRfb3BzIHhzZGlyeHNzX3BhZF9vcHMgPSB7Cj4gKwkuaW5pdF9jZmcgPSB4 c2Rpcnhzc19pbml0X2NmZywKPiArCS5nZXRfZm10ID0geHNkaXJ4c3NfZ2V0X3NldF9mb3JtYXQs Cj4gKwkuc2V0X2ZtdCA9IHhzZGlyeHNzX2dldF9zZXRfZm9ybWF0LAo+ICsJLmVudW1fbWJ1c19j b2RlID0geHNkaXJ4c3NfZW51bV9tYnVzX2NvZGUsCj4gKwkuZW51bV9kdl90aW1pbmdzID0geHNk aXJ4c3NfZW51bV9kdl90aW1pbmdzLAo+ICsJLmR2X3RpbWluZ3NfY2FwID0geHNkaXJ4c3NfZHZf dGltaW5nc19jYXAsCj4gK307Cj4gKwo+ICtzdGF0aWMgY29uc3Qgc3RydWN0IHY0bDJfc3ViZGV2 X29wcyB4c2Rpcnhzc19vcHMgPSB7Cj4gKwkuY29yZSA9ICZ4c2Rpcnhzc19jb3JlX29wcywKPiAr CS52aWRlbyA9ICZ4c2Rpcnhzc192aWRlb19vcHMsCj4gKwkucGFkID0gJnhzZGlyeHNzX3BhZF9v cHMKPiArfTsKPiArCj4gKy8qIC0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0t LS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tCj4gKyAqIFBsYXRmb3JtIERl dmljZSBEcml2ZXIKPiArICovCj4gKwo+ICtzdGF0aWMgaW50IHhzZGlyeHNzX3BhcnNlX29mKHN0 cnVjdCB4c2Rpcnhzc19zdGF0ZSAqeHNkaXJ4c3MpCj4gK3sKPiArCXN0cnVjdCBkZXZpY2Vfbm9k ZSAqbm9kZSA9IHhzZGlyeHNzLT5kZXYtPm9mX25vZGU7Cj4gKwlzdHJ1Y3QgZGV2aWNlICpkZXYg PSB4c2Rpcnhzcy0+ZGV2Owo+ICsJaW50IHJldDsKPiArCj4gKwl4c2Rpcnhzcy0+aW5jbHVkZV9l ZGggPSBvZl9wcm9wZXJ0eV9yZWFkX2Jvb2wobm9kZSwgInhsbngsaW5jbHVkZS1lZGgiKTsKPiAr CWRldl9kYmcoZGV2LCAiRURIIHByb3BlcnR5ID0gJXNcbiIsCj4gKwkJeHNkaXJ4c3MtPmluY2x1 ZGVfZWRoID8gIlByZXNlbnQiIDogIkFic2VudCIpOwo+ICsKPiArCXJldCA9IG9mX3Byb3BlcnR5 X3JlYWRfdTMyKG5vZGUsICJ4bG54LGxpbmUtcmF0ZSIsICZ4c2Rpcnhzcy0+bW9kZSk7Cj4gKwlp ZiAocmV0IDwgMCkgewo+ICsJCWRldl9lcnIoZGV2LCAieGxueCxsaW5lLXJhdGUgcHJvcGVydHkg bm90IGZvdW5kXG4iKTsKPiArCQlyZXR1cm4gcmV0Owo+ICsJfQo+ICsKPiArCWlmICh4c2Rpcnhz cy0+bW9kZSAhPSBYU0RJX1NURF8zRyAmJiB4c2Rpcnhzcy0+bW9kZSAhPSBYU0RJX1NURF82RyAm Jgo+ICsJICAgIHhzZGlyeHNzLT5tb2RlICE9IFhTRElfU1REXzEyR184RFMpIHsKPiArCQlkZXZf ZXJyKGRldiwgIkludmFsaWQgTGluZSBSYXRlXG4iKTsKPiArCQlyZXR1cm4gLUVJTlZBTDsKPiAr CX0KPiArCj4gKwlkZXZfZGJnKGRldiwgIlNESSBSeCBMaW5lIFJhdGUgLyBtb2RlID0gJWRcbiIs IHhzZGlyeHNzLT5tb2RlKTsKPiArCj4gKwlyZXQgPSBvZl9wcm9wZXJ0eV9yZWFkX3UzMihub2Rl LCAieGxueCxicGMiLCAmeHNkaXJ4c3MtPmJwYyk7Cj4gKwlpZiAocmV0ID09IC1FSU5WQUwpIHsK PiArCQl4c2Rpcnhzcy0+YnBjID0gMTA7Cj4gKwkJZGV2X2RiZyhkZXYsICJzZXQgZGVmYXVsdCBi cGMgYXMgMTBcbiIpOwo+ICsJfSBlbHNlIGlmIChyZXQgPCAwKSB7Cj4gKwkJZGV2X2VycihkZXYs ICJmYWlsZWQgdG8gZ2V0IHhsbngsYnBjXG4iKTsKPiArCQlyZXR1cm4gcmV0Owo+ICsJfQo+ICsK PiArCWlmICh4c2Rpcnhzcy0+YnBjICE9IDEwICYmIHhzZGlyeHNzLT5icGMgIT0gMTIpIHsKPiAr CQlkZXZfZXJyKGRldiwgImJpdHMgcGVyIGNvbXBvbmVudD0ldS4gQ2FuIGJlIDEwIG9yIDEyIG9u bHlcbiIsCj4gKwkJCXhzZGlyeHNzLT5icGMpOwo+ICsJCXJldHVybiAtRUlOVkFMOwo+ICsJfQo+ ICsKPiArCXJldHVybiByZXQ7Cj4gK30KPiArCj4gK3N0YXRpYyBpbnQgeHNkaXJ4c3NfcHJvYmUo c3RydWN0IHBsYXRmb3JtX2RldmljZSAqcGRldikKPiArewo+ICsJc3RydWN0IHY0bDJfc3ViZGV2 ICpzdWJkZXY7Cj4gKwlzdHJ1Y3QgeHNkaXJ4c3Nfc3RhdGUgKnhzZGlyeHNzOwo+ICsJc3RydWN0 IGRldmljZSAqZGV2Owo+ICsJaW50IHJldCwgaXJxOwo+ICsJdW5zaWduZWQgaW50IG51bV9jdHJs cywgaTsKPiArCj4gKwl4c2RpcnhzcyA9IGRldm1fa3phbGxvYygmcGRldi0+ZGV2LCBzaXplb2Yo KnhzZGlyeHNzKSwgR0ZQX0tFUk5FTCk7Cj4gKwlpZiAoIXhzZGlyeHNzKQo+ICsJCXJldHVybiAt RU5PTUVNOwo+ICsKPiArCXhzZGlyeHNzLT5kZXYgPSAmcGRldi0+ZGV2Owo+ICsJZGV2ID0geHNk aXJ4c3MtPmRldjsKPiArCj4gKwlzcGluX2xvY2tfaW5pdCgmeHNkaXJ4c3MtPnNsb2NrKTsKPiAr CXJldCA9IHhzZGlyeHNzX3BhcnNlX29mKHhzZGlyeHNzKTsKPiArCWlmIChyZXQgPCAwKQo+ICsJ CXJldHVybiByZXQ7Cj4gKwo+ICsJeHNkaXJ4c3MtPmlvbWVtID0gZGV2bV9wbGF0Zm9ybV9pb3Jl bWFwX3Jlc291cmNlKHBkZXYsIDApOwo+ICsJaWYgKElTX0VSUih4c2Rpcnhzcy0+aW9tZW0pKQo+ ICsJCXJldHVybiBQVFJfRVJSKHhzZGlyeHNzLT5pb21lbSk7Cj4gKwo+ICsJeHNkaXJ4c3MtPm51 bV9jbGtzID0gQVJSQVlfU0laRSh4c2Rpcnhzc19jbGtzKTsKPiArCXhzZGlyeHNzLT5jbGtzID0g ZGV2bV9rY2FsbG9jKGRldiwgeHNkaXJ4c3MtPm51bV9jbGtzLAo+ICsJCQkJICAgICAgc2l6ZW9m KCp4c2Rpcnhzcy0+Y2xrcyksIEdGUF9LRVJORUwpOwo+ICsJaWYgKCF4c2Rpcnhzcy0+Y2xrcykK PiArCQlyZXR1cm4gLUVOT01FTTsKPiArCj4gKwlmb3IgKGkgPSAwOyBpIDwgeHNkaXJ4c3MtPm51 bV9jbGtzOyBpKyspCj4gKwkJeHNkaXJ4c3MtPmNsa3NbaV0uaWQgPSB4c2Rpcnhzc19jbGtzW2ld Owo+ICsKPiArCXJldCA9IGRldm1fY2xrX2J1bGtfZ2V0KGRldiwgeHNkaXJ4c3MtPm51bV9jbGtz LCB4c2Rpcnhzcy0+Y2xrcyk7Cj4gKwlpZiAocmV0KQo+ICsJCXJldHVybiByZXQ7Cj4gKwo+ICsJ cmV0ID0gY2xrX2J1bGtfcHJlcGFyZV9lbmFibGUoeHNkaXJ4c3MtPm51bV9jbGtzLCB4c2Rpcnhz cy0+Y2xrcyk7Cj4gKwlpZiAocmV0KQo+ICsJCXJldHVybiByZXQ7Cj4gKwo+ICsJLyogUmVzZXQg dGhlIGNvcmUgKi8KPiArCXhzZGlyeF9zdHJlYW1mbG93X2NvbnRyb2woeHNkaXJ4c3MsIGZhbHNl KTsKPiArCVhTRElSWF9DT1JFX0RJU0FCTEUoeHNkaXJ4c3MpOwo+ICsJLyogQ2xlYXIgYWxsIGlu dGVycnVwdHMgKi8KPiArCXhzZGlyeHNzX3NldCh4c2RpcnhzcywgWFNESVJYX0lTUl9SRUcsIFhT RElSWF9JTlRSX0FMTF9NQVNLKTsKPiArCXhzZGlyeHNzX2Nscih4c2RpcnhzcywgWFNESVJYX0lF Ul9SRUcsIFhTRElSWF9JTlRSX0FMTF9NQVNLKTsKPiArCXhzZGlyeHNzX3NldCh4c2Rpcnhzcywg WFNESVJYX0lFUl9SRUcsIFhTRElSWF9JTlRSX0FMTF9NQVNLKTsKPiArCVhTRElSWF9HTE9CQUxf SU5UUl9FTkFCTEUoeHNkaXJ4c3MpOwoKTG9va2luZyBoZXJlLCBpbmxpbmluZyB0aGUgbWFjcm8g d2lsbCBiZSBiZXR0ZXIuCgoJeHNkaXJ4c3Nfc2V0KHhzZGlyeHNzLCBYU0RJUlhfR0xCTF9JRVJf UkVHLCBYU0RJUlhfR0xCTF9JTlRSX0VOX01BU0spCgo+ICsJeHNkaXJ4c3Nfd3JpdGUoeHNkaXJ4 c3MsIFhTRElSWF9DUkNfRVJSQ05UX1JFRywgMHhmZmZmKTsKPiArCj4gKwkvKiBSZWdpc3RlciBp bnRlcnJ1cHQgaGFuZGxlciAqLwo+ICsJaXJxID0gcGxhdGZvcm1fZ2V0X2lycShwZGV2LCAwKTsK PiArCXJldCA9IGRldm1fcmVxdWVzdF90aHJlYWRlZF9pcnEoZGV2LCBpcnEsIE5VTEwsIHhzZGly eHNzX2lycV9oYW5kbGVyLAo+ICsJCQkJCUlSUUZfT05FU0hPVCwgZGV2X25hbWUoZGV2KSwgeHNk aXJ4c3MpOwo+ICsJaWYgKHJldCkgewo+ICsJCWRldl9lcnIoZGV2LCAiRXJyID0gJWQgSW50ZXJy dXB0IGhhbmRsZXIgcmVnIGZhaWxlZCFcbiIsCj4gKwkJCXJldCk7Cj4gKwkJZ290byBjbGtfZXJy Owo+ICsJfQo+ICsKPiArCS8qIEluaXRpYWxpemUgVjRMMiBzdWJkZXZpY2UgYW5kIG1lZGlhIGVu dGl0eSAqLwo+ICsJeHNkaXJ4c3MtPnBhZC5mbGFncyA9IE1FRElBX1BBRF9GTF9TT1VSQ0U7Cj4g Kwo+ICsJLyogSW5pdGlhbGl6ZSB0aGUgZGVmYXVsdCBmb3JtYXQgKi8KPiArCWlmICh4c2Rpcnhz cy0+YnBjID09IDEwKQo+ICsJCXhzZGlyeHNzLT5kZWZhdWx0X2Zvcm1hdC5jb2RlID0gTUVESUFf QlVTX0ZNVF9VWVZZMTBfMVgyMDsKPiArCWVsc2UKPiArCQl4c2Rpcnhzcy0+ZGVmYXVsdF9mb3Jt YXQuY29kZSA9IE1FRElBX0JVU19GTVRfVVlWWTEyXzFYMjQ7Cj4gKwl4c2Rpcnhzcy0+ZGVmYXVs dF9mb3JtYXQuZmllbGQgPSBWNEwyX0ZJRUxEX05PTkU7Cj4gKwl4c2Rpcnhzcy0+ZGVmYXVsdF9m b3JtYXQuY29sb3JzcGFjZSA9IFY0TDJfQ09MT1JTUEFDRV9SRUM3MDk7Cj4gKwl4c2Rpcnhzcy0+ ZGVmYXVsdF9mb3JtYXQud2lkdGggPSBYU0RJUlhfREVGQVVMVF9XSURUSDsKPiArCXhzZGlyeHNz LT5kZWZhdWx0X2Zvcm1hdC5oZWlnaHQgPSBYU0RJUlhfREVGQVVMVF9IRUlHSFQ7Cj4gKwl4c2Rp cnhzcy0+ZGVmYXVsdF9mb3JtYXQueGZlcl9mdW5jID0gVjRMMl9YRkVSX0ZVTkNfNzA5Owo+ICsJ eHNkaXJ4c3MtPmRlZmF1bHRfZm9ybWF0LnF1YW50aXphdGlvbiA9IFY0TDJfUVVBTlRJWkFUSU9O X0xJTV9SQU5HRTsKPiArCj4gKwl4c2Rpcnhzcy0+Zm9ybWF0ID0geHNkaXJ4c3MtPmRlZmF1bHRf Zm9ybWF0Owo+ICsKPiArCS8qIEluaXRpYWxpemUgVjRMMiBzdWJkZXZpY2UgYW5kIG1lZGlhIGVu dGl0eSAqLwo+ICsJc3ViZGV2ID0gJnhzZGlyeHNzLT5zdWJkZXY7Cj4gKwl2NGwyX3N1YmRldl9p bml0KHN1YmRldiwgJnhzZGlyeHNzX29wcyk7Cj4gKwo+ICsJc3ViZGV2LT5kZXYgPSAmcGRldi0+ ZGV2Owo+ICsJc3Ryc2NweShzdWJkZXYtPm5hbWUsIGRldl9uYW1lKGRldiksIHNpemVvZihzdWJk ZXYtPm5hbWUpKTsKPiArCj4gKwlzdWJkZXYtPmZsYWdzID0gVjRMMl9TVUJERVZfRkxfSEFTX0VW RU5UUyB8IFY0TDJfU1VCREVWX0ZMX0hBU19ERVZOT0RFOwo+ICsKPiArCXN1YmRldi0+ZW50aXR5 Lm9wcyA9ICZ4c2Rpcnhzc19tZWRpYV9vcHM7Cj4gKwo+ICsJdjRsMl9zZXRfc3ViZGV2ZGF0YShz dWJkZXYsIHhzZGlyeHNzKTsKPiArCj4gKwlyZXQgPSBtZWRpYV9lbnRpdHlfcGFkc19pbml0KCZz dWJkZXYtPmVudGl0eSwgMSwgJnhzZGlyeHNzLT5wYWQpOwo+ICsJaWYgKHJldCA8IDApCj4gKwkJ Z290byBlcnJvcjsKPiArCj4gKwkvKiBJbml0aWFsaXNlIGFuZCByZWdpc3RlciB0aGUgY29udHJv bHMgKi8KPiArCW51bV9jdHJscyA9IEFSUkFZX1NJWkUoeHNkaXJ4c3NfY3RybHMpOwo+ICsKPiAr CWlmICh4c2Rpcnhzcy0+aW5jbHVkZV9lZGgpCj4gKwkJbnVtX2N0cmxzICs9IEFSUkFZX1NJWkUo eHNkaXJ4c3NfZWRoX2N0cmxzKTsKPiArCj4gKwl2NGwyX2N0cmxfaGFuZGxlcl9pbml0KCZ4c2Rp cnhzcy0+Y3RybF9oYW5kbGVyLCBudW1fY3RybHMpOwo+ICsKPiArCWZvciAoaSA9IDA7IGkgPCBB UlJBWV9TSVpFKHhzZGlyeHNzX2N0cmxzKTsgaSsrKSB7Cj4gKwkJc3RydWN0IHY0bDJfY3RybCAq Y3RybDsKPiArCj4gKwkJZGV2X2RiZyhkZXYsICIlZCAlcyBjdHJsID0gMHgleFxuIiwgaSwgeHNk aXJ4c3NfY3RybHNbaV0ubmFtZSwKPiArCQkJeHNkaXJ4c3NfY3RybHNbaV0uaWQpOwo+ICsKPiAr CQljdHJsID0gdjRsMl9jdHJsX25ld19jdXN0b20oJnhzZGlyeHNzLT5jdHJsX2hhbmRsZXIsCj4g KwkJCQkJICAgICZ4c2Rpcnhzc19jdHJsc1tpXSwgTlVMTCk7Cj4gKwl9Cj4gKwo+ICsJaWYgKHhz ZGlyeHNzLT5pbmNsdWRlX2VkaCkgewo+ICsJCWZvciAoaSA9IDA7IGkgPCBBUlJBWV9TSVpFKHhz ZGlyeHNzX2VkaF9jdHJscyk7IGkrKykgewo+ICsJCQlzdHJ1Y3QgdjRsMl9jdHJsICpjdHJsOwo+ ICsKPiArCQkJZGV2X2RiZyhkZXYsICIlZCAlcyBjdHJsID0gMHgleFxuIiwgaSwKPiArCQkJCXhz ZGlyeHNzX2VkaF9jdHJsc1tpXS5uYW1lLAo+ICsJCQkJeHNkaXJ4c3NfZWRoX2N0cmxzW2ldLmlk KTsKPiArCj4gKwkJCWN0cmwgPSB2NGwyX2N0cmxfbmV3X2N1c3RvbSgmeHNkaXJ4c3MtPmN0cmxf aGFuZGxlciwKPiArCQkJCQkJICAgICZ4c2Rpcnhzc19lZGhfY3RybHNbaV0sCj4gKwkJCQkJCSAg ICBOVUxMKTsKPiArCQl9Cj4gKwl9Cj4gKwo+ICsJaWYgKHhzZGlyeHNzLT5jdHJsX2hhbmRsZXIu ZXJyb3IpIHsKPiArCQlkZXZfZXJyKGRldiwgImZhaWxlZCB0byBhZGQgY29udHJvbHNcbiIpOwo+ ICsJCXJldCA9IHhzZGlyeHNzLT5jdHJsX2hhbmRsZXIuZXJyb3I7Cj4gKwkJZ290byBlcnJvcjsK PiArCX0KPiArCj4gKwlzdWJkZXYtPmN0cmxfaGFuZGxlciA9ICZ4c2Rpcnhzcy0+Y3RybF9oYW5k bGVyOwo+ICsKPiArCXJldCA9IHY0bDJfY3RybF9oYW5kbGVyX3NldHVwKCZ4c2Rpcnhzcy0+Y3Ry bF9oYW5kbGVyKTsKPiArCWlmIChyZXQgPCAwKSB7Cj4gKwkJZGV2X2VycihkZXYsICJmYWlsZWQg dG8gc2V0IGNvbnRyb2xzXG4iKTsKPiArCQlnb3RvIGVycm9yOwo+ICsJfQo+ICsKPiArCXBsYXRm b3JtX3NldF9kcnZkYXRhKHBkZXYsIHhzZGlyeHNzKTsKPiArCj4gKwlyZXQgPSB2NGwyX2FzeW5j X3JlZ2lzdGVyX3N1YmRldihzdWJkZXYpOwo+ICsJaWYgKHJldCA8IDApIHsKPiArCQlkZXZfZXJy KGRldiwgImZhaWxlZCB0byByZWdpc3RlciBzdWJkZXZcbiIpOwo+ICsJCWdvdG8gZXJyb3I7Cj4g Kwl9Cj4gKwo+ICsJeHNkaXJ4c3MtPnByZXZfaXNfZnJhYyA9IC0xOwo+ICsKPiArCVhTRElSWF9D T1JFX0VOQUJMRSh4c2Rpcnhzcyk7Cj4gKwo+ICsJcmV0dXJuIDA7CgpOaXQuIEFuZSBlbXB0eSBs aW5lLgoKPiArZXJyb3I6Cj4gKwl2NGwyX2N0cmxfaGFuZGxlcl9mcmVlKCZ4c2Rpcnhzcy0+Y3Ry bF9oYW5kbGVyKTsKPiArCW1lZGlhX2VudGl0eV9jbGVhbnVwKCZzdWJkZXYtPmVudGl0eSk7Cj4g KwlYU0RJUlhfR0xPQkFMX0lOVFJfRElTQUJMRSh4c2Rpcnhzcyk7Cj4gKwl4c2Rpcnhzc19jbHIo eHNkaXJ4c3MsIFhTRElSWF9JRVJfUkVHLCBYU0RJUlhfSU5UUl9BTExfTUFTSyk7Cj4gK2Nsa19l cnI6Cj4gKwljbGtfYnVsa19kaXNhYmxlX3VucHJlcGFyZSh4c2Rpcnhzcy0+bnVtX2Nsa3MsIHhz ZGlyeHNzLT5jbGtzKTsKPiArCXJldHVybiByZXQ7Cj4gK30KPiArCj4gK3N0YXRpYyBpbnQgeHNk aXJ4c3NfcmVtb3ZlKHN0cnVjdCBwbGF0Zm9ybV9kZXZpY2UgKnBkZXYpCj4gK3sKPiArCXN0cnVj dCB4c2Rpcnhzc19zdGF0ZSAqeHNkaXJ4c3MgPSBwbGF0Zm9ybV9nZXRfZHJ2ZGF0YShwZGV2KTsK PiArCXN0cnVjdCB2NGwyX3N1YmRldiAqc3ViZGV2ID0gJnhzZGlyeHNzLT5zdWJkZXY7Cj4gKwo+ ICsJWFNESVJYX0NPUkVfRElTQUJMRSh4c2Rpcnhzcyk7Cj4gKwlYU0RJUlhfR0xPQkFMX0lOVFJf RElTQUJMRSh4c2Rpcnhzcyk7Cj4gKwl4c2Rpcnhzc19jbHIoeHNkaXJ4c3MsIFhTRElSWF9JRVJf UkVHLCBYU0RJUlhfSU5UUl9BTExfTUFTSyk7Cj4gKwl4c2Rpcnhfc3RyZWFtZmxvd19jb250cm9s KHhzZGlyeHNzLCBmYWxzZSk7Cj4gKwo+ICsJdjRsMl9hc3luY191bnJlZ2lzdGVyX3N1YmRldihz dWJkZXYpOwo+ICsJdjRsMl9jdHJsX2hhbmRsZXJfZnJlZSgmeHNkaXJ4c3MtPmN0cmxfaGFuZGxl cik7Cj4gKwltZWRpYV9lbnRpdHlfY2xlYW51cCgmc3ViZGV2LT5lbnRpdHkpOwo+ICsKPiArCWNs a19idWxrX2Rpc2FibGVfdW5wcmVwYXJlKHhzZGlyeHNzLT5udW1fY2xrcywgeHNkaXJ4c3MtPmNs a3MpOwo+ICsKPiArCXJldHVybiAwOwo+ICt9Cj4gKwo+ICtzdGF0aWMgY29uc3Qgc3RydWN0IG9m X2RldmljZV9pZCB4c2Rpcnhzc19vZl9pZF90YWJsZVtdID0gewo+ICsJeyAuY29tcGF0aWJsZSA9 ICJ4bG54LHYtc21wdGUtdWhkc2RpLXJ4LXNzLTIuMCIgfSwKPiArCXsgfQo+ICt9Owo+ICtNT0RV TEVfREVWSUNFX1RBQkxFKG9mLCB4c2Rpcnhzc19vZl9pZF90YWJsZSk7Cj4gKwo+ICtzdGF0aWMg c3RydWN0IHBsYXRmb3JtX2RyaXZlciB4c2Rpcnhzc19kcml2ZXIgPSB7Cj4gKwkuZHJpdmVyID0g ewo+ICsJCS5uYW1lCQk9ICJ4aWxpbngtc2RpcnhzcyIsCj4gKwkJLm9mX21hdGNoX3RhYmxlCT0g eHNkaXJ4c3Nfb2ZfaWRfdGFibGUsCj4gKwl9LAo+ICsJLnByb2JlCQkJPSB4c2Rpcnhzc19wcm9i ZSwKPiArCS5yZW1vdmUJCQk9IHhzZGlyeHNzX3JlbW92ZSwKPiArfTsKPiArCj4gK21vZHVsZV9w bGF0Zm9ybV9kcml2ZXIoeHNkaXJ4c3NfZHJpdmVyKTsKPiArCj4gK01PRFVMRV9BVVRIT1IoIlZp c2hhbCBTYWdhciA8dnNhZ2FyQHhpbGlueC5jb20+Iik7Cj4gK01PRFVMRV9ERVNDUklQVElPTigi WGlsaW54IFNESSBSeCBTdWJzeXN0ZW0gRHJpdmVyIik7Cj4gK01PRFVMRV9MSUNFTlNFKCJHUEwg djIiKTsKPiBkaWZmIC0tZ2l0IGEvaW5jbHVkZS91YXBpL2xpbnV4L3Y0bDItY29udHJvbHMuaCBi L2luY2x1ZGUvdWFwaS9saW51eC92NGwyLWNvbnRyb2xzLmgKPiBpbmRleCA2MjI3MTQxOGMxYmUu Ljk1MjZhNmFjYzZmNCAxMDA2NDQKPiAtLS0gYS9pbmNsdWRlL3VhcGkvbGludXgvdjRsMi1jb250 cm9scy5oCj4gKysrIGIvaW5jbHVkZS91YXBpL2xpbnV4L3Y0bDItY29udHJvbHMuaAo+IEBAIC0x OTgsNiArMTk4LDEyIEBAIGVudW0gdjRsMl9jb2xvcmZ4IHsKPiAgICovCj4gICNkZWZpbmUgVjRM Ml9DSURfVVNFUl9BVE1FTF9JU0NfQkFTRQkJKFY0TDJfQ0lEX1VTRVJfQkFTRSArIDB4MTBjMCkK PiAgCj4gKy8qCj4gKyAqIFRoZSBiYXNlIGZvciB0aGUgWGlsaW54IFNESSBSeCBkcml2ZXIgY29u dHJvbHMuCj4gKyAqIFdlIHJlc2VydmUgMTYgY29udHJvbHMgZm9yIHRoaXMgZHJpdmVyLgo+ICsg Ki8KPiArI2RlZmluZSBWNEwyX0NJRF9VU0VSX1hJTElOWF9TRElSWF9CQVNFCQkoVjRMMl9DSURf VVNFUl9CQVNFICsgMHgxMGUwKQo+ICsKPiAgLyogTVBFRy1jbGFzcyBjb250cm9sIElEcyAqLwo+ ICAvKiBUaGUgTVBFRyBjb250cm9scyBhcmUgYXBwbGljYWJsZSB0byBhbGwgY29kZWMgY29udHJv bHMKPiAgICogYW5kIHRoZSAnTVBFRycgcGFydCBvZiB0aGUgZGVmaW5lIGlzIGhpc3RvcmljYWwg Ki8KPiBkaWZmIC0tZ2l0IGEvaW5jbHVkZS91YXBpL2xpbnV4L3hpbGlueC1zZGlyeHNzLmggYi9p bmNsdWRlL3VhcGkvbGludXgveGlsaW54LXNkaXJ4c3MuaAo+IG5ldyBmaWxlIG1vZGUgMTAwNjQ0 Cj4gaW5kZXggMDAwMDAwMDAwMDAwLi4xYmNiZjU4NTJiMjIKPiAtLS0gL2Rldi9udWxsCj4gKysr IGIvaW5jbHVkZS91YXBpL2xpbnV4L3hpbGlueC1zZGlyeHNzLmgKPiBAQCAtMCwwICsxLDI4MyBA QAo+ICsvKiBTUERYLUxpY2Vuc2UtSWRlbnRpZmllcjogR1BMLTIuMCBXSVRIIExpbnV4LXN5c2Nh bGwtbm90ZSAqLwo+ICsvKgo+ICsgKiBYaWxpbnggU0RJIFJ4IFN1YnN5c3RlbSBtb2RlLCBldmVu dCwgY3VzdG9tIHRpbWluZ3MgYW5kCj4gKyAqIGZsYWcgZGVmaW5pdGlvbnMuCj4gKyAqCj4gKyAq IENvcHlyaWdodCAoQykgMjAxOSAtIDIwMjAgWGlsaW54LCBJbmMuCj4gKyAqCj4gKyAqIENvbnRh Y3RzOiBWaXNoYWwgU2FnYXIgPHZpc2hhbC5zYWdhckB4aWxpbnguY29tPgo+ICsgKi8KPiArCj4g KyNpZm5kZWYgX19VQVBJX1hJTElOWF9TRElSWFNTX0hfXwo+ICsjZGVmaW5lIF9fVUFQSV9YSUxJ TlhfU0RJUlhTU19IX18KPiArCj4gKyNpbmNsdWRlIDxsaW51eC90eXBlcy5oPgo+ICsjaW5jbHVk ZSA8bGludXgvdjRsMi1jb250cm9scy5oPgo+ICsjaW5jbHVkZSA8bGludXgvdjRsMi1kdi10aW1p bmdzLmg+Cj4gKyNpbmNsdWRlIDxsaW51eC92aWRlb2RldjIuaD4KPiArCj4gKy8qCj4gKyAqIEV2 ZW50cwo+ICsgKgo+ICsgKiBWNEwyX0VWRU5UX1hJTElOWF9TRElSWF9VTkRfT1ZSX0ZMT1c6IFZp ZGVvIGluIHRvIEFYSTQgU3RyZWFtIGNvcmUKPiArICogdW5kZXIvb3ZlcmZsb3dlZCBkdXJpbmcg YSByZXNvbHV0aW9uIG9yIGZyYW1lIHJhdGUgY2hhbmdlLgo+ICsgKi8KPiArI2RlZmluZSBWNEwy X0VWRU5UX1hJTElOWF9TRElSWF9DTEFTUyAgICAgIChWNEwyX0VWRU5UX1BSSVZBVEVfU1RBUlQg fCAweDIwMCkKPiArI2RlZmluZSBWNEwyX0VWRU5UX1hJTElOWF9TRElSWF9VTkRfT1ZSX0ZMT1cJ XAo+ICsJCQkJCShWNEwyX0VWRU5UX1hJTElOWF9TRElSWF9DTEFTUyB8IDB4MSkKPiArCj4gKyNk ZWZpbmUgWElMSU5YX1NESVJYX1VOREVSRkxPV19FVkVOVAlCSVQoMSkKPiArI2RlZmluZSBYSUxJ TlhfU0RJUlhfT1ZFUkZMT1dfRVZFTlQJQklUKDIpCj4gKy8qCj4gKyAqIFRoaXMgZW51bSBpcyB1 c2VkIHRvIHByZXBhcmUgdGhlIGJpdG1hc2sgb2YgbW9kZXMgdG8gYmUgZGV0ZWN0ZWQKPiArICov Cj4gK2VudW0gewo+ICsJWFNESVJYX01PREVfU0RfT0ZGU0VUID0gMCwKPiArCVhTRElSWF9NT0RF X0hEX09GRlNFVCwKPiArCVhTRElSWF9NT0RFXzNHQV9PRkZTRVQsCj4gKwlYU0RJUlhfTU9ERV8z R0JfT0ZGU0VULAo+ICsJWFNESVJYX01PREVfNkdfT0ZGU0VULAo+ICsJWFNESVJYX01PREVfMTJH SV9PRkZTRVQsCj4gKwlYU0RJUlhfTU9ERV8xMkdGX09GRlNFVCwKPiArCVhTRElSWF9NT0RFX05V TV9TVVBQT1JURUQsCj4gK307Cj4gKwo+ICsjZGVmaW5lIFhTRElSWF9ERVRFQ1RfQUxMX01PREVT CQkoQklUKFhTRElSWF9NT0RFX1NEX09GRlNFVCkgfCBcCj4gKwkJCQkJQklUKFhTRElSWF9NT0RF X0hEX09GRlNFVCkgfCBcCj4gKwkJCQkJQklUKFhTRElSWF9NT0RFXzNHQV9PRkZTRVQpIHwgXAo+ ICsJCQkJCUJJVChYU0RJUlhfTU9ERV8zR0JfT0ZGU0VUKSB8IFwKPiArCQkJCQlCSVQoWFNESVJY X01PREVfNkdfT0ZGU0VUKSB8IFwKPiArCQkJCQlCSVQoWFNESVJYX01PREVfMTJHSV9PRkZTRVQp IHwgXAo+ICsJCQkJCUJJVChYU0RJUlhfTU9ERV8xMkdGX09GRlNFVCkpCj4gKwo+ICsvKgo+ICsg KiBFREggLSBFcnJvciBEZXRlY3Rpb24gYW5kIEhhbmRsaW5nLgo+ICsgKiBJbiB0aGUgU0QtU0RJ IG1vZGUsIHRoZSBVSEQtU0RJIGNvcmUgZnVsbHkgc3VwcG9ydHMgUlAgMTY1Lgo+ICsgKiBUaGUg Yml0bWFzayBpcyBuYW1lZCBhcyBYU0RJUlhfRURIX0VSUkNOVF9YWF9ZWV9FUlIgZXhjZXB0Cj4g KyAqIGZvciBwYWNrZXQgY2hlY2tzdW0gZXJyb3IuCj4gKyAqCj4gKyAqIFhYIC0gRURIIEVycm9y IFR5cGVzCj4gKyAqIEFOQyAtIEFuY2lsbGFyeSBEYXRhIFBhY2tldCBFcnJvcnMKPiArICogRkYg LSBGdWxsIEZpZWxkIEVycm9ycwo+ICsgKiBBUCAtIEFjdGl2ZSBQb3J0aW9uIEVycm9ycwo+ICsg Kgo+ICsgKiBZWSAtIEVycm9yIEZsYWdzCj4gKyAqIEVESCAtIGVycm9yIGRldGVjdGVkIGhlcmUK PiArICogRURBIC0gZXJyb3IgRGV0ZWN0ZWQgYWxyZWFkeQo+ICsgKiBJREggLSBpbnRlcm5hbCBl cnJvciBkZXRlY3RlZCBoZXJlCj4gKyAqIElEQSAtIGludGVybmFsIGVycm9yIGRldGVjdGVkIGFs cmVhZHkKPiArICogVUVTIC0gdW5rbm93biBlcnJvciBzdGF0dXMKPiArICoKPiArICogUmVmZXIg dG8gU2VjIDQuMyBFcnJvciBGbGFncyBpbiBSUCAxNjUtMTk5NCBmb3IgZGV0YWlscwo+ICsgKi8K PiArCj4gKyNkZWZpbmUgWFNESVJYX0VESF9FUlJDTlRfQU5DX0VESF9FUlIJCUJJVCgwKQo+ICsj ZGVmaW5lIFhTRElSWF9FREhfRVJSQ05UX0FOQ19FREFfRVJSCQlCSVQoMSkKPiArI2RlZmluZSBY U0RJUlhfRURIX0VSUkNOVF9BTkNfSURIX0VSUgkJQklUKDIpCj4gKyNkZWZpbmUgWFNESVJYX0VE SF9FUlJDTlRfQU5DX0lEQV9FUlIJCUJJVCgzKQo+ICsjZGVmaW5lIFhTRElSWF9FREhfRVJSQ05U X0FOQ19VRVNfRVJSCQlCSVQoNCkKPiArI2RlZmluZSBYU0RJUlhfRURIX0VSUkNOVF9GRl9FREhf RVJSCQlCSVQoNSkKPiArI2RlZmluZSBYU0RJUlhfRURIX0VSUkNOVF9GRl9FREFfRVJSCQlCSVQo NikKPiArI2RlZmluZSBYU0RJUlhfRURIX0VSUkNOVF9GRl9JREhfRVJSCQlCSVQoNykKPiArI2Rl ZmluZSBYU0RJUlhfRURIX0VSUkNOVF9GRl9JREFfRVJSCQlCSVQoOCkKPiArI2RlZmluZSBYU0RJ UlhfRURIX0VSUkNOVF9GRl9VRVNfRVJSCQlCSVQoOSkKPiArI2RlZmluZSBYU0RJUlhfRURIX0VS UkNOVF9BUF9FREhfRVJSCQlCSVQoMTApCj4gKyNkZWZpbmUgWFNESVJYX0VESF9FUlJDTlRfQVBf RURBX0VSUgkJQklUKDExKQo+ICsjZGVmaW5lIFhTRElSWF9FREhfRVJSQ05UX0FQX0lESF9FUlIJ CUJJVCgxMikKPiArI2RlZmluZSBYU0RJUlhfRURIX0VSUkNOVF9BUF9JREFfRVJSCQlCSVQoMTMp Cj4gKyNkZWZpbmUgWFNESVJYX0VESF9FUlJDTlRfQVBfVUVTX0VSUgkJQklUKDE0KQo+ICsjZGVm aW5lIFhTRElSWF9FREhfRVJSQ05UX1BLVF9DSEtTVU1fRVJSCUJJVCgxNSkKPiArCj4gKyNkZWZp bmUgWFNESVJYX0VESF9BTExFUlJfTUFTSwkJMHhGRkZGCgpOaXQsIGxvd2VyY2FzZSBmb3IgaGV4 IHZhbHVlcy4KClRoYW5rcyEKLWh5dW4KCj4gKwo+ICsvKgo+ICsgKiBWNEwyIENvbnRyb2xzIC0g V2UgcmVzZXJ2ZWQgMTYgY29udHJvbHMgZm9yIHRoaXMgZHJpdmVyLgo+ICsgKgo+ICsgKiBUaGUg VjRMMl9DSURfWElMSU5YX1NESVJYX0VESF8qIGNvbnRyb2xzIGFyZSBwcmVzZW50IG9ubHkgaWYK PiArICogRURIIGlzIGVuYWJsZWQuCj4gKyAqIFRoZSBjb250cm9scyB3aGljaCBjYW4gYmUgc2V0 IHNob3VsZCBvbmx5IGJlIHNldCBiZWZvcmUgZW5hYmxpbmcKPiArICogc3RyZWFtaW5nLiBUaGUg Y29udHJvbHMgd2hpY2ggY2FuIGJlIGdvdCBzaG91bGQgYmUgY2FsbGVkIHdoaWxlCj4gKyAqIHN0 cmVhbWluZyB0byBnZXQgY29ycmVjdCB2YWx1ZXMuCj4gKyAqIFRoZSBWNEwyX0NJRF9YSUxJTlhf U0RJUlhfTU9ERV9ERVRFQ1QgY2FuIGJlIGNhbGxlZCB3aGVuIHF1ZXJ5IGR2IHRpbWluZwo+ICsg KiByZXR1cm5zIGEgdmFsaWQgdGltaW5nLgo+ICsgKi8KPiArCj4gKy8qCj4gKyAqIEZyYW1lciBD b250cm9sIHRvIGVuYWJsZSBvciBkaXNhYmxlIHRoZSBmcmFtZXIuIFdoZW4gdGhpcyBpcyBzZXQs IHRoZSBmcmFtZXIKPiArICogYXV0b21hdGljYWxseSByZWFkanVzdHMgdGhlIG91dHB1dCB3b3Jk IGFsaWdubWVudCB0byBtYXRjaCB0aGUgYWxpZ25tZW50IG9mCj4gKyAqIGVhY2ggdGltaW5nIHJl ZmVyZW5jZSBzaWduYWwoVFJTKS4gTm9ybWFsbHkgdGhpcyBzaG91bGQgYmUgc2V0LiBCdXQgdXNl ciBtYXkKPiArICogY29udHJvbCB0aGlzIGlucHV0IHRvIGltcGxlbWVudCBUUlMgZmlsdGVyaW5n IHRvIHByZXZlbnQgYSBzaWduYWwgbWlzYWxpZ25lZAo+ICsgKiBUUlMgZnJvbSBjYXVzaW5nIGVy cm9uZW91cyBhbGlnbm1lbnQgY2hhbmdlcy4KPiArICogUmVmZXIgdG8gUEcyMDUgcnhfZnJhbWVf ZW4gZm9yIG1vcmUgZGV0YWlscy4KPiArICovCj4gKyNkZWZpbmUgVjRMMl9DSURfWElMSU5YX1NE SVJYX0ZSQU1FUgkJKFY0TDJfQ0lEX1VTRVJfWElMSU5YX1NESVJYX0JBU0UgKyAxKQo+ICsKPiAr LyoKPiArICogVmlkZW8gTG9jayBXaW5kb3cgQ29udHJvbCB0byBzZXQgdGhlIHZpZGVvIGxvY2sg d2luZG93IHZhbHVlCj4gKyAqIFRoaXMgaXMgdGhlIGFtb3VudCBvZiB0aW1lIHRoZSBtb2RlIGFu ZCB0cmFuc3BvcnQgc3RyZWFtIG5lZWQKPiArICogdG8gYmUgbG9ja2VkIGJlZm9yZSBhIHZpZGVv IGxvY2sgaW50ZXJydXB0IG9jY3Vycy4KPiArICovCj4gKyNkZWZpbmUgVjRMMl9DSURfWElMSU5Y X1NESVJYX1ZJRExPQ0tfV0lORE9XCShWNEwyX0NJRF9VU0VSX1hJTElOWF9TRElSWF9CQVNFICsg MikKPiArCj4gKy8qCj4gKyAqIEVESCBFcnJvciBNYXNrIENvbnRyb2wgdG8gZW5hYmxlIEVESCBl cnJvciBjb3VudAo+ICsgKiBUaGlzIGNvbnRyb2wgdGFrZXMgaW4gdGhlIGJpdG1hc2sgb2YgWFNE SVJYX0VESF9FUlJDTlRfKl9FUlIgdG8gZW5hYmxlIGNvdW50aW5nCj4gKyAqIHN1Y2ggZXJyb3Jz Lgo+ICsgKi8KPiArI2RlZmluZSBWNEwyX0NJRF9YSUxJTlhfU0RJUlhfRURIX0VSUk9SX1NPVVJD RVMJKFY0TDJfQ0lEX1VTRVJfWElMSU5YX1NESVJYX0JBU0UgKyAzKQo+ICsKPiArLyoKPiArICog TW9kZSBzZWFyY2ggQ29udHJvbCB0byBwYXNzIHRoZSBiaXQgbWFzayBvZiBtb2RlcyB0byBkZXRl Y3QuCj4gKyAqIElmIG9ubHkgMSBiaXQgaXMgc2V0LCB0aGUgZHJpdmVyIHByb2dyYW1zIElQIHRv IGJlIGluIGZpeGVkIG1vZGUgZWxzZQo+ICsgKiBpbiBtdWx0aSBkZXRlY3Rpb24gbW9kZS4KPiAr ICoKPiArICogU2V0IHRoaXMgd2hlbiBub3Qgc3RyZWFtaW5nLgo+ICsgKgo+ICsgKiBiaXQgMCBz ZXQgdG8gZGV0ZWN0IFNEICBtb2RlLAo+ICsgKiBiaXQgMSBzZXQgdG8gZGV0ZWN0IEhEICBtb2Rl LAo+ICsgKiBiaXQgMiBzZXQgdG8gZGV0ZWN0IDNHQSBtb2RlLAo+ICsgKiBiaXQgMyBzZXQgdG8g ZGV0ZWN0IDNHQiBtb2RlLAo+ICsgKiBiaXQgNCBzZXQgdG8gZGV0ZWN0IDZHICBtb2RlLAo+ICsg KiBiaXQgNSBzZXQgdG8gZGV0ZWN0IDEyRyBpbnRlZ2VyIGZyYW1lIHJhdGUgbW9kZSwKPiArICog Yml0IDYgc2V0IHRvIGRldGVjdCAxMkcgZnJhY3Rpb25hbCBmcmFtZSByYXRlIG1vZGUsCj4gKyAq Lwo+ICsjZGVmaW5lIFY0TDJfQ0lEX1hJTElOWF9TRElSWF9TRUFSQ0hfTU9ERVMJKFY0TDJfQ0lE X1VTRVJfWElMSU5YX1NESVJYX0JBU0UgKyA0KQo+ICsKPiArLyoKPiArICogR2V0IERldGVjdGVk IFNESSBNb2RlIGNvbnRyb2wgKHJlYWQgb25seSkKPiArICoKPiArICogQ29udHJvbCBWYWx1ZSAt IE1vZGUgZGV0ZWN0ZWQKPiArICogICAgICAgIDAgICAgICAtICAgICBTRAo+ICsgKiAgICAgICAg MSAgICAgIC0gICAgIEhECj4gKyAqICAgICAgICAyICAgICAgLSAgICAgM0dBCj4gKyAqICAgICAg ICAzICAgICAgLSAgICAgM0dCCj4gKyAqICAgICAgICA0ICAgICAgLSAgICAgNkcKPiArICogICAg ICAgIDUgICAgICAtICAgICAxMkcgaW50ZWdlciBmcmFtZSByYXRlCj4gKyAqICAgICAgICA2ICAg ICAgLSAgICAgMTJHIGZyYWN0aW9uYWwgZnJhbWUgcmF0ZQo+ICsgKi8KPiArI2RlZmluZSBWNEwy X0NJRF9YSUxJTlhfU0RJUlhfTU9ERV9ERVRFQ1QJKFY0TDJfQ0lEX1VTRVJfWElMSU5YX1NESVJY X0JBU0UgKyA1KQo+ICsKPiArLyogR2V0IG51bWJlciBvZiBDUkMgZXJyb3JzIHN0YXR1cyBjb250 cm9sCj4gKyAqCj4gKyAqIFdoZW4gYSBDUkMgaXMgZGV0ZWN0ZWQgb24gYSBsaW5lLCB0aGUgQ1JD IGVycm9yIHNpZ25hbCBvZiB0aGF0IGRhdGEgc3RyZWFtCj4gKyAqIGJlY29tZXMgYXNzZXJ0ZWQg c3RhcnRpbmcgYSBmZXcgY2xvY2sgY3ljbGVzIGFmdGVyIHRoZSBsYXN0IENSQyB3b3JkIGlzCj4g KyAqIG91dHB1dCBvbiB0aGUgZGF0YSBzdHJlYW0gcG9ydHMgZm9sbG93aW5nIHRoZSBFQVYgdGhh dCBlbmRzIHRoZSBsaW5lCj4gKyAqIGNvbnRhaW5pbmcgdGhlIGVycm9yLiBUaGUgQ1JDIHNpZ25h bCByZW1haW5zIGFzc2VydGVkIGZvciBvbmUgbGluZSB0aW1lLgo+ICsgKgo+ICsgKiBUaGUgTFNC IDE2IGJpdHMgb2YgdmFsdWUgcmV0dXJuZWQgYnkgdGhzaSBjb250cm9sIHJlcHJlc2VudCB0aGUg ZXJyb3IKPiArICogc2lnbmFsIG9uIGVhY2ggb2YgMTYgZGF0YSBzdHJlYW1zLiBUaGUgTVNCIDE2 IGJpdHMgY29udGFpbnMgdGhlIGFjY3VtdWxhdGVkCj4gKyAqIGVycm9yIGNvdW50Lgo+ICsgKgo+ ICsgKiBSZWZlciB0byBQRzIwNSByeF9jcmNfZXJyX2RzWCAoWCA9IDEgdG8gMTYpIGRlc2NyaXB0 aW9uIGZvciBkZXRhaWxzLgo+ICsgKi8KPiArI2RlZmluZSBWNEwyX0NJRF9YSUxJTlhfU0RJUlhf Q1JDCQkoVjRMMl9DSURfVVNFUl9YSUxJTlhfU0RJUlhfQkFTRSArIDYpCj4gKwo+ICsvKgo+ICsg KiBHZXQgRURIIGVycm9yIGNvdW50IGNvbnRyb2wKPiArICoKPiArICogUmVhZGluZyB0aGlzIGNv bnRyb2wgd2lsbCBnaXZlIHRoZSBudW1iZXIgb2YgRURIIGVycm9ycyBvY2N1cnJlZCBiYXNlZAo+ ICsgKiBvbiB0aGUgYml0bWFzayBwYXNzZWQgaW4gVjRMMl9DSURfWElMSU5YX1NESVJYX0VESF9F UlJPUl9TT1VSQ0VTLgo+ICsgKgo+ICsgKiBJdCBpbmNyZW1lbnRzIG9uY2UgcGVyIGZpZWxkIHdo ZW4gYW55IG9mIHRoZSBlcnJvciBjb25kaXRpb25zIGVuYWJsZWQgYnkKPiArICogdGhlIFJYX0VE SF9FUlJDTlRfRU4gcmVnaXN0ZXIgYml0KHMpIG9jY3VyIGR1cmluZyB0aGF0IGZpZWxkLgo+ICsg Kgo+ICsgKiBSZWZlciB0byBQRzIwNSByeF9lZGhfZXJyY250Cj4gKyAqLwo+ICsjZGVmaW5lIFY0 TDJfQ0lEX1hJTElOWF9TRElSWF9FREhfRVJSQ05UCShWNEwyX0NJRF9VU0VSX1hJTElOWF9TRElS WF9CQVNFICsgNykKPiArCj4gKy8qCj4gKyAqIEdldCBFREggc3RhdHVzIGNvbnRyb2wKPiArICoK PiArICogVGhpcyBjb250cm9sIHJldHVybnMgdGhlIFJYX0VESF9TVFMgcmVnaXN0ZXIgY29udGVu dHMuCj4gKyAqIFJlZmVyIHRvIFBHMjkwIHJlZ2lzdGVyIHNwYWNlIHNlY3Rpb24gZm9yIG1vcmUg ZGV0YWlscy4KPiArICovCj4gKyNkZWZpbmUgVjRMMl9DSURfWElMSU5YX1NESVJYX0VESF9TVEFU VVMJKFY0TDJfQ0lEX1VTRVJfWElMSU5YX1NESVJYX0JBU0UgKyA4KQo+ICsKPiArLyogR2V0IFRy YW5zcG9ydCBJbnRlcmxhY2VkIHN0YXR1cyB3aGV0aGVyIGl0IGlzIGludGVybGFjZWQgb3Igbm90 ICovCj4gKyNkZWZpbmUgVjRMMl9DSURfWElMSU5YX1NESVJYX1RTX0lTX0lOVEVSTEFDRUQJKFY0 TDJfQ0lEX1VTRVJfWElMSU5YX1NESVJYX0JBU0UgKyA5KQo+ICsKPiArLyoKPiArICogWGlsaW54 IERWIHRpbWluZ3MKPiArICogVE9ETyAtIFJlbW92ZSB0aGVzZSBvbmNlIHRoZXkgYXJlIGluIHY0 bDItZHYtdGltaW5ncy5oCj4gKyAqLwo+ICsjZGVmaW5lIFhMTlhfVjRMMl9EVl9CVF8yMDQ4WDEw ODBQMjQgeyBcCj4gKwkudHlwZSA9IFY0TDJfRFZfQlRfNjU2XzExMjAsIFwKPiArCVY0TDJfSU5J VF9CVF9USU1JTkdTKDIwNDgsIDEwODAsIDAsIFwKPiArCQlWNEwyX0RWX0hTWU5DX1BPU19QT0wg fCBWNEwyX0RWX1ZTWU5DX1BPU19QT0wsIFwKPiArCQk3NDI1MDAwMCwgNTEwLCA0NCwgMTQ4LCA0 LCA1LCAzNiwgMCwgMCwgMCwgXAo+ICsJCVY0TDJfRFZfQlRfU1REX1NESSkgXAo+ICt9Cj4gKwo+ ICsjZGVmaW5lIFhMTlhfVjRMMl9EVl9CVF8yMDQ4WDEwODBQMjUgeyBcCj4gKwkudHlwZSA9IFY0 TDJfRFZfQlRfNjU2XzExMjAsIFwKPiArCVY0TDJfSU5JVF9CVF9USU1JTkdTKDIwNDgsIDEwODAs IDAsIFwKPiArCQlWNEwyX0RWX0hTWU5DX1BPU19QT0wgfCBWNEwyX0RWX1ZTWU5DX1BPU19QT0ws IFwKPiArCQk3NDI1MDAwMCwgNDAwLCA0NCwgMTQ4LCA0LCA1LCAzNiwgMCwgMCwgMCwgXAo+ICsJ CVY0TDJfRFZfQlRfU1REX1NESSkgXAo+ICt9Cj4gKwo+ICsjZGVmaW5lIFhMTlhfVjRMMl9EVl9C VF8yMDQ4WDEwODBQMzAgeyBcCj4gKwkudHlwZSA9IFY0TDJfRFZfQlRfNjU2XzExMjAsIFwKPiAr CVY0TDJfSU5JVF9CVF9USU1JTkdTKDIwNDgsIDEwODAsIDAsIFwKPiArCQlWNEwyX0RWX0hTWU5D X1BPU19QT0wgfCBWNEwyX0RWX1ZTWU5DX1BPU19QT0wsIFwKPiArCQk3NDI1MDAwMCwgNjYsIDIw LCA2NiwgNCwgNSwgMzYsIDAsIDAsIDAsIFwKPiArCQlWNEwyX0RWX0JUX1NURF9TREkpIFwKPiAr fQo+ICsKPiArI2RlZmluZSBYTE5YX1Y0TDJfRFZfQlRfMjA0OFgxMDgwSTQ4IHsgXAo+ICsJLnR5 cGUgPSBWNEwyX0RWX0JUXzY1Nl8xMTIwLCBcCj4gKwlWNEwyX0lOSVRfQlRfVElNSU5HUygyMDQ4 LCAxMDgwLCAxLCBcCj4gKwkJVjRMMl9EVl9IU1lOQ19QT1NfUE9MIHwgVjRMMl9EVl9WU1lOQ19Q T1NfUE9MLCBcCj4gKwkJNzQyNTAwMDAsIDMyOSwgNDQsIDMyOSwgMiwgNSwgMTUsIDMsIDUsIDE1 LCBcCj4gKwkJVjRMMl9EVl9CVF9TVERfU0RJKSBcCj4gK30KPiArCj4gKyNkZWZpbmUgWExOWF9W NEwyX0RWX0JUXzIwNDhYMTA4MEk1MCB7IFwKPiArCS50eXBlID0gVjRMMl9EVl9CVF82NTZfMTEy MCwgXAo+ICsJVjRMMl9JTklUX0JUX1RJTUlOR1MoMjA0OCwgMTA4MCwgMSwgXAo+ICsJCVY0TDJf RFZfSFNZTkNfUE9TX1BPTCB8IFY0TDJfRFZfVlNZTkNfUE9TX1BPTCwgXAo+ICsJCTc0MjUwMDAw LCAyNzQsIDQ0LCAyNzQsIDIsIDUsIDE1LCAzLCA1LCAxNSwgXAo+ICsJCVY0TDJfRFZfQlRfU1RE X1NESSkgXAo+ICt9Cj4gKwo+ICsjZGVmaW5lIFhMTlhfVjRMMl9EVl9CVF8yMDQ4WDEwODBJNjAg eyBcCj4gKwkudHlwZSA9IFY0TDJfRFZfQlRfNjU2XzExMjAsIFwKPiArCVY0TDJfSU5JVF9CVF9U SU1JTkdTKDIwNDgsIDEwODAsIDEsIFwKPiArCQlWNEwyX0RWX0hTWU5DX1BPU19QT0wgfCBWNEwy X0RWX1ZTWU5DX1BPU19QT0wsIFwKPiArCQk3NDI1MDAwMCwgNjYsIDIwLCA2NiwgMiwgNSwgMTUs IDMsIDUsIDE1LCBcCj4gKwkJVjRMMl9EVl9CVF9TVERfU0RJKSBcCj4gK30KPiArCj4gKyNkZWZp bmUgWExOWF9WNEwyX0RWX0JUXzIwNDhYMTA4MFA0OCB7IFwKPiArCS50eXBlID0gVjRMMl9EVl9C VF82NTZfMTEyMCwgXAo+ICsJVjRMMl9JTklUX0JUX1RJTUlOR1MoMjA0OCwgMTA4MCwgMCwgXAo+ ICsJCVY0TDJfRFZfSFNZTkNfUE9TX1BPTCB8IFY0TDJfRFZfVlNZTkNfUE9TX1BPTCwgXAo+ICsJ CTE0ODUwMDAwMCwgNTEwLCA0NCwgMTQ4LCA0LCA1LCAzNiwgMCwgMCwgMCwgXAo+ICsJCVY0TDJf RFZfQlRfU1REX1NESSkgXAo+ICt9Cj4gKwo+ICsjZGVmaW5lIFhMTlhfVjRMMl9EVl9CVF8yMDQ4 WDEwODBQNTAgeyBcCj4gKwkudHlwZSA9IFY0TDJfRFZfQlRfNjU2XzExMjAsIFwKPiArCVY0TDJf SU5JVF9CVF9USU1JTkdTKDIwNDgsIDEwODAsIDAsIFwKPiArCQlWNEwyX0RWX0hTWU5DX1BPU19Q T0wgfCBWNEwyX0RWX1ZTWU5DX1BPU19QT0wsIFwKPiArCQkxNDg1MDAwMDAsIDQwMCwgNDQsIDE0 OCwgNCwgNSwgMzYsIDAsIDAsIDAsIFwKPiArCQlWNEwyX0RWX0JUX1NURF9TREkpIFwKPiArfQo+ ICsKPiArI2RlZmluZSBYTE5YX1Y0TDJfRFZfQlRfMjA0OFgxMDgwUDYwIHsgXAo+ICsJLnR5cGUg PSBWNEwyX0RWX0JUXzY1Nl8xMTIwLCBcCj4gKwlWNEwyX0lOSVRfQlRfVElNSU5HUygyMDQ4LCAx MDgwLCAwLCBcCj4gKwkJVjRMMl9EVl9IU1lOQ19QT1NfUE9MIHwgVjRMMl9EVl9WU1lOQ19QT1Nf UE9MLCBcCj4gKwkJMTQ4NTAwMDAwLCA4OCwgNDQsIDIwLCA0LCA1LCAzNiwgMCwgMCwgMCwgXAo+ ICsJCVY0TDJfRFZfQlRfU1REX1NESSkgXAo+ICt9Cj4gKwo+ICsjZGVmaW5lIFhMTlhfVjRMMl9E Vl9CVF8xOTIwWDEwODBJNDggeyBcCj4gKwkudHlwZSA9IFY0TDJfRFZfQlRfNjU2XzExMjAsIFwK PiArCVY0TDJfSU5JVF9CVF9USU1JTkdTKDE5MjAsIDEwODAsIDEsIFwKPiArCQlWNEwyX0RWX0hT WU5DX1BPU19QT0wgfCBWNEwyX0RWX1ZTWU5DX1BPU19QT0wsIFwKPiArCQkxNDg1MDAwMDAsIDM3 MSwgODgsIDM3MSwgMiwgNSwgMTUsIDMsIDUsIDE1LCBcCj4gKwkJVjRMMl9EVl9CVF9TVERfU0RJ KSBcCj4gK30KPiArCj4gKyNlbmRpZiAvKiBfX1VBUElfWElMSU5YX1NESVJYU1NfSF9fICovCj4g LS0gCj4gMi4yMS4wCj4gCj4gCgpfX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f X19fX19fX19fXwpsaW51eC1hcm0ta2VybmVsIG1haWxpbmcgbGlzdApsaW51eC1hcm0ta2VybmVs QGxpc3RzLmluZnJhZGVhZC5vcmcKaHR0cDovL2xpc3RzLmluZnJhZGVhZC5vcmcvbWFpbG1hbi9s aXN0aW5mby9saW51eC1hcm0ta2VybmVsCg== From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-11.5 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,USER_AGENT_SANE_1 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8698BC43467 for ; Wed, 15 Jul 2020 22:46:14 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 5E6A62070E for ; Wed, 15 Jul 2020 22:46:14 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=xilinx.onmicrosoft.com header.i=@xilinx.onmicrosoft.com header.b="YLhlEu9f" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728057AbgGOWqJ (ORCPT ); Wed, 15 Jul 2020 18:46:09 -0400 Received: from mail-eopbgr690044.outbound.protection.outlook.com ([40.107.69.44]:29575 "EHLO NAM04-CO1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1727971AbgGOWqI (ORCPT ); Wed, 15 Jul 2020 18:46:08 -0400 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=SlRagE1Rp/YbtEl670aemNGT3fUWLifOjuCgH7pSNgwb14ryDJO81Pnvgt5ktqE+lu+XEvLBs/1zkhjuIyQnjaye1tyv5nB7VrfRoyJTd49XkEtt/yQwJSmUZzJHNRWO0btUHMoq1m+v7i4OY6jG8LQaujGOXnykkj+xTuMhYgmvZF9GYBoupuyKOBf1uccZGlNGsRH6GO6F8Lc3rO6kaH+YuUSRL9xeF2EhwxdGPa0CoZUq/GxVCJfKv9omeju4Ig6hkxVtcK1jGeXCybjrXiRRSKW+uIfs+jWUKj4mmWIMVoHtIXYmtdHf/0c0FNVqP+7IPz83AqLH7y2KzKXRjA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=h6i4xwLiTh1MUghqkOvaUnXTiyDy2X/KyD9b1tLUQWE=; b=GOOHuE8k6EV37k2V08zhKJR3rcnEnAnOOH01JxJ2hnWC44wdYlpvYO0+i3BeR7eJM/qyXim7z7KMa2HJ4ZRGUYqhCmR3dwvpHiXcCce6xRK8/KTrJrJnxk7/KYtYIp/jvUuVGZnFzLertbrXmWZEG0MMZfkEgPZGXE6ClxttDH+ceVqMj3LgjXRcPaiAXc3iqfQg454XP1L1Oc8Tb/uq35sO/RJVN37JUjOs1lA2RGPGHJNyDxFQZlj3n/o1XZxf2TZsXVNHBjL7k7kckz/IFJ2i/jaNckQJbzNzevB25v5d4LWmK3ZtPcDBkBylJlu8oWT4EZOX48hfD6aIqwHGow== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 149.199.60.83) smtp.rcpttodomain=xs4all.nl smtp.mailfrom=xilinx.com; dmarc=bestguesspass action=none header.from=xilinx.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=xilinx.onmicrosoft.com; s=selector2-xilinx-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=h6i4xwLiTh1MUghqkOvaUnXTiyDy2X/KyD9b1tLUQWE=; b=YLhlEu9f2UQP1B3cjsv0qbChqJkjeG65/mOz1HjZzncEmq/gQuLgRxaUteQVKmoqwVw/ecXKqpTPaujeuwY9z7IdoxT4cQy6hiyELZvHwYjs7yPI/MsCMvvWcEcB65kfeehBX7cJiIPTo5FuPwE8duzE6vu6zedHx/upHmXT3qM= Received: from DM3PR12CA0101.namprd12.prod.outlook.com (2603:10b6:0:55::21) by CY4PR02MB2501.namprd02.prod.outlook.com (2603:10b6:903:72::11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3174.22; Wed, 15 Jul 2020 22:45:49 +0000 Received: from CY1NAM02FT058.eop-nam02.prod.protection.outlook.com (2603:10b6:0:55:cafe::ec) by DM3PR12CA0101.outlook.office365.com (2603:10b6:0:55::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3195.18 via Frontend Transport; Wed, 15 Jul 2020 22:45:48 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 149.199.60.83) smtp.mailfrom=xilinx.com; xs4all.nl; dkim=none (message not signed) header.d=none;xs4all.nl; dmarc=bestguesspass action=none header.from=xilinx.com; Received-SPF: Pass (protection.outlook.com: domain of xilinx.com designates 149.199.60.83 as permitted sender) receiver=protection.outlook.com; client-ip=149.199.60.83; helo=xsj-pvapsmtpgw01; Received: from xsj-pvapsmtpgw01 (149.199.60.83) by CY1NAM02FT058.mail.protection.outlook.com (10.152.74.149) with Microsoft SMTP Server id 15.20.3195.18 via Frontend Transport; Wed, 15 Jul 2020 22:45:47 +0000 Received: from [149.199.38.66] (port=45491 helo=xsj-pvapsmtp01) by xsj-pvapsmtpgw01 with esmtp (Exim 4.90) (envelope-from ) id 1jvq8C-0004lZ-5d; Wed, 15 Jul 2020 15:44:04 -0700 Received: from [127.0.0.1] (helo=localhost) by xsj-pvapsmtp01 with smtp (Exim 4.63) (envelope-from ) id 1jvq9r-0003ij-FG; Wed, 15 Jul 2020 15:45:47 -0700 Received: from xsj-pvapsmtp01 (mail.xilinx.com [149.199.38.66] (may be forged)) by xsj-smtp-dlp1.xlnx.xilinx.com (8.13.8/8.13.1) with ESMTP id 06FMjgk0030737; Wed, 15 Jul 2020 15:45:42 -0700 Received: from [172.19.2.244] (helo=xsjhyunkubuntu) by xsj-pvapsmtp01 with esmtp (Exim 4.63) (envelope-from ) id 1jvq9m-0003hq-KM; Wed, 15 Jul 2020 15:45:42 -0700 Received: by xsjhyunkubuntu (Postfix, from userid 13638) id D00172C6BB2; Wed, 15 Jul 2020 15:42:49 -0700 (PDT) Date: Wed, 15 Jul 2020 15:42:49 -0700 From: Hyun Kwon To: Vishal Sagar Cc: "laurent.pinchart@ideasonboard.com" , "hverkuil@xs4all.nl" , "mchehab@kernel.org" , "robh+dt@kernel.org" , "mark.rutland@arm.com" , Michal Simek , "linux-media@vger.kernel.org" , "devicetree@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" , "joe@perches.com" , Sandip Kothari , Dinesh Kumar , Vishal Sagar Subject: Re: [PATCH v3 3/3] media: v4l: xilinx: Add Xilinx UHD-SDI Rx Subsystem driver Message-ID: <20200715224248.GA3490@xilinx.com> References: <20200618053304.14551-1-vishal.sagar@xilinx.com> <20200618053304.14551-4-vishal.sagar@xilinx.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: <20200618053304.14551-4-vishal.sagar@xilinx.com> User-Agent: Mutt/1.5.24 (2015-08-30) Content-Transfer-Encoding: quoted-printable X-RCIS-Action: ALLOW X-TM-AS-Product-Ver: IMSS-7.1.0.1224-8.2.0.1013-23620.005 X-TM-AS-User-Approved-Sender: Yes;Yes X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-Forefront-Antispam-Report: CIP:149.199.60.83;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:xsj-pvapsmtpgw01;PTR:unknown-60-83.xilinx.com;CAT:NONE;SFTY:;SFS:(136003)(396003)(346002)(39860400002)(376002)(46966005)(7416002)(316002)(186003)(42186006)(83380400001)(6636002)(37006003)(30864003)(2906002)(47076004)(336012)(81166007)(70586007)(5660300002)(54906003)(6862004)(33656002)(82740400003)(356005)(8676002)(478600001)(26005)(6266002)(426003)(8936002)(107886003)(44832011)(1076003)(82310400002)(36756003)(70206006)(2616005)(4326008)(42866002)(559001)(579004)(309714004);DIR:OUT;SFP:1101; X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: f62b8fd2-880a-48c5-a165-08d82910d123 X-MS-TrafficTypeDiagnostic: CY4PR02MB2501: X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Oob-TLC-OOBClassifiers: OLM:5236; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: aLpXJiYX88L5FZtAqbieXUqc/wNEDJDx5ipZkjcSGxU3CTQ7FuHc6oUGjkvQAH00F/MgG+kAc5JyM+7jlaMP1wxSr0KiNJhZ4xPQxEfpLg+8WB2HgS3u8ZaMpbeS018lSf7parb7CKXAp7E/Y0lxnSdZdb2x/w9QB63dJNZLBzmj8sz0kG43y09pm8bCAJMR0iKt899mhEV3fctQuFwK8TJMmLzJEqykDifmLkRtRSDw2OTEnHIug3riFTxCuDqQKYY+JZk5Tu/Ot1XIOr3uzJqvKnswmDIUyz1lf/9RoeIosxbu6WxzrYiwdnvvokVtIVAFC4L67M2u6gWy8hf90MkKvvwv6mlCBXs+b7pu9Eeh8JsXHzYlZVSsY7FV8JVlEGCBeazS12gvJDwnoSaF+X+Ly8zWqJ9u8MUMzbOOLFJ/dDtvfdVsepQwAC+W6ORA X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Jul 2020 22:45:47.7764 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f62b8fd2-880a-48c5-a165-08d82910d123 X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c;Ip=[149.199.60.83];Helo=[xsj-pvapsmtpgw01] X-MS-Exchange-CrossTenant-AuthSource: CY1NAM02FT058.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY4PR02MB2501 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Hi Vishal, Thank you for the patch. Sorry for late response. On Wed, Jun 17, 2020 at 10:33:04PM -0700, Vishal Sagar wrote: > The Xilinx UHD-SDI Rx subsystem soft IP is used to capture native SDI > streams from SDI sources like SDI broadcast equipment like cameras and > mixers. This block outputs either native SDI, native video or > AXI4-Stream compliant data stream for further processing. Please refer > to PG290 for details. >=20 > The driver is used to configure the IP to add framer, search for > specific modes, get the detected mode, stream parameters, errors, etc. > It also generates events for video lock/unlock, bridge over/under flow. >=20 > The driver supports 10/12 bpc YUV 422 media bus format currently. It > also decodes the stream parameters based on the ST352 packet embedded i= n the > stream. In case the ST352 packet isn't present in the stream, the core'= s > detected properties are used to set stream properties. >=20 > The driver currently supports only the AXI4-Stream IP configuration. >=20 > Signed-off-by: Vishal Sagar > --- > v3 > - fixed KConfig with better description > - removed unnecessary header files > - converted uppercase to lowercase for all hex values > - merged core struct to state struct > - removed most one line functions and replaced with direct reg > read/write or macros > - dt property bpp to bpc. default 10. not mandatory. > - fixed subscribe events, log_status, s_stream > - merged overflow/underflow to one event > - moved all controls to xilinx-sdirxss.h > - max events from 128 to 8 > - used FIELD_GET() instead of custom macro > - updated the controls documentation > - added spinlock > - removed 3GB control and added mode to detect bitmask > - fixed format for (width, height, colorspace, xfer func, etc) > - added dv_timings_cap, s/g_dv_timings > - fixed set/get_format > - fix v4l control registrations > - fix order of registration / deregistration in probe() remove() > - fixed other comments from Hyun, Laurent and Hans > - things yet to close > - adding source port for connector (Laurent's suggestion) > - adding new FIELD type for Transport Stream V4L2_FIELD_ALTERNATE_PRO= G (Han's suggestion) > - Update / remove EDH or CRC related controls >=20 > v2 > - Added DV timing support based on Hans Verkuil=C5=9B feedback > - More documentation to custom v4l controls and events > - Fixed Hyun=C5=9B comments > - Added macro for masking and shifting as per Joe Perches comments > - Updated to latest as per Xilinx github repo driver like > adding new DV timings not in mainline yet uptill 03/21/20 >=20 > drivers/media/platform/xilinx/Kconfig | 11 + > drivers/media/platform/xilinx/Makefile | 1 + > .../media/platform/xilinx/xilinx-sdirxss.c | 2121 +++++++++++++++++ > include/uapi/linux/v4l2-controls.h | 6 + > include/uapi/linux/xilinx-sdirxss.h | 283 +++ > 5 files changed, 2422 insertions(+) > create mode 100644 drivers/media/platform/xilinx/xilinx-sdirxss.c > create mode 100644 include/uapi/linux/xilinx-sdirxss.h >=20 > diff --git a/drivers/media/platform/xilinx/Kconfig b/drivers/media/plat= form/xilinx/Kconfig > index 01c96fb66414..578cdcc1036e 100644 > --- a/drivers/media/platform/xilinx/Kconfig > +++ b/drivers/media/platform/xilinx/Kconfig > @@ -12,6 +12,17 @@ config VIDEO_XILINX > =20 > if VIDEO_XILINX > =20 > +config VIDEO_XILINX_SDIRXSS > + tristate "Xilinx UHD SDI Rx Subsystem" > + help > + Driver for Xilinx UHD-SDI Rx Subsystem. This is a V4L sub-device > + based driver that takes input from a SDI source like SDI camera and > + converts it into an AXI4-Stream. The subsystem comprises a SMPTE > + UHD-SDI Rx core, a SDI Rx to Native Video bridge and a Video In to > + AXI4-Stream bridge. The driver is used to set different stream > + detection modes and identify stream properties to properly configur= e > + downstream. > + > config VIDEO_XILINX_TPG > tristate "Xilinx Video Test Pattern Generator" > depends on VIDEO_XILINX > diff --git a/drivers/media/platform/xilinx/Makefile b/drivers/media/pla= tform/xilinx/Makefile > index 4cdc0b1ec7a5..3beaf24d832c 100644 > --- a/drivers/media/platform/xilinx/Makefile > +++ b/drivers/media/platform/xilinx/Makefile > @@ -3,5 +3,6 @@ > xilinx-video-objs +=3D xilinx-dma.o xilinx-vip.o xilinx-vipp.o > =20 > obj-$(CONFIG_VIDEO_XILINX) +=3D xilinx-video.o > +obj-$(CONFIG_VIDEO_XILINX_SDIRXSS) +=3D xilinx-sdirxss.o > obj-$(CONFIG_VIDEO_XILINX_TPG) +=3D xilinx-tpg.o > obj-$(CONFIG_VIDEO_XILINX_VTC) +=3D xilinx-vtc.o > diff --git a/drivers/media/platform/xilinx/xilinx-sdirxss.c b/drivers/m= edia/platform/xilinx/xilinx-sdirxss.c > new file mode 100644 > index 000000000000..e39aab7c656a > --- /dev/null > +++ b/drivers/media/platform/xilinx/xilinx-sdirxss.c > @@ -0,0 +1,2121 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Driver for Xilinx SDI Rx Subsystem > + * > + * Copyright (C) 2017 - 2020 Xilinx, Inc. > + * > + * Contacts: Vishal Sagar > + */ > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +/* > + * SDI Rx register map, bitmask and offsets > + */ > +#define XSDIRX_RST_CTRL_REG 0x00 > +#define XSDIRX_MDL_CTRL_REG 0x04 > +#define XSDIRX_GLBL_IER_REG 0x0c > +#define XSDIRX_ISR_REG 0x10 > +#define XSDIRX_IER_REG 0x14 > +#define XSDIRX_ST352_VALID_REG 0x18 > +#define XSDIRX_ST352_DS1_REG 0x1c > +#define XSDIRX_ST352_DS3_REG 0x20 > +#define XSDIRX_ST352_DS5_REG 0x24 > +#define XSDIRX_ST352_DS7_REG 0x28 > +#define XSDIRX_ST352_DS9_REG 0x2c > +#define XSDIRX_ST352_DS11_REG 0x30 > +#define XSDIRX_ST352_DS13_REG 0x34 > +#define XSDIRX_ST352_DS15_REG 0x38 > +#define XSDIRX_VERSION_REG 0x3c > +#define XSDIRX_SS_CONFIG_REG 0x40 > +#define XSDIRX_MODE_DET_STAT_REG 0x44 > +#define XSDIRX_TS_DET_STAT_REG 0x48 > +#define XSDIRX_EDH_STAT_REG 0x4c > +#define XSDIRX_EDH_ERRCNT_EN_REG 0x50 > +#define XSDIRX_EDH_ERRCNT_REG 0x54 > +#define XSDIRX_CRC_ERRCNT_REG 0x58 > +#define XSDIRX_VID_LOCK_WINDOW_REG 0x5c > +#define XSDIRX_ST352_DS2_REG 0x70 > +#define XSDIRX_ST352_DS4_REG 0x74 > +#define XSDIRX_ST352_DS6_REG 0x78 > +#define XSDIRX_ST352_DS8_REG 0x7c > +#define XSDIRX_ST352_DS10_REG 0x80 > +#define XSDIRX_ST352_DS12_REG 0x84 > +#define XSDIRX_ST352_DS14_REG 0x88 > +#define XSDIRX_ST352_DS16_REG 0x8c > + > +#define XSDIRX_RST_CTRL_SS_EN_MASK BIT(0) > +#define XSDIRX_RST_CTRL_SRST_MASK BIT(1) > +#define XSDIRX_RST_CTRL_RST_CRC_ERRCNT_MASK BIT(2) > +#define XSDIRX_RST_CTRL_RST_EDH_ERRCNT_MASK BIT(3) > +#define XSDIRX_RST_CTRL_SDIRX_BRIDGE_ENB_MASK BIT(8) > +#define XSDIRX_RST_CTRL_VIDIN_AXI4S_MOD_ENB_MASK BIT(9) > +#define XSDIRX_RST_CTRL_BRIDGE_CH_FMT_OFFSET 10 > +#define XSDIRX_RST_CTRL_BRIDGE_CH_FMT_MASK GENMASK(12, 10) > +#define XSDIRX_RST_CTRL_BRIDGE_CH_FMT_YUV444 1 > + > +#define XSDIRX_MDL_CTRL_FRM_EN_MASK BIT(4) > +#define XSDIRX_MDL_CTRL_MODE_DET_EN_MASK BIT(5) > +#define XSDIRX_MDL_CTRL_MODE_HD_EN_MASK BIT(8) > +#define XSDIRX_MDL_CTRL_MODE_SD_EN_MASK BIT(9) > +#define XSDIRX_MDL_CTRL_MODE_3G_EN_MASK BIT(10) > +#define XSDIRX_MDL_CTRL_MODE_6G_EN_MASK BIT(11) > +#define XSDIRX_MDL_CTRL_MODE_12GI_EN_MASK BIT(12) > +#define XSDIRX_MDL_CTRL_MODE_12GF_EN_MASK BIT(13) > +#define XSDIRX_MDL_CTRL_MODE_AUTO_DET_MASK GENMASK(13, 8) > + > +#define XSDIRX_MDL_CTRL_FORCED_MODE_OFFSET 16 > +#define XSDIRX_MDL_CTRL_FORCED_MODE_MASK GENMASK(18, 16) > + > +#define XSDIRX_GLBL_INTR_EN_MASK BIT(0) > + > +#define XSDIRX_INTR_VIDLOCK_MASK BIT(0) > +#define XSDIRX_INTR_VIDUNLOCK_MASK BIT(1) > +#define XSDIRX_INTR_OVERFLOW_MASK BIT(9) > +#define XSDIRX_INTR_UNDERFLOW_MASK BIT(10) > + > +#define XSDIRX_INTR_ALL_MASK (XSDIRX_INTR_VIDLOCK_MASK |\ > + XSDIRX_INTR_VIDUNLOCK_MASK |\ > + XSDIRX_INTR_OVERFLOW_MASK |\ > + XSDIRX_INTR_UNDERFLOW_MASK) > + > +#define XSDIRX_ST352_VALID_DS1_MASK BIT(0) > +#define XSDIRX_ST352_VALID_DS3_MASK BIT(1) > +#define XSDIRX_ST352_VALID_DS5_MASK BIT(2) > +#define XSDIRX_ST352_VALID_DS7_MASK BIT(3) > +#define XSDIRX_ST352_VALID_DS9_MASK BIT(4) > +#define XSDIRX_ST352_VALID_DS11_MASK BIT(5) > +#define XSDIRX_ST352_VALID_DS13_MASK BIT(6) > +#define XSDIRX_ST352_VALID_DS15_MASK BIT(7) > + > +#define XSDIRX_MODE_DET_STAT_RX_MODE_MASK GENMASK(2, 0) > +#define XSDIRX_MODE_DET_STAT_MODE_LOCK_MASK BIT(3) > +#define XSDIRX_MODE_DET_STAT_ACT_STREAM_MASK GENMASK(6, 4) > +#define XSDIRX_MODE_DET_STAT_ACT_STREAM_OFFSET 4 > +#define XSDIRX_MODE_DET_STAT_LVLB_3G_MASK BIT(7) > + > +#define XSDIRX_TS_DET_STAT_LOCKED_MASK BIT(0) > +#define XSDIRX_TS_DET_STAT_SCAN_MASK BIT(1) > +#define XSDIRX_TS_DET_STAT_FAMILY_MASK GENMASK(7, 4) > +#define XSDIRX_TS_DET_STAT_RATE_MASK GENMASK(11, 8) > + > +#define XSDIRX_TS_DET_STAT_RATE_NONE 0x0 > +#define XSDIRX_TS_DET_STAT_RATE_23_98HZ 0x2 > +#define XSDIRX_TS_DET_STAT_RATE_24HZ 0x3 > +#define XSDIRX_TS_DET_STAT_RATE_47_95HZ 0x4 > +#define XSDIRX_TS_DET_STAT_RATE_25HZ 0x5 > +#define XSDIRX_TS_DET_STAT_RATE_29_97HZ 0x6 > +#define XSDIRX_TS_DET_STAT_RATE_30HZ 0x7 > +#define XSDIRX_TS_DET_STAT_RATE_48HZ 0x8 > +#define XSDIRX_TS_DET_STAT_RATE_50HZ 0x9 > +#define XSDIRX_TS_DET_STAT_RATE_59_94HZ 0xa > +#define XSDIRX_TS_DET_STAT_RATE_60HZ 0xb > + > +#define XSDIRX_EDH_STAT_EDH_AP_MASK BIT(0) > +#define XSDIRX_EDH_STAT_EDH_FF_MASK BIT(1) > +#define XSDIRX_EDH_STAT_EDH_ANC_MASK BIT(2) > +#define XSDIRX_EDH_STAT_AP_FLAG_MASK GENMASK(8, 4) > +#define XSDIRX_EDH_STAT_FF_FLAG_MASK GENMASK(13, 9) > +#define XSDIRX_EDH_STAT_ANC_FLAG_MASK GENMASK(18, 14) > +#define XSDIRX_EDH_STAT_PKT_FLAG_MASK GENMASK(22, 19) > + > +#define XSDIRX_EDH_ERRCNT_COUNT_MASK GENMASK(15, 0) > + > +#define XSDIRX_CRC_ERRCNT_COUNT_MASK GENMASK(31, 16) > +#define XSDIRX_CRC_ERRCNT_DS_CRC_MASK GENMASK(15, 0) > + > +#define XSDIRX_VERSION_REV_MASK GENMASK(7, 0) > +#define XSDIRX_VERSION_PATCHID_MASK GENMASK(11, 8) > +#define XSDIRX_VERSION_VER_REV_MASK GENMASK(15, 12) > +#define XSDIRX_VERSION_VER_MIN_MASK GENMASK(23, 16) > +#define XSDIRX_VERSION_VER_MAJ_MASK GENMASK(31, 24) > + > +#define XSDIRX_SS_CONFIG_EDH_INCLUDED_MASK BIT(1) > + > +#define XSDIRX_STAT_SB_RX_TDATA_CHANGE_DONE_MASK BIT(0) > +#define XSDIRX_STAT_SB_RX_TDATA_CHANGE_FAIL_MASK BIT(1) > +#define XSDIRX_STAT_SB_RX_TDATA_GT_RESETDONE_MASK BIT(2) > +#define XSDIRX_STAT_SB_RX_TDATA_GT_BITRATE_MASK BIT(3) > + > +#define XSDIRX_DEFAULT_WIDTH 1920 > +#define XSDIRX_DEFAULT_HEIGHT 1080 > + > +#define XSDIRX_MAX_STR_LENGTH 16 This is not used. Please remove. > + > +#define XSDIRX_DEFAULT_VIDEO_LOCK_WINDOW 0x3000 Not sure if this macro is needed. The value can be used directly. Single user macro without additional description may be removed. Please check. > + > +#define XSDIRX_MODE_HD_MASK 0x0 > +#define XSDIRX_MODE_SD_MASK 0x1 > +#define XSDIRX_MODE_3G_MASK 0x2 > +#define XSDIRX_MODE_6G_MASK 0x4 > +#define XSDIRX_MODE_12GI_MASK 0x5 > +#define XSDIRX_MODE_12GF_MASK 0x6 These are not masks, so _MASK better be removed from names. > + > +/* Maximum number of events per file handle. */ > +#define XSDIRX_MAX_EVENTS 8 > + > +/* ST352 related macros */ > +#define XST352_PAYLOAD_BYTE1_MASK GENMASK(7, 0) > +#define XST352_PAYLOAD_BYTE2_OFFSET 8 > +#define XST352_PAYLOAD_BYTE3_OFFSET 16 > +#define XST352_PAYLOAD_BYTE4_OFFSET 24 Last 3 are not used. Those may have become unused from using FIELD_GET(). Please remove. > + > +#define XST352_BYTE1_ST292_1x720L_1_5G 0x84 > +#define XST352_BYTE1_ST292_1x1080L_1_5G 0x85 > +#define XST352_BYTE1_ST425_2008_750L_3GB 0x88 > +#define XST352_BYTE1_ST425_2008_1125L_3GA 0x89 > +#define XST352_BYTE1_ST372_DL_3GB 0x8a > +#define XST352_BYTE1_ST372_2x720L_3GB 0x8b > +#define XST352_BYTE1_ST372_2x1080L_3GB 0x8c > +#define XST352_BYTE1_ST2081_10_2160L_6G 0xc0 > +#define XST352_BYTE1_ST2081_10_2_1080L_6G 0xc1 > +#define XST352_BYTE1_ST2081_10_DL_2160L_6G 0xc2 > +#define XST352_BYTE1_ST2082_10_2160L_12G 0xce > + > +#define XST352_BYTE2_TS_TYPE_MASK BIT(15) > +#define XST352_BYTE2_PIC_TYPE_MASK BIT(14) > +#define XST352_BYTE2_TS_PIC_TYPE_INTERLACED 0 > +#define XST352_BYTE2_TS_PIC_TYPE_PROGRESSIVE 1 Not used. :) Please check and remove unneeded definitions. > + > +#define XST352_BYTE2_FPS_MASK GENMASK(11, 8) > +#define XST352_BYTE2_FPS_24F 0x2 > +#define XST352_BYTE2_FPS_24 0x3 > +#define XST352_BYTE2_FPS_48F 0x4 > +#define XST352_BYTE2_FPS_25 0x5 > +#define XST352_BYTE2_FPS_30F 0x6 > +#define XST352_BYTE2_FPS_30 0x7 > +#define XST352_BYTE2_FPS_48 0x8 > +#define XST352_BYTE2_FPS_50 0x9 > +#define XST352_BYTE2_FPS_60F 0xa > +#define XST352_BYTE2_FPS_60 0xb > +/* Table 4 ST 2081-10:2015 */ > +#define XST352_BYTE2_FPS_96 0xc > +#define XST352_BYTE2_FPS_100 0xd > +#define XST352_BYTE2_FPS_120 0xe > +#define XST352_BYTE2_FPS_120F 0xf > + > +#define XST352_BYTE3_ACT_LUMA_COUNT_MASK BIT(22) > + > +#define XST352_BYTE3_COLOR_FORMAT_MASK GENMASK(19, 16) > +#define XST352_BYTE3_COLOR_FORMAT_422 0x0 > +#define XST352_BYTE3_COLOR_FORMAT_YUV444 0x1 > +#define XST352_BYTE3_COLOR_FORMAT_420 0x3 > +#define XST352_BYTE3_COLOR_FORMAT_GBR 0x2 > + > +#define XST352_BYTE3_COLORIMETRY_MASK GENMASK(21, 20) > +#define XST352_BYTE3_COLORIMETRY_BT709 0 > +#define XST352_BYTE3_COLORIMETRY_COLOR_VANC 1 > +#define XST352_BYTE3_COLORIMETRY_UHDTV 2 > +#define XST352_BYTE3_COLORIMETRY_UNKNOWN 3 > + > +#define XST352_BYTE4_BIT_DEPTH_MASK GENMASK(25, 24) > +#define XST352_BYTE4_BIT_DEPTH_10 0x1 > +#define XST352_BYTE4_BIT_DEPTH_12 0x2 > + > +/* GT input clock for sdi_rx_clk */ > +#define CLK_INT 148500000UL > + > +#define XSDIRXSS_WIDTH_MIN 720 > +#define XSDIRXSS_WIDTH_MAX 4096 > +#define XSDIRXSS_HEIGHT_MIN 243 > +#define XSDIRXSS_HEIGHT_MAX 2160 > +#define XSDIRXSS_PIXELCLOCK_MIN 13500000 > +#define XSDIRXSS_PIXELCLOCK_MAX 594000000 > + > +/** > + * enum sdi_family_enc - SDI Transport Video Format Detected with Acti= ve Pixels > + * @XSDIRX_SMPTE_ST_274: SMPTE ST 274 detected with AP 1920x1080 > + * @XSDIRX_SMPTE_ST_296: SMPTE ST 296 detected with AP 1280x720 > + * @XSDIRX_SMPTE_ST_2048_2: SMPTE ST 2048-2 detected with AP 2048x1080 > + * @XSDIRX_SMPTE_ST_295: SMPTE ST 295 detected with AP 1920x1080 > + * @XSDIRX_NTSC: NTSC encoding detected with AP 720x486 > + * @XSDIRX_PAL: PAL encoding detected with AP 720x576 > + * @XSDIRX_TS_UNKNOWN: Unknown SMPTE Transport family type > + */ > +enum sdi_family_enc { > + XSDIRX_SMPTE_ST_274 =3D 0, > + XSDIRX_SMPTE_ST_296 =3D 1, > + XSDIRX_SMPTE_ST_2048_2 =3D 2, > + XSDIRX_SMPTE_ST_295 =3D 3, > + XSDIRX_NTSC =3D 8, > + XSDIRX_PAL =3D 9, > + XSDIRX_TS_UNKNOWN =3D 15 > +}; > + > +/** > + * struct xsdirxss_state - SDI Rx Subsystem device structure > + * @subdev: The v4l2 subdev structure > + * @ctrl_handler: control handler > + * @default_format: default V4L2 media bus format > + * @pad: source media pad > + * @dev: Platform structure > + * @iomem: Base address of subsystem > + * @clks: array of clocks > + * @prev_is_frac: Previous clock is fractional or not flag > + * @bpc: Bits per component, can be 10 or 12 > + * @mode: 3G/6G/12G mode > + * @num_clks: number of clocks > + * @include_edh: EDH processor presence > + * @slock: spinlock to protect below members > + * @format: Active V4L2 format detected > + * @src_format: Active V4L2 format on source pad > + * @frame_interval: Captures the frame rate > + * @current_timings: DV timings from application > + * @detected_timings_index: index of DV timings detected on incoming s= tream > + * @vidlockwin: Video lock window value set by control > + * @edhmask: EDH mask set by control > + * @searchmask: Search mask set by control > + * @streaming: Flag for storing streaming state > + * @vidlocked: Flag indicating SDI Rx has locked onto video stream > + * @ts_is_interlaced: Flag indicating Transport Stream is interlaced. > + * @framer_enable: Flag for framer enabled or not set by control > + * > + * This structure contains the device driver related parameters > + */ > +struct xsdirxss_state { > + struct v4l2_subdev subdev; > + struct v4l2_ctrl_handler ctrl_handler; > + struct v4l2_mbus_framefmt default_format; > + struct media_pad pad; > + struct device *dev; > + void __iomem *iomem; > + struct clk_bulk_data *clks; > + int prev_is_frac; > + u32 bpc; > + u32 mode; > + unsigned int num_clks; > + bool include_edh; > + > + /* > + * This spinlock is used to protect the below members > + * format, src_format, frame_interval, current_timings, > + * detected_timings_index, vidlockwin, edhmask, searchmask, > + * streaming, vidlocked, ts_is_interlaced, framer_enable > + */ > + spinlock_t slock; > + struct v4l2_mbus_framefmt format; > + struct v4l2_mbus_framefmt src_format; > + struct v4l2_fract frame_interval; > + struct v4l2_dv_timings current_timings; > + u32 detected_timings_index; > + u32 vidlockwin; > + u32 edhmask; > + u16 searchmask; > + bool streaming; > + bool vidlocked; > + bool ts_is_interlaced; Use of bool in struct is not recommended. Not sure if it's doable with on= es getting values from other functions, but I beleive above 3 can change usi= ng bit field or normal integer type. > + bool framer_enable; > +}; > + > +/* List of clocks required by UHD-SDI Rx subsystem */ > +static const char * const xsdirxss_clks[] =3D { > + "s_axi_aclk", "sdi_rx_clk", "video_out_clk", > +}; This can move into probe() to reduce the scope. > + > +/* TODO - Add YUV 444/420 and RBG 10/12 bpc mbus formats here */ > +static const u32 xsdirxss_10bpc_mbus_fmts[] =3D { > + MEDIA_BUS_FMT_UYVY10_1X20, > +}; > + > +static const u32 xsdirxss_12bpc_mbus_fmts[] =3D { > + MEDIA_BUS_FMT_UYVY12_1X24, > +}; > + > +static const struct v4l2_dv_timings fmt_cap[] =3D { > + V4L2_DV_BT_SDI_720X487I60, > + V4L2_DV_BT_CEA_720X576I50, > + V4L2_DV_BT_CEA_1280X720P24, > + V4L2_DV_BT_CEA_1280X720P25, > + V4L2_DV_BT_CEA_1280X720P30, > + V4L2_DV_BT_CEA_1280X720P50, > + V4L2_DV_BT_CEA_1280X720P60, > + V4L2_DV_BT_CEA_1920X1080P24, > + V4L2_DV_BT_CEA_1920X1080P30, > + V4L2_DV_BT_CEA_1920X1080I50, > + V4L2_DV_BT_CEA_1920X1080I60, > + V4L2_DV_BT_CEA_1920X1080P48, > + V4L2_DV_BT_CEA_1920X1080P50, > + V4L2_DV_BT_CEA_1920X1080P60, > + V4L2_DV_BT_CEA_3840X2160P24, > + V4L2_DV_BT_CEA_3840X2160P30, > + V4L2_DV_BT_CEA_3840X2160P48, > + V4L2_DV_BT_CEA_3840X2160P50, > + V4L2_DV_BT_CEA_3840X2160P60, > + V4L2_DV_BT_CEA_4096X2160P24, > + V4L2_DV_BT_CEA_4096X2160P25, > + V4L2_DV_BT_CEA_4096X2160P30, > + V4L2_DV_BT_CEA_4096X2160P48, > + V4L2_DV_BT_CEA_4096X2160P50, > + V4L2_DV_BT_CEA_4096X2160P60, > + > + XLNX_V4L2_DV_BT_2048X1080P24, > + XLNX_V4L2_DV_BT_2048X1080P25, > + XLNX_V4L2_DV_BT_2048X1080P30, > + XLNX_V4L2_DV_BT_2048X1080I48, > + XLNX_V4L2_DV_BT_2048X1080I50, > + XLNX_V4L2_DV_BT_2048X1080I60, > + XLNX_V4L2_DV_BT_2048X1080P48, > + XLNX_V4L2_DV_BT_2048X1080P50, > + XLNX_V4L2_DV_BT_2048X1080P60, > + XLNX_V4L2_DV_BT_1920X1080I48, > +}; > + > +struct xsdirxss_dv_map { > + u32 width; > + u32 height; > + u32 fps; > + struct v4l2_dv_timings timing; > +}; > + > +static const struct xsdirxss_dv_map xsdirxss_dv_timings[] =3D { > + /* SD - 720x487i60 */ > + { 720, 243, 30, V4L2_DV_BT_SDI_720X487I60 }, > + /* SD - 720x576i50 */ > + { 720, 288, 25, V4L2_DV_BT_CEA_720X576I50 }, > + /* HD - 1280x720p23.98 */ > + /* HD - 1280x720p24 */ > + { 1280, 720, 24, V4L2_DV_BT_CEA_1280X720P24 }, > + /* HD - 1280x720p25 */ > + { 1280, 720, 25, V4L2_DV_BT_CEA_1280X720P25 }, > + /* HD - 1280x720p29.97 */ > + /* HD - 1280x720p30 */ > + { 1280, 720, 30, V4L2_DV_BT_CEA_1280X720P30 }, > + /* HD - 1280x720p50 */ > + { 1280, 720, 50, V4L2_DV_BT_CEA_1280X720P50 }, > + /* HD - 1280x720p59.94 */ > + /* HD - 1280x720p60 */ > + { 1280, 720, 60, V4L2_DV_BT_CEA_1280X720P60 }, > + /* HD - 1920x1080p23.98 */ > + /* HD - 1920x1080p24 */ > + { 1920, 1080, 24, V4L2_DV_BT_CEA_1920X1080P24 }, > + /* HD - 1920x1080p25 */ > + { 1920, 1080, 25, V4L2_DV_BT_CEA_1920X1080P25 }, > + /* HD - 1920x1080p29.97 */ > + /* HD - 1920x1080p30 */ > + { 1920, 1080, 30, V4L2_DV_BT_CEA_1920X1080P30 }, > + > + /* HD - 2048x1080p23.98 */ > + /* HD - 2048x1080p24 */ > + { 2048, 1080, 24, XLNX_V4L2_DV_BT_2048X1080P24 }, > + /* HD - 2048x1080p25 */ > + { 2048, 1080, 24, XLNX_V4L2_DV_BT_2048X1080P25 }, > + /* HD - 2048x1080p29.97 */ > + /* HD - 2048x1080p30 */ > + { 2048, 1080, 24, XLNX_V4L2_DV_BT_2048X1080P30 }, > + /* HD - 1920x1080i47.95 */ > + /* HD - 1920x1080i48 */ > + { 1920, 540, 24, XLNX_V4L2_DV_BT_1920X1080I48 }, > + > + /* HD - 1920x1080i50 */ > + { 1920, 540, 25, V4L2_DV_BT_CEA_1920X1080I50 }, > + /* HD - 1920x1080i59.94 */ > + /* HD - 1920x1080i60 */ > + { 1920, 540, 30, V4L2_DV_BT_CEA_1920X1080I60 }, > + > + /* HD - 2048x1080i47.95 */ > + /* HD - 2048x1080i48 */ > + { 2048, 540, 24, XLNX_V4L2_DV_BT_2048X1080I48 }, > + /* HD - 2048x1080i50 */ > + { 2048, 540, 25, XLNX_V4L2_DV_BT_2048X1080I50 }, > + /* HD - 2048x1080i59.94 */ > + /* HD - 2048x1080i60 */ > + { 2048, 540, 30, XLNX_V4L2_DV_BT_2048X1080I60 }, > + /* 3G - 1920x1080p47.95 */ > + /* 3G - 1920x1080p48 */ > + { 1920, 1080, 48, V4L2_DV_BT_CEA_1920X1080P48 }, > + > + /* 3G - 1920x1080p50 148.5 */ > + { 1920, 1080, 50, V4L2_DV_BT_CEA_1920X1080P50 }, > + /* 3G - 1920x1080p59.94 148.5/1.001 */ > + /* 3G - 1920x1080p60 148.5 */ > + { 1920, 1080, 60, V4L2_DV_BT_CEA_1920X1080P60 }, > + > + /* 3G - 2048x1080p47.95 */ > + /* 3G - 2048x1080p48 */ > + { 2048, 1080, 48, XLNX_V4L2_DV_BT_2048X1080P48 }, > + /* 3G - 2048x1080p50 */ > + { 2048, 1080, 50, XLNX_V4L2_DV_BT_2048X1080P50 }, > + /* 3G - 2048x1080p59.94 */ > + /* 3G - 2048x1080p60 */ > + { 2048, 1080, 60, XLNX_V4L2_DV_BT_2048X1080P60 }, > + > + /* 6G - 3840X2160p23.98 */ > + /* 6G - 3840X2160p24 */ > + { 3840, 2160, 24, V4L2_DV_BT_CEA_3840X2160P24 }, > + /* 6G - 3840X2160p25 */ > + { 3840, 2160, 25, V4L2_DV_BT_CEA_3840X2160P25 }, > + /* 6G - 3840X2160p29.97 */ > + /* 6G - 3840X2160p30 */ > + { 3840, 2160, 30, V4L2_DV_BT_CEA_3840X2160P30 }, > + /* 6G - 4096X2160p23.98 */ > + /* 6G - 4096X2160p24 */ > + { 4096, 2160, 24, V4L2_DV_BT_CEA_4096X2160P24 }, > + /* 6G - 4096X2160p25 */ > + { 4096, 2160, 25, V4L2_DV_BT_CEA_4096X2160P25 }, > + /* 6G - 4096X2160p29.97 */ > + /* 6G - 4096X2160p30 */ > + { 4096, 2160, 30, V4L2_DV_BT_CEA_4096X2160P30 }, > + /* 12G - 3840X2160p47.95 */ > + /* 12G - 3840X2160p48 */ > + { 3840, 2160, 48, V4L2_DV_BT_CEA_3840X2160P48 }, > + > + /* 12G - 3840X2160p50 */ > + { 3840, 2160, 50, V4L2_DV_BT_CEA_3840X2160P50 }, > + /* 12G - 3840X2160p59.94 */ > + /* 12G - 3840X2160p60 */ > + { 3840, 2160, 60, V4L2_DV_BT_CEA_3840X2160P60 }, > + > + /* 12G - 4096X2160p47.95 */ > + /* 12G - 4096X2160p48 */ > + { 3840, 2160, 48, V4L2_DV_BT_CEA_4096X2160P48 }, > + > + /* 12G - 4096X2160p50 */ > + { 4096, 2160, 50, V4L2_DV_BT_CEA_4096X2160P50 }, > + /* 12G - 4096X2160p59.94 */ > + /* 12G - 4096X2160p60 */ > + { 4096, 2160, 60, V4L2_DV_BT_CEA_4096X2160P60 }, > +}; > + > +static const struct v4l2_dv_timings_cap xsdirxss_timings_cap =3D { > + .type =3D V4L2_DV_BT_656_1120, > + .pad =3D 0, > + .reserved =3D { 0 }, > + V4L2_INIT_BT_TIMINGS(XSDIRXSS_WIDTH_MIN, XSDIRXSS_WIDTH_MAX, > + XSDIRXSS_HEIGHT_MIN, XSDIRXSS_HEIGHT_MAX, > + XSDIRXSS_PIXELCLOCK_MIN, XSDIRXSS_PIXELCLOCK_MAX, > + V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_SDI, > + V4L2_DV_BT_CAP_PROGRESSIVE > + | V4L2_DV_BT_CAP_INTERLACED) > + > +}; > + > +struct regmap { > + const char *name; > + u32 offset; > +}; > + > +static const struct regmap xsdirxss_regmap[] =3D { > + { .name =3D "Reset Control", .offset =3D XSDIRX_RST_CTRL_REG }, > + { .name =3D "Module Control", .offset =3D XSDIRX_MDL_CTRL_REG }, > + { .name =3D "Interrupt Enable", .offset =3D XSDIRX_IER_REG }, > + { .name =3D "Global Interrupt Enable", .offset =3D XSDIRX_GLBL_IER_RE= G }, > + { .name =3D "ST352 Valid", .offset =3D XSDIRX_ST352_VALID_REG }, > + { .name =3D "ST352 DS1", .offset =3D XSDIRX_ST352_DS1_REG }, > + { .name =3D "ST352 DS2", .offset =3D XSDIRX_ST352_DS2_REG }, > + { .name =3D "ST352 DS3", .offset =3D XSDIRX_ST352_DS3_REG }, > + { .name =3D "ST352 DS4", .offset =3D XSDIRX_ST352_DS4_REG }, > + { .name =3D "ST352 DS5", .offset =3D XSDIRX_ST352_DS5_REG }, > + { .name =3D "ST352 DS6", .offset =3D XSDIRX_ST352_DS6_REG }, > + { .name =3D "ST352 DS7", .offset =3D XSDIRX_ST352_DS7_REG }, > + { .name =3D "ST352 DS8", .offset =3D XSDIRX_ST352_DS8_REG }, > + { .name =3D "ST352 DS9", .offset =3D XSDIRX_ST352_DS9_REG }, > + { .name =3D "ST352 DS10", .offset =3D XSDIRX_ST352_DS10_REG }, > + { .name =3D "ST352 DS11", .offset =3D XSDIRX_ST352_DS11_REG }, > + { .name =3D "ST352 DS12", .offset =3D XSDIRX_ST352_DS12_REG }, > + { .name =3D "ST352 DS13", .offset =3D XSDIRX_ST352_DS13_REG }, > + { .name =3D "ST352 DS14", .offset =3D XSDIRX_ST352_DS14_REG }, > + { .name =3D "ST352 DS15", .offset =3D XSDIRX_ST352_DS15_REG }, > + { .name =3D "ST352 DS16", .offset =3D XSDIRX_ST352_DS16_REG }, > + { .name =3D "Version", .offset =3D XSDIRX_VERSION_REG }, > + { .name =3D "Subsystem Config ", .offset =3D XSDIRX_SS_CONFIG_REG }, > + { .name =3D "Mode Detect", .offset =3D XSDIRX_MODE_DET_STAT_REG }, > + { .name =3D "Transport Stream Detect", .offset =3D XSDIRX_TS_DET_STAT= _REG }, > + { .name =3D "EDH Status", .offset =3D XSDIRX_EDH_STAT_REG }, > + { .name =3D "EDH Error Count", .offset =3D XSDIRX_EDH_ERRCNT_EN_REG }= , > + { .name =3D "CRC error indication", .offset =3D XSDIRX_CRC_ERRCNT_REG= }, > + { .name =3D "Video Lock Window", .offset =3D XSDIRX_VID_LOCK_WINDOW_R= EG }, > +}; > + > +static inline struct xsdirxss_state * > +to_xsdirxssstate(struct v4l2_subdev *subdev) > +{ > + return container_of(subdev, struct xsdirxss_state, subdev); > +} > + > +/* > + * Register related operations > + */ > +static inline u32 xsdirxss_read(struct xsdirxss_state *xsdirxss, u32 a= ddr) > +{ > + return ioread32(xsdirxss->iomem + addr); > +} > + > +static inline void xsdirxss_write(struct xsdirxss_state *xsdirxss, u32= addr, > + u32 value) > +{ > + iowrite32(value, xsdirxss->iomem + addr); > +} > + > +static inline void xsdirxss_clr(struct xsdirxss_state *xsdirxss, u32 a= ddr, > + u32 clr) > +{ > + xsdirxss_write(xsdirxss, addr, xsdirxss_read(xsdirxss, addr) & ~clr); > +} > + > +static inline void xsdirxss_set(struct xsdirxss_state *xsdirxss, u32 a= ddr, > + u32 set) > +{ > + xsdirxss_write(xsdirxss, addr, xsdirxss_read(xsdirxss, addr) | set); > +} > + In my opinion, from here to > +#define XSDIRX_CORE_DISABLE(state) xsdirxss_clr((state), XSDIRX_RST_C= TRL_REG,\ > + XSDIRX_RST_CTRL_SS_EN_MASK) > + > +#define XSDIRX_CORE_ENABLE(state) xsdirxss_set((state), XSDIRX_RST_CT= RL_REG,\ > + XSDIRX_RST_CTRL_SS_EN_MASK) > + > +#define XSDIRX_GLOBAL_INTR_ENABLE(state) \ > + xsdirxss_set((state), XSDIRX_GLBL_IER_REG, XSDIRX_GLBL_INTR_EN_MASK) > + > +#define XSDIRX_GLOBAL_INTR_DISABLE(state) \ > + xsdirxss_clr((state), XSDIRX_GLBL_IER_REG, XSDIRX_GLBL_INTR_EN_MASK) here, inlining single liners or static inline would be better than above = macros. > + > +static int xsdirx_set_modedetect(struct xsdirxss_state *state, u16 mas= k) > +{ > + u32 val; > + struct device *dev =3D state->dev; > + > + mask &=3D XSDIRX_DETECT_ALL_MODES; > + if (!mask) { > + dev_err(dev, "Invalid bit mask =3D 0x%08x\n", mask); > + return -EINVAL; > + } > + > + dev_dbg(dev, "mask =3D 0x%x\n", mask); > + > + val =3D xsdirxss_read(state, XSDIRX_MDL_CTRL_REG); > + val &=3D ~XSDIRX_MDL_CTRL_MODE_DET_EN_MASK; > + val &=3D ~XSDIRX_MDL_CTRL_MODE_AUTO_DET_MASK; > + val &=3D ~XSDIRX_MDL_CTRL_FORCED_MODE_MASK; > + > + if (hweight16(mask) > 1) { > + /* Multi mode detection as more than 1 bit set in mask */ > + dev_dbg(dev, "Detect multiple modes\n"); > + > + if (mask & BIT(XSDIRX_MODE_SD_OFFSET)) > + val |=3D XSDIRX_MDL_CTRL_MODE_SD_EN_MASK; > + if (mask & BIT(XSDIRX_MODE_HD_OFFSET)) > + val |=3D XSDIRX_MDL_CTRL_MODE_HD_EN_MASK; > + /* > + * There is only one bit in IP to detect 3G mode. > + * So set it when 3GA or 3GB mask is set. > + */ > + if (mask & (BIT(XSDIRX_MODE_3GA_OFFSET) | > + BIT(XSDIRX_MODE_3GB_OFFSET))) > + val |=3D XSDIRX_MDL_CTRL_MODE_3G_EN_MASK; > + if (mask & BIT(XSDIRX_MODE_6G_OFFSET)) > + val |=3D XSDIRX_MDL_CTRL_MODE_6G_EN_MASK; > + if (mask & BIT(XSDIRX_MODE_12GI_OFFSET)) > + val |=3D XSDIRX_MDL_CTRL_MODE_12GI_EN_MASK; > + if (mask & BIT(XSDIRX_MODE_12GF_OFFSET)) > + val |=3D XSDIRX_MDL_CTRL_MODE_12GF_EN_MASK; > + > + val |=3D XSDIRX_MDL_CTRL_MODE_DET_EN_MASK; > + } else { > + /* Fixed Mode */ > + u32 forced_mode_mask; > + > + dev_dbg(dev, "Detect fixed mode\n"); > + > + /* Find offset of first bit set */ > + switch (mask) { > + case XSDIRX_MODE_SD_OFFSET: > + forced_mode_mask =3D XSDIRX_MODE_SD_MASK; > + break; > + case XSDIRX_MODE_HD_OFFSET: > + forced_mode_mask =3D XSDIRX_MODE_HD_MASK; > + break; > + /* > + * There is only one bit in IP to detect 3G mode. > + * So set it when 3GA or 3GB mask is set. > + */ > + case XSDIRX_MODE_3GA_OFFSET: > + case XSDIRX_MODE_3GB_OFFSET: > + forced_mode_mask =3D XSDIRX_MODE_3G_MASK; > + break; > + case XSDIRX_MODE_6G_OFFSET: > + forced_mode_mask =3D XSDIRX_MODE_6G_MASK; > + break; > + case XSDIRX_MODE_12GI_OFFSET: > + forced_mode_mask =3D XSDIRX_MODE_12GI_MASK; > + break; > + case XSDIRX_MODE_12GF_OFFSET: > + forced_mode_mask =3D XSDIRX_MODE_12GF_MASK; > + break; > + default: > + dev_err(dev, "Invalid mask for fixed detect mode\n"); > + return -EINVAL; > + } > + dev_dbg(dev, "Forced Mode Mask : 0x%x\n", > + forced_mode_mask); > + val |=3D forced_mode_mask << XSDIRX_MDL_CTRL_FORCED_MODE_OFFSET; > + } > + > + dev_dbg(dev, "Modes to be detected : sdi ctrl reg =3D 0x%08x\n", > + val); > + xsdirxss_write(state, XSDIRX_MDL_CTRL_REG, val); > + > + return 0; > +} > + > +static void xsdirx_streamflow_control(struct xsdirxss_state *state, bo= ol enable) > +{ > + /* The sdi to native bridge is followed by native to axis4 bridge */ > + /* > + * TODO - Enable YUV444/RBG format in the bridge based > + * on BYTE3 color format. > + * XSDIRX_RST_CTRL_BRIDGE_CH_FMT_YUV444 > + */ > + if (enable) { > + xsdirxss_set(state, XSDIRX_RST_CTRL_REG, > + XSDIRX_RST_CTRL_VIDIN_AXI4S_MOD_ENB_MASK); > + xsdirxss_set(state, XSDIRX_RST_CTRL_REG, > + XSDIRX_RST_CTRL_SDIRX_BRIDGE_ENB_MASK); > + } else { > + xsdirxss_clr(state, XSDIRX_RST_CTRL_REG, > + XSDIRX_RST_CTRL_SDIRX_BRIDGE_ENB_MASK); > + xsdirxss_clr(state, XSDIRX_RST_CTRL_REG, > + XSDIRX_RST_CTRL_VIDIN_AXI4S_MOD_ENB_MASK); > + } > + state->streaming =3D enable; > +} > + > +static void xsdirxss_get_framerate(struct v4l2_fract *frame_interval, > + u32 framerate) > +{ > + switch (framerate) { > + case XSDIRX_TS_DET_STAT_RATE_23_98HZ: > + frame_interval->numerator =3D 1001; > + frame_interval->denominator =3D 24000; > + break; > + case XSDIRX_TS_DET_STAT_RATE_24HZ: > + frame_interval->numerator =3D 1000; > + frame_interval->denominator =3D 24000; > + break; > + case XSDIRX_TS_DET_STAT_RATE_25HZ: > + frame_interval->numerator =3D 1000; > + frame_interval->denominator =3D 25000; > + break; > + case XSDIRX_TS_DET_STAT_RATE_29_97HZ: > + frame_interval->numerator =3D 1001; > + frame_interval->denominator =3D 30000; > + break; > + case XSDIRX_TS_DET_STAT_RATE_30HZ: > + frame_interval->numerator =3D 1000; > + frame_interval->denominator =3D 30000; > + break; > + case XSDIRX_TS_DET_STAT_RATE_47_95HZ: > + frame_interval->numerator =3D 1001; > + frame_interval->denominator =3D 48000; > + break; > + case XSDIRX_TS_DET_STAT_RATE_48HZ: > + frame_interval->numerator =3D 1000; > + frame_interval->denominator =3D 48000; > + break; > + case XSDIRX_TS_DET_STAT_RATE_50HZ: > + frame_interval->numerator =3D 1000; > + frame_interval->denominator =3D 50000; > + break; > + case XSDIRX_TS_DET_STAT_RATE_59_94HZ: > + frame_interval->numerator =3D 1001; > + frame_interval->denominator =3D 60000; > + break; > + case XSDIRX_TS_DET_STAT_RATE_60HZ: > + frame_interval->numerator =3D 1000; > + frame_interval->denominator =3D 60000; > + break; > + default: > + frame_interval->numerator =3D 1; > + frame_interval->denominator =3D 1; This shouldn't happen, so would it make sense to have an error here? > + } > +} > + > +static void xsdirxss_set_gtclk(struct xsdirxss_state *state) > +{ > + struct clk *gtclk; This variable is not needed. Up to you. > + unsigned long clkrate; > + int ret, is_frac; > + u32 mode; > + > + mode =3D xsdirxss_read(state, XSDIRX_MODE_DET_STAT_REG); > + mode &=3D XSDIRX_MODE_DET_STAT_RX_MODE_MASK; > + > + /* > + * TODO: For now, don't change the clock rate for any mode except 12G= . > + * In future, configure gt clock for all modes and enable clock only > + * when needed (stream on/off). > + */ > + if (mode !=3D XSDIRX_MODE_12GI_MASK && mode !=3D XSDIRX_MODE_12GF_MAS= K) > + return; > + > + /* When numerator is 1001 then frame rate is fractional else integer = */ > + is_frac =3D state->frame_interval.numerator =3D=3D 1001 ? 1 : 0; > + > + if (state->prev_is_frac =3D=3D is_frac) > + return; > + > + XSDIRX_GLOBAL_INTR_DISABLE(state); > + xsdirxss_clr(state, XSDIRX_IER_REG, XSDIRX_INTR_ALL_MASK); > + XSDIRX_CORE_DISABLE(state); > + > + /* get sdi_rx_clk */ I'd remove this comment, > + gtclk =3D state->clks[1].clk; > + > + /* calculate clkrate */ and this. Up to you. > + if (!is_frac) > + clkrate =3D CLK_INT; > + else > + clkrate =3D (CLK_INT * 1000) / 1001; > + > + ret =3D clk_set_rate(gtclk, clkrate); > + if (ret) > + dev_err(state->dev, "failed to set clk rate =3D %d\n", ret); > + > + state->prev_is_frac =3D is_frac; > + clkrate =3D clk_get_rate(gtclk); Shouldn't the returned rate be checked and warn if diff is too much? Abov= e changes the rate by 0.1% which means the rate should be quite precise. So= it better be checked. > + > + dev_dbg(state->dev, "clkrate =3D %lu is_frac =3D %d\n", > + clkrate, is_frac); > + > + if (state->framer_enable) { > + xsdirxss_set(state, XSDIRX_MDL_CTRL_REG, > + XSDIRX_MDL_CTRL_FRM_EN_MASK); > + } else { > + xsdirxss_clr(state, XSDIRX_MDL_CTRL_REG, > + XSDIRX_MDL_CTRL_FRM_EN_MASK); > + } > + xsdirxss_write(state, XSDIRX_EDH_ERRCNT_EN_REG, > + state->edhmask & XSDIRX_EDH_ALLERR_MASK); > + xsdirxss_write(state, XSDIRX_VID_LOCK_WINDOW_REG, state->vidlocked); > + xsdirx_set_modedetect(state, state->searchmask); > + XSDIRX_CORE_ENABLE(state); > + xsdirxss_set(state, XSDIRX_IER_REG, XSDIRX_INTR_ALL_MASK); > + XSDIRX_GLOBAL_INTR_ENABLE(state); > +} > + > +/** > + * xsdirx_get_stream_properties - Get SDI Rx stream properties > + * @state: pointer to driver state > + * > + * This function decodes the stream's ST352 payload (if available) to = get > + * stream properties like width, height, picture type (interlaced/prog= ressive), > + * etc. > + * > + * Return: 0 for success else errors > + */ > +static int xsdirx_get_stream_properties(struct xsdirxss_state *state) > +{ > + struct device *dev =3D state->dev; > + u32 mode, payload =3D 0, val, family, valid, tscan; > + u8 byte1 =3D 0, active_luma =3D 0, pic_type =3D 0, framerate =3D 0; > + u8 sampling =3D XST352_BYTE3_COLOR_FORMAT_422; > + struct v4l2_mbus_framefmt *format =3D &state->format; > + u32 bpc =3D XST352_BYTE4_BIT_DEPTH_10; > + u32 colorimetry =3D XST352_BYTE3_COLORIMETRY_BT709; > + > + mode =3D xsdirxss_read(state, XSDIRX_MODE_DET_STAT_REG); > + mode &=3D XSDIRX_MODE_DET_STAT_RX_MODE_MASK; > + > + valid =3D xsdirxss_read(state, XSDIRX_ST352_VALID_REG); > + > + if (mode >=3D XSDIRX_MODE_3G_MASK && !valid) { > + dev_err(dev, "No valid ST352 payload present even for 3G mode and ab= ove\n"); > + return -EINVAL; > + } > + > + val =3D xsdirxss_read(state, XSDIRX_TS_DET_STAT_REG); > + if (valid & XSDIRX_ST352_VALID_DS1_MASK) { > + payload =3D xsdirxss_read(state, XSDIRX_ST352_DS1_REG); > + byte1 =3D FIELD_GET(XST352_PAYLOAD_BYTE1_MASK, payload); > + active_luma =3D FIELD_GET(XST352_BYTE3_ACT_LUMA_COUNT_MASK, > + payload); > + pic_type =3D FIELD_GET(XST352_BYTE2_PIC_TYPE_MASK, payload); > + framerate =3D FIELD_GET(XST352_BYTE2_FPS_MASK, payload); > + tscan =3D FIELD_GET(XST352_BYTE2_TS_TYPE_MASK, payload); > + sampling =3D FIELD_GET(XST352_BYTE3_COLOR_FORMAT_MASK, payload); > + bpc =3D FIELD_GET(XST352_BYTE4_BIT_DEPTH_MASK, payload); > + colorimetry =3D FIELD_GET(XST352_BYTE3_COLORIMETRY_MASK, payload); > + } else { > + dev_dbg(dev, "No ST352 payload available : Mode =3D %d\n", mode); > + framerate =3D FIELD_GET(XSDIRX_TS_DET_STAT_RATE_MASK, val); > + tscan =3D FIELD_GET(XSDIRX_TS_DET_STAT_SCAN_MASK, val); > + } > + > + if ((bpc =3D=3D XST352_BYTE4_BIT_DEPTH_10 && state->bpc !=3D 10) || > + (bpc =3D=3D XST352_BYTE4_BIT_DEPTH_12 && state->bpc !=3D 12)) { > + dev_dbg(dev, "Bit depth not supported. bpc =3D %d state->bpc =3D %d\= n", > + bpc, state->bpc); > + return -EINVAL; > + } > + > + family =3D FIELD_GET(XSDIRX_TS_DET_STAT_FAMILY_MASK, val); > + state->ts_is_interlaced =3D tscan ? false : true; > + > + dev_dbg(dev, "ts_is_interlaced =3D %d, family =3D %d\n", > + state->ts_is_interlaced, family); > + > + switch (mode) { > + case XSDIRX_MODE_HD_MASK: > + if (!valid) { > + /* No payload obtained */ > + dev_dbg(dev, "frame rate : %d, tscan =3D %d\n", > + framerate, tscan); > + /* > + * NOTE : A progressive segmented frame pSF will be > + * reported incorrectly as Interlaced as we rely on IP's > + * transport scan locked bit. > + */ > + dev_warn(dev, "pSF will be incorrectly reported as Interlaced\n"); > + > + switch (framerate) { > + case XSDIRX_TS_DET_STAT_RATE_23_98HZ: > + case XSDIRX_TS_DET_STAT_RATE_24HZ: > + case XSDIRX_TS_DET_STAT_RATE_25HZ: > + case XSDIRX_TS_DET_STAT_RATE_29_97HZ: > + case XSDIRX_TS_DET_STAT_RATE_30HZ: > + if (family =3D=3D XSDIRX_SMPTE_ST_296) { > + format->width =3D 1280; > + format->height =3D 720; > + format->field =3D V4L2_FIELD_NONE; > + } else if (family =3D=3D XSDIRX_SMPTE_ST_2048_2) { > + format->width =3D 2048; > + format->height =3D 1080; > + if (tscan) > + format->field =3D V4L2_FIELD_NONE; > + else > + format->field =3D > + V4L2_FIELD_ALTERNATE; > + } else { > + format->width =3D 1920; > + format->height =3D 1080; > + if (tscan) > + format->field =3D V4L2_FIELD_NONE; > + else > + format->field =3D > + V4L2_FIELD_ALTERNATE; > + } > + break; > + case XSDIRX_TS_DET_STAT_RATE_50HZ: > + case XSDIRX_TS_DET_STAT_RATE_59_94HZ: > + case XSDIRX_TS_DET_STAT_RATE_60HZ: > + if (family =3D=3D XSDIRX_SMPTE_ST_274) { > + format->width =3D 1920; > + format->height =3D 1080; > + } else { > + format->width =3D 1280; > + format->height =3D 720; > + } > + format->field =3D V4L2_FIELD_NONE; > + break; > + default: > + format->width =3D 1920; > + format->height =3D 1080; > + format->field =3D V4L2_FIELD_NONE; > + } > + } else { > + dev_dbg(dev, "Got the payload\n"); > + switch (byte1) { > + case XST352_BYTE1_ST292_1x720L_1_5G: > + /* SMPTE ST 292-1 for 720 line payloads */ > + format->width =3D 1280; > + format->height =3D 720; > + break; > + case XST352_BYTE1_ST292_1x1080L_1_5G: > + /* SMPTE ST 292-1 for 1080 line payloads */ > + format->height =3D 1080; > + if (active_luma) > + format->width =3D 2048; > + else > + format->width =3D 1920; > + break; > + default: > + dev_dbg(dev, "Unknown HD Mode SMPTE standard\n"); > + return -EINVAL; > + } > + } > + break; > + case XSDIRX_MODE_SD_MASK: > + format->field =3D V4L2_FIELD_ALTERNATE; > + > + switch (family) { > + case XSDIRX_NTSC: > + format->width =3D 720; > + format->height =3D 486; > + break; > + case XSDIRX_PAL: > + format->width =3D 720; > + format->height =3D 576; > + break; > + default: > + dev_dbg(dev, "Unknown SD Mode SMPTE standard\n"); > + return -EINVAL; > + } > + break; > + case XSDIRX_MODE_3G_MASK: > + switch (byte1) { > + case XST352_BYTE1_ST425_2008_750L_3GB: > + /* Sec 4.1.6.1 SMPTE 425-2008 */ > + case XST352_BYTE1_ST372_2x720L_3GB: > + /* Table 13 SMPTE 425-2008 */ > + format->width =3D 1280; > + format->height =3D 720; > + break; > + case XST352_BYTE1_ST425_2008_1125L_3GA: > + /* ST352 Table SMPTE 425-1 */ > + case XST352_BYTE1_ST372_DL_3GB: > + /* Table 13 SMPTE 425-2008 */ > + case XST352_BYTE1_ST372_2x1080L_3GB: > + /* Table 13 SMPTE 425-2008 */ > + format->height =3D 1080; > + if (active_luma) > + format->width =3D 2048; > + else > + format->width =3D 1920; > + break; > + default: > + dev_dbg(dev, "Unknown 3G Mode SMPTE standard\n"); > + return -EINVAL; > + } > + break; > + case XSDIRX_MODE_6G_MASK: > + switch (byte1) { > + case XST352_BYTE1_ST2081_10_DL_2160L_6G: > + /* Dual link 6G */ > + case XST352_BYTE1_ST2081_10_2160L_6G: > + /* Table 3 SMPTE ST 2081-10 */ > + format->height =3D 2160; > + if (active_luma) > + format->width =3D 4096; > + else > + format->width =3D 3840; > + break; > + case XST352_BYTE1_ST2081_10_2_1080L_6G: > + format->height =3D 1080; > + if (active_luma) > + format->width =3D 2048; > + else > + format->width =3D 1920; > + break; > + default: > + dev_dbg(dev, "Unknown 6G Mode SMPTE standard\n"); > + return -EINVAL; > + } > + break; > + case XSDIRX_MODE_12GI_MASK: > + case XSDIRX_MODE_12GF_MASK: > + switch (byte1) { > + case XST352_BYTE1_ST2082_10_2160L_12G: > + /* Section 4.3.1 SMPTE ST 2082-10 */ > + format->height =3D 2160; > + if (active_luma) > + format->width =3D 4096; > + else > + format->width =3D 3840; > + break; > + default: > + dev_dbg(dev, "Unknown 12G Mode SMPTE standard\n"); > + return -EINVAL; > + } > + break; > + default: > + dev_err(dev, "Invalid Mode\n"); > + return -EINVAL; > + } > + > + if (valid) { > + if (pic_type) > + format->field =3D V4L2_FIELD_NONE; > + else > + format->field =3D V4L2_FIELD_ALTERNATE; > + > + if (format->height =3D=3D 1080 && pic_type && !tscan) > + format->field =3D V4L2_FIELD_ALTERNATE; > + > + /* > + * In 3GB DL pSF mode the video is similar to interlaced. > + * So though it is a progressive video, its transport is > + * interlaced and is sent as two width x (height/2) buffers. > + */ > + if (byte1 =3D=3D XST352_BYTE1_ST372_DL_3GB) { > + if (state->ts_is_interlaced) > + format->field =3D V4L2_FIELD_ALTERNATE; > + else > + format->field =3D V4L2_FIELD_NONE; > + } > + } > + > + if (format->field =3D=3D V4L2_FIELD_ALTERNATE) > + format->height =3D format->height / 2; > + > + switch (sampling) { > + case XST352_BYTE3_COLOR_FORMAT_422: > + if (state->bpc =3D=3D 10) > + format->code =3D MEDIA_BUS_FMT_UYVY10_1X20; > + else > + format->code =3D MEDIA_BUS_FMT_UYVY12_1X24; > + break; > + case XST352_BYTE3_COLOR_FORMAT_420: > + case XST352_BYTE3_COLOR_FORMAT_YUV444: > + case XST352_BYTE3_COLOR_FORMAT_GBR: > + format->code =3D 0; > + dev_dbg(dev, "No corresponding media bus formats\n"); > + break; > + default: > + dev_err(dev, "Unsupported color format : %d\n", sampling); > + return -EINVAL; > + } > + > + /* Refer Table 3 SMPTE ST 2081-10:2018 */ > + switch (colorimetry) { > + case XST352_BYTE3_COLORIMETRY_BT709: > + format->colorspace =3D V4L2_COLORSPACE_REC709; > + break; > + /* When HDR support is added UHDTV will have BT2020 colorspace */ > + case XST352_BYTE3_COLORIMETRY_UHDTV: > + case XST352_BYTE3_COLORIMETRY_COLOR_VANC: > + case XST352_BYTE3_COLORIMETRY_UNKNOWN: > + default: > + dev_err(dev, "Unknown colorimetry : %d\n", colorimetry); > + return -EINVAL; > + } > + > + xsdirxss_get_framerate(&state->frame_interval, framerate); > + > + dev_dbg(dev, "Stream width =3D %d height =3D %d Field =3D %d payload = =3D 0x%08x ts =3D 0x%08x\n", > + format->width, format->height, format->field, payload, val); > + dev_dbg(dev, "frame rate numerator =3D %d denominator =3D %d\n", > + state->frame_interval.numerator, > + state->frame_interval.denominator); > + dev_dbg(dev, "Stream code =3D 0x%x\n", format->code); > + return 0; > +} > + > +/** > + * xsdirxss_irq_handler - Interrupt handler for SDI Rx > + * @irq: IRQ number > + * @dev_id: Pointer to device state > + * > + * The SDI Rx interrupts are cleared by writing 1 to corresponding bit= . > + * > + * Return: IRQ_HANDLED after handling interrupts > + */ > +static irqreturn_t xsdirxss_irq_handler(int irq, void *dev_id) > +{ > + struct xsdirxss_state *state =3D (struct xsdirxss_state *)dev_id; > + struct device *dev =3D state->dev; > + u32 status; > + > + status =3D xsdirxss_read(state, XSDIRX_ISR_REG); > + xsdirxss_write(state, XSDIRX_ISR_REG, status); This can be done after check below, so IO is skipped when not needed. > + dev_dbg(dev, "interrupt status =3D 0x%08x\n", status); > + > + if (!status) > + return IRQ_NONE; > + > + if (status & XSDIRX_INTR_VIDLOCK_MASK || > + status & XSDIRX_INTR_VIDUNLOCK_MASK) { > + u32 val1, val2; > + struct v4l2_event event =3D { 0 }; > + unsigned long flags; > + > + dev_dbg(dev, "video lock/unlock interrupt\n"); > + > + spin_lock_irqsave(&state->slock, flags); > + xsdirx_streamflow_control(state, false); > + > + val1 =3D xsdirxss_read(state, XSDIRX_MODE_DET_STAT_REG); > + val2 =3D xsdirxss_read(state, XSDIRX_TS_DET_STAT_REG); > + > + if ((val1 & XSDIRX_MODE_DET_STAT_MODE_LOCK_MASK) && > + (val2 & XSDIRX_TS_DET_STAT_LOCKED_MASK)) { > + u32 mask =3D XSDIRX_RST_CTRL_RST_CRC_ERRCNT_MASK | > + XSDIRX_RST_CTRL_RST_EDH_ERRCNT_MASK; > + > + dev_dbg(dev, "video lock interrupt\n"); > + > + xsdirxss_set(state, XSDIRX_RST_CTRL_REG, mask); > + xsdirxss_clr(state, XSDIRX_RST_CTRL_REG, mask); > + > + val1 =3D xsdirxss_read(state, XSDIRX_ST352_VALID_REG); > + val2 =3D xsdirxss_read(state, XSDIRX_ST352_DS1_REG); > + > + dev_dbg(dev, "valid st352 mask =3D 0x%08x\n", val1); > + dev_dbg(dev, "st352 payload =3D 0x%08x\n", val2); > + > + if (!xsdirx_get_stream_properties(state)) { > + state->vidlocked =3D true; > + xsdirxss_set_gtclk(state); > + } else { > + dev_err(dev, "Unable to get stream properties!\n"); > + state->vidlocked =3D false; > + } > + } else { > + dev_dbg(dev, "video unlock interrupt\n"); > + state->vidlocked =3D false; > + } > + spin_unlock_irqrestore(&state->slock, flags); > + > + event.type =3D V4L2_EVENT_SOURCE_CHANGE; > + event.u.src_change.changes =3D V4L2_EVENT_SRC_CH_RESOLUTION; > + v4l2_subdev_notify_event(&state->subdev, &event); > + } > + > + if (status & (XSDIRX_INTR_UNDERFLOW_MASK | XSDIRX_INTR_OVERFLOW_MASK)= ) { > + struct v4l2_event event =3D { 0 }; > + > + dev_dbg(dev, "Video in to AXI4 Stream core under/overflow interrupt\= n"); > + > + event.type =3D V4L2_EVENT_XILINX_SDIRX_UND_OVR_FLOW; > + if (status & XSDIRX_INTR_UNDERFLOW_MASK) > + event.u.data[0] =3D XILINX_SDIRX_UNDERFLOW_EVENT; > + if (status & XSDIRX_INTR_OVERFLOW_MASK) > + event.u.data[0] =3D XILINX_SDIRX_OVERFLOW_EVENT; Should be ORed? > + > + v4l2_subdev_notify_event(&state->subdev, &event); > + } > + return IRQ_HANDLED; > +} > + > +/** > + * xsdirxss_subscribe_event - Subscribe to video lock and unlock event > + * @sd: V4L2 Sub device > + * @fh: V4L2 File Handle > + * @sub: Subcribe event structure > + * > + * Return: 0 on success, errors otherwise > + */ > +static int xsdirxss_subscribe_event(struct v4l2_subdev *sd, > + struct v4l2_fh *fh, > + struct v4l2_event_subscription *sub) > +{ > + int ret; > + struct xsdirxss_state *xsdirxss =3D to_xsdirxssstate(sd); > + > + dev_dbg(xsdirxss->dev, "Event subscribed : 0x%08x\n", sub->type); > + switch (sub->type) { > + case V4L2_EVENT_XILINX_SDIRX_UND_OVR_FLOW: > + ret =3D v4l2_event_subscribe(fh, sub, XSDIRX_MAX_EVENTS, NULL); > + break; > + case V4L2_EVENT_SOURCE_CHANGE: > + ret =3D v4l2_src_change_event_subscribe(fh, sub); > + break; > + default: > + ret =3D v4l2_ctrl_subscribe_event(fh, sub); > + } > + return ret; > +} > + > +/** > + * xsdirxss_s_ctrl - This is used to set the Xilinx SDI Rx V4L2 contro= ls > + * @ctrl: V4L2 control to be set > + * > + * This function is used to set the V4L2 controls for the Xilinx SDI R= x > + * Subsystem. > + * > + * Return: 0 on success, errors otherwise > + */ > +static int xsdirxss_s_ctrl(struct v4l2_ctrl *ctrl) > +{ > + int ret =3D 0; No need to initialize this. > + struct xsdirxss_state *xsdirxss =3D > + container_of(ctrl->handler, struct xsdirxss_state, > + ctrl_handler); > + struct device *dev =3D xsdirxss->dev; > + unsigned long flags; > + > + dev_dbg(dev, "set ctrl id =3D 0x%08x val =3D 0x%08x\n", > + ctrl->id, ctrl->val); > + > + spin_lock_irqsave(&xsdirxss->slock, flags); > + > + if (xsdirxss->streaming) { > + spin_unlock_irqrestore(&xsdirxss->slock, flags); > + dev_err(dev, "Cannot set controls while streaming\n"); > + return -EINVAL; > + } > + > + XSDIRX_CORE_DISABLE(xsdirxss); > + switch (ctrl->id) { > + case V4L2_CID_XILINX_SDIRX_FRAMER: > + xsdirxss->framer_enable =3D ctrl->val; > + if (xsdirxss->framer_enable) { > + xsdirxss_set(xsdirxss, XSDIRX_MDL_CTRL_REG, > + XSDIRX_MDL_CTRL_FRM_EN_MASK); > + } else { > + xsdirxss_clr(xsdirxss, XSDIRX_MDL_CTRL_REG, > + XSDIRX_MDL_CTRL_FRM_EN_MASK); > + } > + break; > + case V4L2_CID_XILINX_SDIRX_VIDLOCK_WINDOW: > + /* > + * The video lock window is the amount of time for which the > + * the mode and transport stream should be locked to get the > + * video lock interrupt. > + */ > + xsdirxss->vidlockwin =3D ctrl->val; > + xsdirxss_write(xsdirxss, XSDIRX_VID_LOCK_WINDOW_REG, > + xsdirxss->vidlockwin); > + break; > + case V4L2_CID_XILINX_SDIRX_EDH_ERROR_SOURCES: > + xsdirxss->edhmask =3D ctrl->val & XSDIRX_EDH_ALLERR_MASK; > + xsdirxss_write(xsdirxss, XSDIRX_EDH_ERRCNT_EN_REG, > + xsdirxss->edhmask); > + break; > + case V4L2_CID_XILINX_SDIRX_SEARCH_MODES: > + if (!ctrl->val) { > + spin_unlock_irqrestore(&xsdirxss->slock, flags); > + dev_err(dev, "Select at least one mode!\n"); > + return -EINVAL; > + } > + > + if (xsdirxss->mode =3D=3D XSDI_STD_3G) { > + dev_dbg(dev, "Upto 3G supported\n"); > + ctrl->val &=3D ~(BIT(XSDIRX_MODE_6G_OFFSET) | > + BIT(XSDIRX_MODE_12GI_OFFSET) | > + BIT(XSDIRX_MODE_12GF_OFFSET)); > + } > + > + if (xsdirxss->mode =3D=3D XSDI_STD_6G) { > + dev_dbg(dev, "Upto 6G supported\n"); > + ctrl->val &=3D ~(BIT(XSDIRX_MODE_12GI_OFFSET) | > + BIT(XSDIRX_MODE_12GF_OFFSET)); > + } > + > + ret =3D xsdirx_set_modedetect(xsdirxss, ctrl->val); > + if (!ret) > + xsdirxss->searchmask =3D ctrl->val; > + break; > + default: > + ret =3D -EINVAL; > + break; > + } > + XSDIRX_CORE_ENABLE(xsdirxss); > + > + spin_unlock_irqrestore(&xsdirxss->slock, flags); > + return ret; > +} > + > +/** > + * xsdirxss_g_volatile_ctrl - get the Xilinx SDI Rx controls > + * @ctrl: Pointer to V4L2 control > + * > + * Return: 0 on success, errors otherwise > + */ > +static int xsdirxss_g_volatile_ctrl(struct v4l2_ctrl *ctrl) > +{ > + u32 val; > + struct xsdirxss_state *xsdirxss =3D > + container_of(ctrl->handler, > + struct xsdirxss_state, ctrl_handler); > + struct device *dev =3D xsdirxss->dev; > + unsigned long flags; > + > + spin_lock_irqsave(&xsdirxss->slock, flags); > + if (!xsdirxss->vidlocked) { > + spin_unlock_irqrestore(&xsdirxss->slock, flags); > + dev_err(dev, "Can't get values when video not locked!\n"); > + return -EINVAL; > + } > + switch (ctrl->id) { > + case V4L2_CID_XILINX_SDIRX_MODE_DETECT: > + val =3D xsdirxss_read(xsdirxss, XSDIRX_MODE_DET_STAT_REG); > + val &=3D XSDIRX_MODE_DET_STAT_RX_MODE_MASK; > + > + switch (val) { > + case XSDIRX_MODE_SD_MASK: > + ctrl->val =3D XSDIRX_MODE_SD_OFFSET; > + break; > + case XSDIRX_MODE_HD_MASK: > + ctrl->val =3D XSDIRX_MODE_HD_OFFSET; > + break; > + case XSDIRX_MODE_3G_MASK: > + val =3D xsdirxss_read(xsdirxss, XSDIRX_MODE_DET_STAT_REG); > + val &=3D XSDIRX_MODE_DET_STAT_LVLB_3G_MASK; > + ctrl->val =3D val ? XSDIRX_MODE_3GB_OFFSET : > + XSDIRX_MODE_3GA_OFFSET; > + break; > + case XSDIRX_MODE_6G_MASK: > + ctrl->val =3D XSDIRX_MODE_6G_OFFSET; > + break; > + case XSDIRX_MODE_12GI_MASK: > + ctrl->val =3D XSDIRX_MODE_12GI_OFFSET; > + break; > + case XSDIRX_MODE_12GF_MASK: > + ctrl->val =3D XSDIRX_MODE_12GF_OFFSET; > + break; > + } > + break; > + case V4L2_CID_XILINX_SDIRX_CRC: > + ctrl->val =3D xsdirxss_read(xsdirxss, XSDIRX_CRC_ERRCNT_REG); > + xsdirxss_write(xsdirxss, XSDIRX_CRC_ERRCNT_REG, 0xffff); > + break; > + case V4L2_CID_XILINX_SDIRX_EDH_ERRCNT: > + val =3D xsdirxss_read(xsdirxss, XSDIRX_MODE_DET_STAT_REG); > + val &=3D XSDIRX_MODE_DET_STAT_RX_MODE_MASK; > + if (val =3D=3D XSDIRX_MODE_SD_MASK) { > + ctrl->val =3D xsdirxss_read(xsdirxss, > + XSDIRX_EDH_ERRCNT_REG); > + } else { > + spin_unlock_irqrestore(&xsdirxss->slock, flags); > + dev_dbg(dev, "%d - not in SD mode\n", ctrl->id); > + return -EINVAL; > + } > + break; > + case V4L2_CID_XILINX_SDIRX_EDH_STATUS: > + val =3D xsdirxss_read(xsdirxss, XSDIRX_MODE_DET_STAT_REG); > + val &=3D XSDIRX_MODE_DET_STAT_RX_MODE_MASK; > + if (val =3D=3D XSDIRX_MODE_SD_MASK) { > + ctrl->val =3D xsdirxss_read(xsdirxss, > + XSDIRX_EDH_STAT_REG); > + } else { > + spin_unlock_irqrestore(&xsdirxss->slock, flags); > + dev_dbg(dev, "%d - not in SD mode\n", ctrl->id); > + return -EINVAL; > + } > + break; > + case V4L2_CID_XILINX_SDIRX_TS_IS_INTERLACED: > + ctrl->val =3D xsdirxss->ts_is_interlaced; > + break; > + default: > + spin_unlock_irqrestore(&xsdirxss->slock, flags); > + dev_err(dev, "Get Invalid control id 0x%0x\n", ctrl->id); > + return -EINVAL; > + } > + > + spin_unlock_irqrestore(&xsdirxss->slock, flags); > + return 0; > +} > + > +/** > + * xsdirxss_log_status - Logs the status of the SDI Rx Subsystem > + * @sd: Pointer to V4L2 subdevice structure > + * > + * This function prints the current status of Xilinx SDI Rx Subsystem > + * > + * Return: 0 on success > + */ > +static int xsdirxss_log_status(struct v4l2_subdev *sd) > +{ > + struct xsdirxss_state *xsdirxss =3D to_xsdirxssstate(sd); > + u32 i; > + > + v4l2_info(sd, "***** SDI Rx subsystem reg dump start *****\n"); > + v4l2_info(sd, "No : Register Name : Value\n"); > + for (i =3D 0; i < ARRAY_SIZE(xsdirxss_regmap); i++) { > + v4l2_info(sd, "%02d : %s register : 0x%08x\n", i, > + xsdirxss_regmap[i].name, > + xsdirxss_read(xsdirxss, xsdirxss_regmap[i].offset)); > + } > + v4l2_info(sd, "***** SDI Rx subsystem reg dump end *****\n"); > + > + v4l2_ctrl_subdev_log_status(sd); > + > + return 0; > +} > + > +/** > + * xsdirxss_g_frame_interval - Get the frame interval > + * @sd: V4L2 Sub device > + * @fi: Pointer to V4l2 Sub device frame interval structure > + * > + * This function is used to get the frame interval. > + * The frame rate can be integral or fractional. > + * Integral frame rate e.g. numerator =3D 1000, denominator =3D 24000 = =3D> 24 fps > + * Fractional frame rate e.g. numerator =3D 1001, denominator =3D 2400= 0 =3D> 23.97 fps > + * > + * Return: 0 on success > + */ > +static int xsdirxss_g_frame_interval(struct v4l2_subdev *sd, > + struct v4l2_subdev_frame_interval *fi) > +{ > + struct xsdirxss_state *xsdirxss =3D to_xsdirxssstate(sd); > + unsigned long flags; > + > + if (!xsdirxss->vidlocked) { Shouldn't this be accessed under spinlock? > + dev_err(xsdirxss->dev, "Video not locked!\n"); > + return -EINVAL; > + } > + > + spin_lock_irqsave(&xsdirxss->slock, flags); > + fi->interval =3D xsdirxss->frame_interval; > + spin_unlock_irqrestore(&xsdirxss->slock, flags); > + > + dev_dbg(xsdirxss->dev, "frame rate numerator =3D %d denominator =3D %= d\n", > + xsdirxss->frame_interval.numerator, > + xsdirxss->frame_interval.denominator); This too. > + return 0; > +} > + > +/** > + * xsdirxss_s_stream - It is used to start/stop the streaming. > + * @sd: V4L2 Sub device > + * @enable: Flag (True / False) > + * > + * This function controls the start or stop of streaming for the > + * Xilinx SDI Rx Subsystem. > + * > + * Return: 0 on success, errors otherwise > + */ > +static int xsdirxss_s_stream(struct v4l2_subdev *sd, int enable) > +{ > + struct xsdirxss_state *xsdirxss =3D to_xsdirxssstate(sd); > + struct device *dev =3D xsdirxss->dev; > + unsigned long flags; > + > + spin_lock_irqsave(&xsdirxss->slock, flags); > + if (enable =3D=3D xsdirxss->streaming) { > + spin_unlock_irqrestore(&xsdirxss->slock, flags); > + dev_dbg(dev, "already in same streaming state as requested\n"); > + return 0; > + } > + > + if (enable) { > + if (!xsdirxss->vidlocked) { > + spin_unlock_irqrestore(&xsdirxss->slock, flags); > + dev_err(dev, "Video is not locked\n"); > + return -EINVAL; > + } > + xsdirx_streamflow_control(xsdirxss, true); > + } else { > + xsdirx_streamflow_control(xsdirxss, false); This can move out of this if statement, passing enable or !!enable direct= ly. Up to you. > + } > + spin_unlock_irqrestore(&xsdirxss->slock, flags); > + dev_dbg(dev, "Streaming %s\n", enable ? "started" : "stopped"); > + return 0; > +} > + > +/** > + * xsdirxss_g_input_status - It is used to determine if the video sign= al > + * is present / locked onto or not. > + * > + * @sd: V4L2 Sub device > + * @status: status of signal locked > + * > + * This is used to determine if the video signal is present and locked= onto > + * by the SDI Rx core or not based on vidlocked flag. > + * > + * Return: zero on success > + */ > +static int xsdirxss_g_input_status(struct v4l2_subdev *sd, u32 *status= ) > +{ > + struct xsdirxss_state *xsdirxss =3D to_xsdirxssstate(sd); > + unsigned long flags; > + > + spin_lock_irqsave(&xsdirxss->slock, flags); > + if (!xsdirxss->vidlocked) > + *status =3D V4L2_IN_ST_NO_SYNC | V4L2_IN_ST_NO_SIGNAL; > + else > + *status =3D 0; > + > + spin_unlock_irqrestore(&xsdirxss->slock, flags); > + return 0; > +} > + > +static struct v4l2_mbus_framefmt * > +__xsdirxss_get_pad_format(struct xsdirxss_state *xsdirxss, > + struct v4l2_subdev_pad_config *cfg, > + unsigned int pad, u32 which) > +{ > + switch (which) { > + case V4L2_SUBDEV_FORMAT_TRY: > + return v4l2_subdev_get_try_format(&xsdirxss->subdev, cfg, pad); > + case V4L2_SUBDEV_FORMAT_ACTIVE: > + return &xsdirxss->src_format; > + default: > + return NULL; > + } > +} > + > +/** > + * xsdirxss_init_cfg - Initialise the pad format config to default > + * @sd: Pointer to V4L2 Sub device structure > + * @cfg: Pointer to sub device pad information structure > + * > + * This function is used to initialize the pad format with the default > + * values. > + * > + * Return: 0 on success > + */ > +static int xsdirxss_init_cfg(struct v4l2_subdev *sd, > + struct v4l2_subdev_pad_config *cfg) > +{ > + struct xsdirxss_state *xsdirxss =3D to_xsdirxssstate(sd); > + struct v4l2_mbus_framefmt *format; > + > + format =3D v4l2_subdev_get_try_format(sd, cfg, 0); > + *format =3D xsdirxss->default_format; > + > + return 0; > +} > + > +/** > + * xsdirxss_get_set_format - This is used to get/set the pad format > + * @sd: Pointer to V4L2 Sub device structure > + * @cfg: Pointer to sub device pad information structure > + * @fmt: Pointer to pad level media bus format > + * > + * This function is used to get and set the pad format. > + * Since the pad format is fixed in hardware, it can't be > + * modified on run time. So set and get are same. > + * > + * Return: 0 on success > + */ > +static int xsdirxss_get_set_format(struct v4l2_subdev *sd, > + struct v4l2_subdev_pad_config *cfg, > + struct v4l2_subdev_format *fmt) > +{ > + struct xsdirxss_state *xsdirxss =3D to_xsdirxssstate(sd); > + unsigned long flags; > + > + spin_lock_irqsave(&xsdirxss->slock, flags); > + if (!xsdirxss->vidlocked) { > + spin_unlock_irqrestore(&xsdirxss->slock, flags); > + dev_err(xsdirxss->dev, "Video not locked!\n"); > + return -EINVAL; > + } > + > + fmt->format =3D *__xsdirxss_get_pad_format(xsdirxss, cfg, > + fmt->pad, fmt->which); > + > + spin_unlock_irqrestore(&xsdirxss->slock, flags); > + dev_dbg(xsdirxss->dev, > + "stream width %d height %d code %d field %d colorspace %d xfer_func = %d quantization %d\n", > + fmt->format.width, fmt->format.height, > + fmt->format.code, fmt->format.field, > + fmt->format.colorspace, fmt->format.xfer_func, > + fmt->format.quantization); > + return 0; > +} > + > +/** > + * xsdirxss_enum_mbus_code - Handle pixel format enumeration > + * @sd: pointer to v4l2 subdev structure > + * @cfg: V4L2 subdev pad configuration > + * @code: pointer to v4l2_subdev_mbus_code_enum structure > + * > + * Return: -EINVAL or zero on success > + */ > +static int xsdirxss_enum_mbus_code(struct v4l2_subdev *sd, > + struct v4l2_subdev_pad_config *cfg, > + struct v4l2_subdev_mbus_code_enum *code) > +{ > + struct xsdirxss_state *xsdirxss =3D to_xsdirxssstate(sd); > + u32 index =3D code->index; > + u32 maxindex; > + > + if (xsdirxss->bpc =3D=3D 10) > + maxindex =3D ARRAY_SIZE(xsdirxss_10bpc_mbus_fmts); > + else > + maxindex =3D ARRAY_SIZE(xsdirxss_12bpc_mbus_fmts); > + > + if (code->pad || index >=3D maxindex) > + return -EINVAL; > + > + if (xsdirxss->bpc =3D=3D 10) > + code->code =3D xsdirxss_10bpc_mbus_fmts[index]; > + else > + code->code =3D xsdirxss_12bpc_mbus_fmts[index]; > + > + return 0; > +} > + > +/** > + * xsdirxss_enum_dv_timings - Enumerate all the supported DV timings > + * @sd: pointer to v4l2 subdev structure > + * @timings: DV timings structure to be returned. > + * > + * Return: -EINVAL incase of invalid index and pad or zero on success > + */ > +static int xsdirxss_enum_dv_timings(struct v4l2_subdev *sd, > + struct v4l2_enum_dv_timings *timings) > +{ > + if (timings->index >=3D ARRAY_SIZE(fmt_cap)) > + return -EINVAL; > + > + if (timings->pad !=3D 0) > + return -EINVAL; > + > + timings->timings =3D fmt_cap[timings->index]; > + return 0; > +} > + > +/** > + * xsdirxss_query_dv_timings - Query for the current DV timings > + * @sd: pointer to v4l2 subdev structure > + * @timings: DV timings structure to be returned. > + * > + * Return: -ENOLCK when video is not locked, -ERANGE when correspondin= g timing > + * entry is not found or zero on success. > + */ > +static int xsdirxss_query_dv_timings(struct v4l2_subdev *sd, > + struct v4l2_dv_timings *timings) > +{ > + struct xsdirxss_state *state =3D to_xsdirxssstate(sd); > + unsigned int i; > + unsigned long flags; > + > + spin_lock_irqsave(&state->slock, flags); > + if (!state->vidlocked) { > + spin_unlock_irqrestore(&state->slock, flags); > + return -ENOLCK; > + } > + > + for (i =3D 0; i < ARRAY_SIZE(xsdirxss_dv_timings); i++) { > + if (state->format.width =3D=3D xsdirxss_dv_timings[i].width && > + state->format.height =3D=3D xsdirxss_dv_timings[i].height && > + state->frame_interval.denominator =3D=3D > + (xsdirxss_dv_timings[i].fps * 1000)) { > + *timings =3D xsdirxss_dv_timings[i].timing; > + state->detected_timings_index =3D i; > + spin_unlock_irqrestore(&state->slock, flags); > + return 0; > + } > + } > + spin_unlock_irqrestore(&state->slock, flags); > + > + return -ERANGE; > +} > + > +static int xsdirxss_s_dv_timings(struct v4l2_subdev *sd, > + struct v4l2_dv_timings *timings) > +{ > + struct xsdirxss_state *state =3D to_xsdirxssstate(sd); > + u32 i =3D state->detected_timings_index; > + unsigned long flags; > + > + spin_lock_irqsave(&state->slock, flags); > + if (!state->vidlocked) { > + spin_unlock_irqrestore(&state->slock, flags); > + return -EINVAL; > + } > + Is the spinlock needed to be held for below? > + /* input timing should match query dv_timing */ > + if (!v4l2_match_dv_timings(timings, > + &xsdirxss_dv_timings[i].timing, > + 0, false)) { > + spin_unlock_irqrestore(&state->slock, flags); > + return -EINVAL; > + } > + > + state->current_timings =3D *timings; > + > + /* Update the media bus format */ > + state->src_format =3D state->format; > + spin_unlock_irqrestore(&state->slock, flags); > + > + return 0; > +} > + > +static int xsdirxss_g_dv_timings(struct v4l2_subdev *sd, > + struct v4l2_dv_timings *timings) > +{ > + struct xsdirxss_state *state =3D to_xsdirxssstate(sd); > + > + *timings =3D state->current_timings; This needs the lock if above doesn't change, at least per lock descriptio= n. > + return 0; > +} > + > +static int xsdirxss_dv_timings_cap(struct v4l2_subdev *sd, > + struct v4l2_dv_timings_cap *cap) > +{ > + if (cap->pad !=3D 0) > + return -EINVAL; > + > + *cap =3D xsdirxss_timings_cap; > + return 0; > +} > + > +/* -------------------------------------------------------------------= ---------- > + * Media Operations > + */ > + > +static const struct media_entity_operations xsdirxss_media_ops =3D { > + .link_validate =3D v4l2_subdev_link_validate > +}; > + > +static const struct v4l2_ctrl_ops xsdirxss_ctrl_ops =3D { > + .g_volatile_ctrl =3D xsdirxss_g_volatile_ctrl, > + .s_ctrl =3D xsdirxss_s_ctrl > +}; > + > +static const struct v4l2_ctrl_config xsdirxss_edh_ctrls[] =3D { > + { > + .ops =3D &xsdirxss_ctrl_ops, > + .id =3D V4L2_CID_XILINX_SDIRX_EDH_ERROR_SOURCES, > + .name =3D "SDI Rx : EDH Error Count Enable", > + .type =3D V4L2_CTRL_TYPE_BITMASK, > + .min =3D 0, > + .max =3D XSDIRX_EDH_ALLERR_MASK, > + .def =3D 0, > + }, { > + .ops =3D &xsdirxss_ctrl_ops, > + .id =3D V4L2_CID_XILINX_SDIRX_EDH_ERRCNT, > + .name =3D "SDI Rx : EDH Error Count", > + .type =3D V4L2_CTRL_TYPE_INTEGER, > + .min =3D 0, > + .max =3D 0xffff, > + .step =3D 1, > + .def =3D 0, > + .flags =3D V4L2_CTRL_FLAG_VOLATILE | V4L2_CTRL_FLAG_READ_ONLY, > + }, { > + .ops =3D &xsdirxss_ctrl_ops, > + .id =3D V4L2_CID_XILINX_SDIRX_EDH_STATUS, > + .name =3D "SDI Rx : EDH Status", > + .type =3D V4L2_CTRL_TYPE_INTEGER, > + .min =3D 0, > + .max =3D 0xffffffff, > + .step =3D 1, > + .def =3D 0, > + .flags =3D V4L2_CTRL_FLAG_VOLATILE | V4L2_CTRL_FLAG_READ_ONLY, > + } > +}; > + > +static const struct v4l2_ctrl_config xsdirxss_ctrls[] =3D { > + { > + .ops =3D &xsdirxss_ctrl_ops, > + .id =3D V4L2_CID_XILINX_SDIRX_FRAMER, > + .name =3D "SDI Rx : Enable Framer", > + .type =3D V4L2_CTRL_TYPE_BOOLEAN, > + .min =3D false, > + .max =3D true, > + .step =3D 1, > + .def =3D true, > + }, { > + .ops =3D &xsdirxss_ctrl_ops, > + .id =3D V4L2_CID_XILINX_SDIRX_VIDLOCK_WINDOW, > + .name =3D "SDI Rx : Video Lock Window", > + .type =3D V4L2_CTRL_TYPE_INTEGER, > + .min =3D 0, > + .max =3D 0xffffffff, > + .step =3D 1, > + .def =3D XSDIRX_DEFAULT_VIDEO_LOCK_WINDOW, > + }, { > + .ops =3D &xsdirxss_ctrl_ops, > + .id =3D V4L2_CID_XILINX_SDIRX_SEARCH_MODES, > + .name =3D "SDI Rx : Modes search Mask", > + .type =3D V4L2_CTRL_TYPE_BITMASK, > + .min =3D 0, > + .max =3D XSDIRX_DETECT_ALL_MODES, > + .def =3D XSDIRX_DETECT_ALL_MODES, > + }, { > + .ops =3D &xsdirxss_ctrl_ops, > + .id =3D V4L2_CID_XILINX_SDIRX_MODE_DETECT, > + .name =3D "SDI Rx : Mode Detect Status", > + .type =3D V4L2_CTRL_TYPE_INTEGER, > + .min =3D XSDIRX_MODE_SD_OFFSET, > + .max =3D XSDIRX_MODE_12GF_OFFSET, > + .step =3D 1, > + .flags =3D V4L2_CTRL_FLAG_VOLATILE | V4L2_CTRL_FLAG_READ_ONLY, > + }, { > + .ops =3D &xsdirxss_ctrl_ops, > + .id =3D V4L2_CID_XILINX_SDIRX_CRC, > + .name =3D "SDI Rx : CRC Error status", > + .type =3D V4L2_CTRL_TYPE_INTEGER, > + .min =3D 0, > + .max =3D 0xffffffff, > + .step =3D 1, > + .def =3D 0, > + .flags =3D V4L2_CTRL_FLAG_VOLATILE | V4L2_CTRL_FLAG_READ_ONLY, > + }, { > + .ops =3D &xsdirxss_ctrl_ops, > + .id =3D V4L2_CID_XILINX_SDIRX_TS_IS_INTERLACED, > + .name =3D "SDI Rx : TS is Interlaced", > + .type =3D V4L2_CTRL_TYPE_BOOLEAN, > + .min =3D false, > + .max =3D true, > + .def =3D false, > + .step =3D 1, > + .flags =3D V4L2_CTRL_FLAG_VOLATILE | V4L2_CTRL_FLAG_READ_ONLY, > + }, > +}; > + > +static const struct v4l2_subdev_core_ops xsdirxss_core_ops =3D { > + .log_status =3D xsdirxss_log_status, > + .subscribe_event =3D xsdirxss_subscribe_event, > + .unsubscribe_event =3D v4l2_event_subdev_unsubscribe, > +}; > + > +static const struct v4l2_subdev_video_ops xsdirxss_video_ops =3D { > + .g_frame_interval =3D xsdirxss_g_frame_interval, > + .s_stream =3D xsdirxss_s_stream, > + .g_input_status =3D xsdirxss_g_input_status, > + .query_dv_timings =3D xsdirxss_query_dv_timings, > + .g_dv_timings =3D xsdirxss_g_dv_timings, > + .s_dv_timings =3D xsdirxss_s_dv_timings, > +}; > + > +static const struct v4l2_subdev_pad_ops xsdirxss_pad_ops =3D { > + .init_cfg =3D xsdirxss_init_cfg, > + .get_fmt =3D xsdirxss_get_set_format, > + .set_fmt =3D xsdirxss_get_set_format, > + .enum_mbus_code =3D xsdirxss_enum_mbus_code, > + .enum_dv_timings =3D xsdirxss_enum_dv_timings, > + .dv_timings_cap =3D xsdirxss_dv_timings_cap, > +}; > + > +static const struct v4l2_subdev_ops xsdirxss_ops =3D { > + .core =3D &xsdirxss_core_ops, > + .video =3D &xsdirxss_video_ops, > + .pad =3D &xsdirxss_pad_ops > +}; > + > +/* -------------------------------------------------------------------= ---------- > + * Platform Device Driver > + */ > + > +static int xsdirxss_parse_of(struct xsdirxss_state *xsdirxss) > +{ > + struct device_node *node =3D xsdirxss->dev->of_node; > + struct device *dev =3D xsdirxss->dev; > + int ret; > + > + xsdirxss->include_edh =3D of_property_read_bool(node, "xlnx,include-e= dh"); > + dev_dbg(dev, "EDH property =3D %s\n", > + xsdirxss->include_edh ? "Present" : "Absent"); > + > + ret =3D of_property_read_u32(node, "xlnx,line-rate", &xsdirxss->mode)= ; > + if (ret < 0) { > + dev_err(dev, "xlnx,line-rate property not found\n"); > + return ret; > + } > + > + if (xsdirxss->mode !=3D XSDI_STD_3G && xsdirxss->mode !=3D XSDI_STD_6= G && > + xsdirxss->mode !=3D XSDI_STD_12G_8DS) { > + dev_err(dev, "Invalid Line Rate\n"); > + return -EINVAL; > + } > + > + dev_dbg(dev, "SDI Rx Line Rate / mode =3D %d\n", xsdirxss->mode); > + > + ret =3D of_property_read_u32(node, "xlnx,bpc", &xsdirxss->bpc); > + if (ret =3D=3D -EINVAL) { > + xsdirxss->bpc =3D 10; > + dev_dbg(dev, "set default bpc as 10\n"); > + } else if (ret < 0) { > + dev_err(dev, "failed to get xlnx,bpc\n"); > + return ret; > + } > + > + if (xsdirxss->bpc !=3D 10 && xsdirxss->bpc !=3D 12) { > + dev_err(dev, "bits per component=3D%u. Can be 10 or 12 only\n", > + xsdirxss->bpc); > + return -EINVAL; > + } > + > + return ret; > +} > + > +static int xsdirxss_probe(struct platform_device *pdev) > +{ > + struct v4l2_subdev *subdev; > + struct xsdirxss_state *xsdirxss; > + struct device *dev; > + int ret, irq; > + unsigned int num_ctrls, i; > + > + xsdirxss =3D devm_kzalloc(&pdev->dev, sizeof(*xsdirxss), GFP_KERNEL); > + if (!xsdirxss) > + return -ENOMEM; > + > + xsdirxss->dev =3D &pdev->dev; > + dev =3D xsdirxss->dev; > + > + spin_lock_init(&xsdirxss->slock); > + ret =3D xsdirxss_parse_of(xsdirxss); > + if (ret < 0) > + return ret; > + > + xsdirxss->iomem =3D devm_platform_ioremap_resource(pdev, 0); > + if (IS_ERR(xsdirxss->iomem)) > + return PTR_ERR(xsdirxss->iomem); > + > + xsdirxss->num_clks =3D ARRAY_SIZE(xsdirxss_clks); > + xsdirxss->clks =3D devm_kcalloc(dev, xsdirxss->num_clks, > + sizeof(*xsdirxss->clks), GFP_KERNEL); > + if (!xsdirxss->clks) > + return -ENOMEM; > + > + for (i =3D 0; i < xsdirxss->num_clks; i++) > + xsdirxss->clks[i].id =3D xsdirxss_clks[i]; > + > + ret =3D devm_clk_bulk_get(dev, xsdirxss->num_clks, xsdirxss->clks); > + if (ret) > + return ret; > + > + ret =3D clk_bulk_prepare_enable(xsdirxss->num_clks, xsdirxss->clks); > + if (ret) > + return ret; > + > + /* Reset the core */ > + xsdirx_streamflow_control(xsdirxss, false); > + XSDIRX_CORE_DISABLE(xsdirxss); > + /* Clear all interrupts */ > + xsdirxss_set(xsdirxss, XSDIRX_ISR_REG, XSDIRX_INTR_ALL_MASK); > + xsdirxss_clr(xsdirxss, XSDIRX_IER_REG, XSDIRX_INTR_ALL_MASK); > + xsdirxss_set(xsdirxss, XSDIRX_IER_REG, XSDIRX_INTR_ALL_MASK); > + XSDIRX_GLOBAL_INTR_ENABLE(xsdirxss); Looking here, inlining the macro will be better. xsdirxss_set(xsdirxss, XSDIRX_GLBL_IER_REG, XSDIRX_GLBL_INTR_EN_MASK) > + xsdirxss_write(xsdirxss, XSDIRX_CRC_ERRCNT_REG, 0xffff); > + > + /* Register interrupt handler */ > + irq =3D platform_get_irq(pdev, 0); > + ret =3D devm_request_threaded_irq(dev, irq, NULL, xsdirxss_irq_handle= r, > + IRQF_ONESHOT, dev_name(dev), xsdirxss); > + if (ret) { > + dev_err(dev, "Err =3D %d Interrupt handler reg failed!\n", > + ret); > + goto clk_err; > + } > + > + /* Initialize V4L2 subdevice and media entity */ > + xsdirxss->pad.flags =3D MEDIA_PAD_FL_SOURCE; > + > + /* Initialize the default format */ > + if (xsdirxss->bpc =3D=3D 10) > + xsdirxss->default_format.code =3D MEDIA_BUS_FMT_UYVY10_1X20; > + else > + xsdirxss->default_format.code =3D MEDIA_BUS_FMT_UYVY12_1X24; > + xsdirxss->default_format.field =3D V4L2_FIELD_NONE; > + xsdirxss->default_format.colorspace =3D V4L2_COLORSPACE_REC709; > + xsdirxss->default_format.width =3D XSDIRX_DEFAULT_WIDTH; > + xsdirxss->default_format.height =3D XSDIRX_DEFAULT_HEIGHT; > + xsdirxss->default_format.xfer_func =3D V4L2_XFER_FUNC_709; > + xsdirxss->default_format.quantization =3D V4L2_QUANTIZATION_LIM_RANGE= ; > + > + xsdirxss->format =3D xsdirxss->default_format; > + > + /* Initialize V4L2 subdevice and media entity */ > + subdev =3D &xsdirxss->subdev; > + v4l2_subdev_init(subdev, &xsdirxss_ops); > + > + subdev->dev =3D &pdev->dev; > + strscpy(subdev->name, dev_name(dev), sizeof(subdev->name)); > + > + subdev->flags =3D V4L2_SUBDEV_FL_HAS_EVENTS | V4L2_SUBDEV_FL_HAS_DEVN= ODE; > + > + subdev->entity.ops =3D &xsdirxss_media_ops; > + > + v4l2_set_subdevdata(subdev, xsdirxss); > + > + ret =3D media_entity_pads_init(&subdev->entity, 1, &xsdirxss->pad); > + if (ret < 0) > + goto error; > + > + /* Initialise and register the controls */ > + num_ctrls =3D ARRAY_SIZE(xsdirxss_ctrls); > + > + if (xsdirxss->include_edh) > + num_ctrls +=3D ARRAY_SIZE(xsdirxss_edh_ctrls); > + > + v4l2_ctrl_handler_init(&xsdirxss->ctrl_handler, num_ctrls); > + > + for (i =3D 0; i < ARRAY_SIZE(xsdirxss_ctrls); i++) { > + struct v4l2_ctrl *ctrl; > + > + dev_dbg(dev, "%d %s ctrl =3D 0x%x\n", i, xsdirxss_ctrls[i].name, > + xsdirxss_ctrls[i].id); > + > + ctrl =3D v4l2_ctrl_new_custom(&xsdirxss->ctrl_handler, > + &xsdirxss_ctrls[i], NULL); > + } > + > + if (xsdirxss->include_edh) { > + for (i =3D 0; i < ARRAY_SIZE(xsdirxss_edh_ctrls); i++) { > + struct v4l2_ctrl *ctrl; > + > + dev_dbg(dev, "%d %s ctrl =3D 0x%x\n", i, > + xsdirxss_edh_ctrls[i].name, > + xsdirxss_edh_ctrls[i].id); > + > + ctrl =3D v4l2_ctrl_new_custom(&xsdirxss->ctrl_handler, > + &xsdirxss_edh_ctrls[i], > + NULL); > + } > + } > + > + if (xsdirxss->ctrl_handler.error) { > + dev_err(dev, "failed to add controls\n"); > + ret =3D xsdirxss->ctrl_handler.error; > + goto error; > + } > + > + subdev->ctrl_handler =3D &xsdirxss->ctrl_handler; > + > + ret =3D v4l2_ctrl_handler_setup(&xsdirxss->ctrl_handler); > + if (ret < 0) { > + dev_err(dev, "failed to set controls\n"); > + goto error; > + } > + > + platform_set_drvdata(pdev, xsdirxss); > + > + ret =3D v4l2_async_register_subdev(subdev); > + if (ret < 0) { > + dev_err(dev, "failed to register subdev\n"); > + goto error; > + } > + > + xsdirxss->prev_is_frac =3D -1; > + > + XSDIRX_CORE_ENABLE(xsdirxss); > + > + return 0; Nit. Ane empty line. > +error: > + v4l2_ctrl_handler_free(&xsdirxss->ctrl_handler); > + media_entity_cleanup(&subdev->entity); > + XSDIRX_GLOBAL_INTR_DISABLE(xsdirxss); > + xsdirxss_clr(xsdirxss, XSDIRX_IER_REG, XSDIRX_INTR_ALL_MASK); > +clk_err: > + clk_bulk_disable_unprepare(xsdirxss->num_clks, xsdirxss->clks); > + return ret; > +} > + > +static int xsdirxss_remove(struct platform_device *pdev) > +{ > + struct xsdirxss_state *xsdirxss =3D platform_get_drvdata(pdev); > + struct v4l2_subdev *subdev =3D &xsdirxss->subdev; > + > + XSDIRX_CORE_DISABLE(xsdirxss); > + XSDIRX_GLOBAL_INTR_DISABLE(xsdirxss); > + xsdirxss_clr(xsdirxss, XSDIRX_IER_REG, XSDIRX_INTR_ALL_MASK); > + xsdirx_streamflow_control(xsdirxss, false); > + > + v4l2_async_unregister_subdev(subdev); > + v4l2_ctrl_handler_free(&xsdirxss->ctrl_handler); > + media_entity_cleanup(&subdev->entity); > + > + clk_bulk_disable_unprepare(xsdirxss->num_clks, xsdirxss->clks); > + > + return 0; > +} > + > +static const struct of_device_id xsdirxss_of_id_table[] =3D { > + { .compatible =3D "xlnx,v-smpte-uhdsdi-rx-ss-2.0" }, > + { } > +}; > +MODULE_DEVICE_TABLE(of, xsdirxss_of_id_table); > + > +static struct platform_driver xsdirxss_driver =3D { > + .driver =3D { > + .name =3D "xilinx-sdirxss", > + .of_match_table =3D xsdirxss_of_id_table, > + }, > + .probe =3D xsdirxss_probe, > + .remove =3D xsdirxss_remove, > +}; > + > +module_platform_driver(xsdirxss_driver); > + > +MODULE_AUTHOR("Vishal Sagar "); > +MODULE_DESCRIPTION("Xilinx SDI Rx Subsystem Driver"); > +MODULE_LICENSE("GPL v2"); > diff --git a/include/uapi/linux/v4l2-controls.h b/include/uapi/linux/v4= l2-controls.h > index 62271418c1be..9526a6acc6f4 100644 > --- a/include/uapi/linux/v4l2-controls.h > +++ b/include/uapi/linux/v4l2-controls.h > @@ -198,6 +198,12 @@ enum v4l2_colorfx { > */ > #define V4L2_CID_USER_ATMEL_ISC_BASE (V4L2_CID_USER_BASE + 0x10c0) > =20 > +/* > + * The base for the Xilinx SDI Rx driver controls. > + * We reserve 16 controls for this driver. > + */ > +#define V4L2_CID_USER_XILINX_SDIRX_BASE (V4L2_CID_USER_BASE + 0x10e0) > + > /* MPEG-class control IDs */ > /* The MPEG controls are applicable to all codec controls > * and the 'MPEG' part of the define is historical */ > diff --git a/include/uapi/linux/xilinx-sdirxss.h b/include/uapi/linux/x= ilinx-sdirxss.h > new file mode 100644 > index 000000000000..1bcbf5852b22 > --- /dev/null > +++ b/include/uapi/linux/xilinx-sdirxss.h > @@ -0,0 +1,283 @@ > +/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ > +/* > + * Xilinx SDI Rx Subsystem mode, event, custom timings and > + * flag definitions. > + * > + * Copyright (C) 2019 - 2020 Xilinx, Inc. > + * > + * Contacts: Vishal Sagar > + */ > + > +#ifndef __UAPI_XILINX_SDIRXSS_H__ > +#define __UAPI_XILINX_SDIRXSS_H__ > + > +#include > +#include > +#include > +#include > + > +/* > + * Events > + * > + * V4L2_EVENT_XILINX_SDIRX_UND_OVR_FLOW: Video in to AXI4 Stream core > + * under/overflowed during a resolution or frame rate change. > + */ > +#define V4L2_EVENT_XILINX_SDIRX_CLASS (V4L2_EVENT_PRIVATE_START |= 0x200) > +#define V4L2_EVENT_XILINX_SDIRX_UND_OVR_FLOW \ > + (V4L2_EVENT_XILINX_SDIRX_CLASS | 0x1) > + > +#define XILINX_SDIRX_UNDERFLOW_EVENT BIT(1) > +#define XILINX_SDIRX_OVERFLOW_EVENT BIT(2) > +/* > + * This enum is used to prepare the bitmask of modes to be detected > + */ > +enum { > + XSDIRX_MODE_SD_OFFSET =3D 0, > + XSDIRX_MODE_HD_OFFSET, > + XSDIRX_MODE_3GA_OFFSET, > + XSDIRX_MODE_3GB_OFFSET, > + XSDIRX_MODE_6G_OFFSET, > + XSDIRX_MODE_12GI_OFFSET, > + XSDIRX_MODE_12GF_OFFSET, > + XSDIRX_MODE_NUM_SUPPORTED, > +}; > + > +#define XSDIRX_DETECT_ALL_MODES (BIT(XSDIRX_MODE_SD_OFFSET) | \ > + BIT(XSDIRX_MODE_HD_OFFSET) | \ > + BIT(XSDIRX_MODE_3GA_OFFSET) | \ > + BIT(XSDIRX_MODE_3GB_OFFSET) | \ > + BIT(XSDIRX_MODE_6G_OFFSET) | \ > + BIT(XSDIRX_MODE_12GI_OFFSET) | \ > + BIT(XSDIRX_MODE_12GF_OFFSET)) > + > +/* > + * EDH - Error Detection and Handling. > + * In the SD-SDI mode, the UHD-SDI core fully supports RP 165. > + * The bitmask is named as XSDIRX_EDH_ERRCNT_XX_YY_ERR except > + * for packet checksum error. > + * > + * XX - EDH Error Types > + * ANC - Ancillary Data Packet Errors > + * FF - Full Field Errors > + * AP - Active Portion Errors > + * > + * YY - Error Flags > + * EDH - error detected here > + * EDA - error Detected already > + * IDH - internal error detected here > + * IDA - internal error detected already > + * UES - unknown error status > + * > + * Refer to Sec 4.3 Error Flags in RP 165-1994 for details > + */ > + > +#define XSDIRX_EDH_ERRCNT_ANC_EDH_ERR BIT(0) > +#define XSDIRX_EDH_ERRCNT_ANC_EDA_ERR BIT(1) > +#define XSDIRX_EDH_ERRCNT_ANC_IDH_ERR BIT(2) > +#define XSDIRX_EDH_ERRCNT_ANC_IDA_ERR BIT(3) > +#define XSDIRX_EDH_ERRCNT_ANC_UES_ERR BIT(4) > +#define XSDIRX_EDH_ERRCNT_FF_EDH_ERR BIT(5) > +#define XSDIRX_EDH_ERRCNT_FF_EDA_ERR BIT(6) > +#define XSDIRX_EDH_ERRCNT_FF_IDH_ERR BIT(7) > +#define XSDIRX_EDH_ERRCNT_FF_IDA_ERR BIT(8) > +#define XSDIRX_EDH_ERRCNT_FF_UES_ERR BIT(9) > +#define XSDIRX_EDH_ERRCNT_AP_EDH_ERR BIT(10) > +#define XSDIRX_EDH_ERRCNT_AP_EDA_ERR BIT(11) > +#define XSDIRX_EDH_ERRCNT_AP_IDH_ERR BIT(12) > +#define XSDIRX_EDH_ERRCNT_AP_IDA_ERR BIT(13) > +#define XSDIRX_EDH_ERRCNT_AP_UES_ERR BIT(14) > +#define XSDIRX_EDH_ERRCNT_PKT_CHKSUM_ERR BIT(15) > + > +#define XSDIRX_EDH_ALLERR_MASK 0xFFFF Nit, lowercase for hex values. Thanks! -hyun > + > +/* > + * V4L2 Controls - We reserved 16 controls for this driver. > + * > + * The V4L2_CID_XILINX_SDIRX_EDH_* controls are present only if > + * EDH is enabled. > + * The controls which can be set should only be set before enabling > + * streaming. The controls which can be got should be called while > + * streaming to get correct values. > + * The V4L2_CID_XILINX_SDIRX_MODE_DETECT can be called when query dv t= iming > + * returns a valid timing. > + */ > + > +/* > + * Framer Control to enable or disable the framer. When this is set, t= he framer > + * automatically readjusts the output word alignment to match the alig= nment of > + * each timing reference signal(TRS). Normally this should be set. But= user may > + * control this input to implement TRS filtering to prevent a signal m= isaligned > + * TRS from causing erroneous alignment changes. > + * Refer to PG205 rx_frame_en for more details. > + */ > +#define V4L2_CID_XILINX_SDIRX_FRAMER (V4L2_CID_USER_XILINX_SDIRX_BASE= + 1) > + > +/* > + * Video Lock Window Control to set the video lock window value > + * This is the amount of time the mode and transport stream need > + * to be locked before a video lock interrupt occurs. > + */ > +#define V4L2_CID_XILINX_SDIRX_VIDLOCK_WINDOW (V4L2_CID_USER_XILINX_SDI= RX_BASE + 2) > + > +/* > + * EDH Error Mask Control to enable EDH error count > + * This control takes in the bitmask of XSDIRX_EDH_ERRCNT_*_ERR to ena= ble counting > + * such errors. > + */ > +#define V4L2_CID_XILINX_SDIRX_EDH_ERROR_SOURCES (V4L2_CID_USER_XILINX_= SDIRX_BASE + 3) > + > +/* > + * Mode search Control to pass the bit mask of modes to detect. > + * If only 1 bit is set, the driver programs IP to be in fixed mode el= se > + * in multi detection mode. > + * > + * Set this when not streaming. > + * > + * bit 0 set to detect SD mode, > + * bit 1 set to detect HD mode, > + * bit 2 set to detect 3GA mode, > + * bit 3 set to detect 3GB mode, > + * bit 4 set to detect 6G mode, > + * bit 5 set to detect 12G integer frame rate mode, > + * bit 6 set to detect 12G fractional frame rate mode, > + */ > +#define V4L2_CID_XILINX_SDIRX_SEARCH_MODES (V4L2_CID_USER_XILINX_SDIRX= _BASE + 4) > + > +/* > + * Get Detected SDI Mode control (read only) > + * > + * Control Value - Mode detected > + * 0 - SD > + * 1 - HD > + * 2 - 3GA > + * 3 - 3GB > + * 4 - 6G > + * 5 - 12G integer frame rate > + * 6 - 12G fractional frame rate > + */ > +#define V4L2_CID_XILINX_SDIRX_MODE_DETECT (V4L2_CID_USER_XILINX_SDIRX_= BASE + 5) > + > +/* Get number of CRC errors status control > + * > + * When a CRC is detected on a line, the CRC error signal of that data= stream > + * becomes asserted starting a few clock cycles after the last CRC wor= d is > + * output on the data stream ports following the EAV that ends the lin= e > + * containing the error. The CRC signal remains asserted for one line = time. > + * > + * The LSB 16 bits of value returned by thsi control represent the err= or > + * signal on each of 16 data streams. The MSB 16 bits contains the acc= umulated > + * error count. > + * > + * Refer to PG205 rx_crc_err_dsX (X =3D 1 to 16) description for detai= ls. > + */ > +#define V4L2_CID_XILINX_SDIRX_CRC (V4L2_CID_USER_XILINX_SDIRX_BASE + = 6) > + > +/* > + * Get EDH error count control > + * > + * Reading this control will give the number of EDH errors occurred ba= sed > + * on the bitmask passed in V4L2_CID_XILINX_SDIRX_EDH_ERROR_SOURCES. > + * > + * It increments once per field when any of the error conditions enabl= ed by > + * the RX_EDH_ERRCNT_EN register bit(s) occur during that field. > + * > + * Refer to PG205 rx_edh_errcnt > + */ > +#define V4L2_CID_XILINX_SDIRX_EDH_ERRCNT (V4L2_CID_USER_XILINX_SDIRX_B= ASE + 7) > + > +/* > + * Get EDH status control > + * > + * This control returns the RX_EDH_STS register contents. > + * Refer to PG290 register space section for more details. > + */ > +#define V4L2_CID_XILINX_SDIRX_EDH_STATUS (V4L2_CID_USER_XILINX_SDIRX_B= ASE + 8) > + > +/* Get Transport Interlaced status whether it is interlaced or not */ > +#define V4L2_CID_XILINX_SDIRX_TS_IS_INTERLACED (V4L2_CID_USER_XILINX_S= DIRX_BASE + 9) > + > +/* > + * Xilinx DV timings > + * TODO - Remove these once they are in v4l2-dv-timings.h > + */ > +#define XLNX_V4L2_DV_BT_2048X1080P24 { \ > + .type =3D V4L2_DV_BT_656_1120, \ > + V4L2_INIT_BT_TIMINGS(2048, 1080, 0, \ > + V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ > + 74250000, 510, 44, 148, 4, 5, 36, 0, 0, 0, \ > + V4L2_DV_BT_STD_SDI) \ > +} > + > +#define XLNX_V4L2_DV_BT_2048X1080P25 { \ > + .type =3D V4L2_DV_BT_656_1120, \ > + V4L2_INIT_BT_TIMINGS(2048, 1080, 0, \ > + V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ > + 74250000, 400, 44, 148, 4, 5, 36, 0, 0, 0, \ > + V4L2_DV_BT_STD_SDI) \ > +} > + > +#define XLNX_V4L2_DV_BT_2048X1080P30 { \ > + .type =3D V4L2_DV_BT_656_1120, \ > + V4L2_INIT_BT_TIMINGS(2048, 1080, 0, \ > + V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ > + 74250000, 66, 20, 66, 4, 5, 36, 0, 0, 0, \ > + V4L2_DV_BT_STD_SDI) \ > +} > + > +#define XLNX_V4L2_DV_BT_2048X1080I48 { \ > + .type =3D V4L2_DV_BT_656_1120, \ > + V4L2_INIT_BT_TIMINGS(2048, 1080, 1, \ > + V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ > + 74250000, 329, 44, 329, 2, 5, 15, 3, 5, 15, \ > + V4L2_DV_BT_STD_SDI) \ > +} > + > +#define XLNX_V4L2_DV_BT_2048X1080I50 { \ > + .type =3D V4L2_DV_BT_656_1120, \ > + V4L2_INIT_BT_TIMINGS(2048, 1080, 1, \ > + V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ > + 74250000, 274, 44, 274, 2, 5, 15, 3, 5, 15, \ > + V4L2_DV_BT_STD_SDI) \ > +} > + > +#define XLNX_V4L2_DV_BT_2048X1080I60 { \ > + .type =3D V4L2_DV_BT_656_1120, \ > + V4L2_INIT_BT_TIMINGS(2048, 1080, 1, \ > + V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ > + 74250000, 66, 20, 66, 2, 5, 15, 3, 5, 15, \ > + V4L2_DV_BT_STD_SDI) \ > +} > + > +#define XLNX_V4L2_DV_BT_2048X1080P48 { \ > + .type =3D V4L2_DV_BT_656_1120, \ > + V4L2_INIT_BT_TIMINGS(2048, 1080, 0, \ > + V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ > + 148500000, 510, 44, 148, 4, 5, 36, 0, 0, 0, \ > + V4L2_DV_BT_STD_SDI) \ > +} > + > +#define XLNX_V4L2_DV_BT_2048X1080P50 { \ > + .type =3D V4L2_DV_BT_656_1120, \ > + V4L2_INIT_BT_TIMINGS(2048, 1080, 0, \ > + V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ > + 148500000, 400, 44, 148, 4, 5, 36, 0, 0, 0, \ > + V4L2_DV_BT_STD_SDI) \ > +} > + > +#define XLNX_V4L2_DV_BT_2048X1080P60 { \ > + .type =3D V4L2_DV_BT_656_1120, \ > + V4L2_INIT_BT_TIMINGS(2048, 1080, 0, \ > + V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ > + 148500000, 88, 44, 20, 4, 5, 36, 0, 0, 0, \ > + V4L2_DV_BT_STD_SDI) \ > +} > + > +#define XLNX_V4L2_DV_BT_1920X1080I48 { \ > + .type =3D V4L2_DV_BT_656_1120, \ > + V4L2_INIT_BT_TIMINGS(1920, 1080, 1, \ > + V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ > + 148500000, 371, 88, 371, 2, 5, 15, 3, 5, 15, \ > + V4L2_DV_BT_STD_SDI) \ > +} > + > +#endif /* __UAPI_XILINX_SDIRXSS_H__ */ > --=20 > 2.21.0 >=20 >=20