diff for duplicates of <20200716125945.GD535268@ulmo> diff --git a/a/1.txt b/N1/1.txt index 864812b..01a55e3 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -1,5 +1,5 @@ On Tue, Jun 23, 2020 at 04:55:27PM +0200, Thierry Reding wrote: -> From: Thierry Reding <treding@nvidia.com> +> From: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> > > The XUSB pad controller, which provides access to various USB, PCI and > SATA pads (or PHYs), needs to bring up the PLLs associated with these @@ -10,7 +10,7 @@ On Tue, Jun 23, 2020 at 04:55:27PM +0200, Thierry Reding wrote: > not need direct access to them. Instead it will only use the configured > pads provided by the XUSB pad controller. > -> Signed-off-by: Thierry Reding <treding@nvidia.com> +> Signed-off-by: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> > --- > Hi Rob, > diff --git a/a/content_digest b/N1/content_digest index 2b0808a..f799e1a 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,17 +1,18 @@ "ref\020200623145528.1658337-1-thierry.reding@gmail.com\0" - "From\0Thierry Reding <thierry.reding@gmail.com>\0" + "ref\020200623145528.1658337-1-thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org\0" + "From\0Thierry Reding <thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>\0" "Subject\0Re: [PATCH v2 1/2] dt-bindings: pci: tegra: Remove PLL power supplies\0" "Date\0Thu, 16 Jul 2020 14:59:45 +0200\0" - "To\0Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>" - Bjorn Helgaas <bhelgaas@google.com> - " Rob Herring <robh+dt@kernel.org>\0" - "Cc\0Jon Hunter <jonathanh@nvidia.com>" - linux-pci@vger.kernel.org - " linux-tegra@vger.kernel.org\0" + "To\0Lorenzo Pieralisi <lorenzo.pieralisi-5wv7dgnIgG8@public.gmane.org>" + Bjorn Helgaas <bhelgaas-hpIqsD4AKlfQT0dZR+AlfA@public.gmane.org> + " Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>\0" + "Cc\0Jon Hunter <jonathanh-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>" + linux-pci-u79uwXL29TY76Z2rM5mHXA@public.gmane.org + " linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org\0" "\01:1\0" "b\0" "On Tue, Jun 23, 2020 at 04:55:27PM +0200, Thierry Reding wrote:\n" - "> From: Thierry Reding <treding@nvidia.com>\n" + "> From: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>\n" "> \n" "> The XUSB pad controller, which provides access to various USB, PCI and\n" "> SATA pads (or PHYs), needs to bring up the PLLs associated with these\n" @@ -22,7 +23,7 @@ "> not need direct access to them. Instead it will only use the configured\n" "> pads provided by the XUSB pad controller.\n" "> \n" - "> Signed-off-by: Thierry Reding <treding@nvidia.com>\n" + "> Signed-off-by: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>\n" "> ---\n" "> Hi Rob,\n" "> \n" @@ -98,4 +99,4 @@ "=j1RD\n" "-----END PGP SIGNATURE-----\n" -b88e33c130832093417c7001a9cc841d620daeca462d2c67f51c3b1b50e34cbc +b3ef017c57d3220e65d69ac72d5b27442ba5e6e69a8e1e2f72ddffbff1324cd7
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