From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-3.8 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7348EC433E3 for ; Thu, 23 Jul 2020 11:30:47 +0000 (UTC) Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 42EAE20709 for ; Thu, 23 Jul 2020 11:30:47 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=citrix.com header.i=@citrix.com header.b="CrH+/rCG" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 42EAE20709 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=citrix.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1jyZQp-0005dB-5x; Thu, 23 Jul 2020 11:30:35 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57] helo=us1-amaz-eas2.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1jyZQo-0005d3-2B for xen-devel@lists.xenproject.org; Thu, 23 Jul 2020 11:30:34 +0000 X-Inumbo-ID: eb242685-ccd7-11ea-a281-12813bfff9fa Received: from esa4.hc3370-68.iphmx.com (unknown [216.71.155.144]) by us1-amaz-eas2.inumbo.com (Halon) with ESMTPS id eb242685-ccd7-11ea-a281-12813bfff9fa; Thu, 23 Jul 2020 11:30:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=citrix.com; s=securemail; t=1595503832; h=date:from:to:cc:subject:message-id:references: mime-version:content-transfer-encoding:in-reply-to; bh=AEGXJnYUL36sPmyfPejacPpdAzMnNyNFpcFfg/8Dcwc=; b=CrH+/rCGPfvvhoez4tPgWrRACfDX+t1qlVAwvPc0PuJ4DHBqZUJFmVBZ 5b8IDALzoIkvg6OGVBV1btIdFZTONE7BAoNq4B3x/bBUUoUORTYX8cADd n5XtPaFA8PU3Wz9a8CzxW6tNb80uR0T5OHar+UShBO/xLJTq344S5Q2Gi M=; Authentication-Results: esa4.hc3370-68.iphmx.com; dkim=none (message not signed) header.i=none IronPort-SDR: WNh0sKpjmcuyb8eJEuv9zo7IX2gwMJjXI2cuvfu94C5HwfUCbokOJVcr/MO2vueW5qKaUlFLQ8 xmgWrrEOKBTRAHbQ27aqdn5sSV7Lx0JfbtfRcb3i3drfcGRer67UJ933t98A3V19nH4CNbBV7f O9+wUmuD4E0Kpx2shfYKJ6vNJb9QB6/uotOc87vUQIYmAU3dESqSZSGE/PCZkZAZB+v6fFHpua zKeCSFpkh1R3UQv1g9q9p8BCyXvAEAsbvZKkj2VIZdcBfcWJ9Mwvn1HDhjezTnll4ZgEgbB08k FVg= X-SBRS: 2.7 X-MesageID: 23889623 X-Ironport-Server: esa4.hc3370-68.iphmx.com X-Remote-IP: 162.221.158.21 X-Policy: $RELAYED X-IronPort-AV: E=Sophos;i="5.75,386,1589256000"; d="scan'208";a="23889623" Date: Thu, 23 Jul 2020 13:30:25 +0200 From: Roger Pau =?utf-8?B?TW9ubsOp?= To: Andrew Cooper Subject: Re: [PATCH] x86/vmce: Dispatch vmce_{rd,wr}msr() from guest_{rd,wr}msr() Message-ID: <20200723113025.GC7191@Air-de-Roger> References: <20200722101809.8389-1-andrew.cooper3@citrix.com> <20200723100727.GA7191@Air-de-Roger> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: X-ClientProxiedBy: AMSPEX02CAS02.citrite.net (10.69.22.113) To AMSPEX02CL02.citrite.net (10.69.22.126) X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Xen-devel , Wei Liu , Jan Beulich Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" On Thu, Jul 23, 2020 at 12:00:53PM +0100, Andrew Cooper wrote: > On 23/07/2020 11:07, Roger Pau Monné wrote: > > On Wed, Jul 22, 2020 at 11:18:09AM +0100, Andrew Cooper wrote: > >> + case MSR_IA32_MCG_CAP ... MSR_IA32_MCG_CTL: /* 0x179 -> 0x17b */ > >> + case MSR_IA32_MCx_CTL2(0) ... MSR_IA32_MCx_CTL2(31): /* 0x280 -> 0x29f */ > >> + case MSR_IA32_MCx_CTL(0) ... MSR_IA32_MCx_MISC(31): /* 0x400 -> 0x47f */ > > Where do you get the ranges from 0 to 31? It seems like the count > > field in the CAP register is 8 bits, which could allow for up to 256 > > banks? > > > > I'm quite sure this would then overlap with other MSRs? > > Irritatingly, nothing I can find actually states an upper architectural > limit. > > SDM Vol4, Table 2-2 which enumerates the Architectural MSRs. > > 0x280 thru 0x29f are explicitly reserved MCx_CTL2, which is a limit of > 32 banks.  There are gaps after this in the architectural table, but > IceLake has PRMRR_BASE_0 at 0x2a0. > > The main bank of MCx_{CTL,STATUS,ADDR,MISC} start at 0x400 and are > listed in the table up to 0x473, which is a limit of 29 banks.  The > Model specific table for SandyBridge fills in the remaining 3 banks up > to MSR 0x47f, which is the previous limit of 32 banks.  (These MSRs have > package scope rather than core/thread scope, but they are still > enumerated architecturally so I'm not sure why they are in the model > specific tables.) > > More importantly however, the VMX MSR range starts at 0x480, immediately > above bank 31, which puts an architectural hard limit on the number of > banks. Yes, realized about the VMX MSRs starting at 0x480, which limits the number of banks. Maybe a small comment about the fact that albeit the count in the CAP register could go up to 256 32 is the actual limit due to how MSRs are arranged? Note there's also GUEST_MC_BANK_NUM which is the actual implementation limit in Xen AFAICT, maybe using it here would be clearer? (and limit the ranges forwarded to vmce_rdmsr) Thanks, Roger.