Re: BUG: omap5: v5.8-rc7 boot fails

[Tony Lindgren <tony@atomide.com>]

* Tony Lindgren <tony@atomide.com> [200728 08:23]:
> * H. Nikolaus Schaller <hns@goldelico.com> [200727 20:51]:
> > Hi Tony,
> > after trying v5.8-rc7 the Pyra boot hangs after ca. 3 seconds
> > (a little random what the last log line is).
> > 
> > I could bisect it to:
> > 
> > 6cfcd5563b4fadbf49ba8fa481978e5e86d30322 is the first bad commit
> > commit 6cfcd5563b4fadbf49ba8fa481978e5e86d30322
> > Author: Tony Lindgren <tony@atomide.com>
> > Date:   Mon Jul 13 09:26:01 2020 -0700
> > 
> >     clocksource/drivers/timer-ti-dm: Fix suspend and resume for am3 and am4
> > 
> > And a git revert makes it boot again.
> > 
> > I haven't had time to do more tests (e.g. with omap3/4 or on omap5uevm).
> 
> Oops sorry about that, I'll take a look.

This fixes booting for me, but I still need to check if we also
need to enable before the reset. And then this needs to be tested
on all the related SoCs again.

Regards,

Tony

8< ------------------
diff --git a/drivers/clocksource/timer-ti-dm-systimer.c b/drivers/clocksource/timer-ti-dm-systimer.c
--- a/drivers/clocksource/timer-ti-dm-systimer.c
+++ b/drivers/clocksource/timer-ti-dm-systimer.c
@@ -409,8 +409,8 @@ static int __init dmtimer_systimer_setup(struct device_node *np,
 	t->wakeup = regbase + _OMAP_TIMER_WAKEUP_EN_OFFSET;
 	t->ifctrl = regbase + _OMAP_TIMER_IF_CTRL_OFFSET;
 
-	dmtimer_systimer_enable(t);
 	dmtimer_systimer_reset(t);
+	dmtimer_systimer_enable(t);
 	pr_debug("dmtimer rev %08x sysc %08x\n", readl_relaxed(t->base),
 		 readl_relaxed(t->base + t->sysc));