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[84.3.50.134]) by smtp.gmail.com with ESMTPSA id bc10sm15968725edb.5.2020.08.03.05.37.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Aug 2020 05:37:31 -0700 (PDT) Date: Mon, 3 Aug 2020 14:37:29 +0200 From: Ingo Molnar To: Linus Torvalds Cc: linux-kernel@vger.kernel.org, Peter Zijlstra , Arnaldo Carvalho de Melo , Thomas Gleixner , Andrew Morton Subject: [GIT PULL] perf events updates for v5.9 Message-ID: <20200803123729.GA567306@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Linus, Please pull the latest perf/core git tree from: git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git perf-core-2020-08-03 # HEAD: d903b6d029d66e6478562d75ea18d89098f7b7e8 perf/x86/rapl: Add Hygon Fam18h RAPL support - HW support updates: - Add uncore support for Intel Comet Lake - Add RAPL support for Hygon Fam18h - Add Intel "IIO stack to PMON mapping" support on Skylake-SP CPUs, which enumerates per device performance counters via sysfs and enables the perf stat --iiostat functionality - Add support for Intel "Architectural LBRs", which generalized the model specific LBR hardware tracing feature into a model-independent, architected performance monitoring feature. Usage is mostly seamless to tooling, as the pre-existing LBR features are kept, but there's a couple of advantages under the hood, such as faster context-switching, faster LBR reads, cleaner exposure of LBR features to guest kernels, etc. ( Since architectural LBRs are supported via XSAVE, there's related changes to the x86 FPU code as well. ) - ftrace/perf updates: Add support to add a text poke event to record changes to kernel text (i.e. self-modifying code) in order to support tracers like Intel PT decoding through jump labels, kprobes and ftrace trampolines. - Misc cleanups, smaller fixes. Thanks, Ingo ------------------> Adrian Hunter (8): perf: Add perf text poke event perf/x86: Add support for perf text poke event for text_poke_bp_batch() callers kprobes: Add symbols for kprobe insn pages kprobes: Add perf ksymbol events for kprobe insn pages perf/x86: Add perf text poke events for kprobes ftrace: Add symbols for ftrace trampolines ftrace: Add perf ksymbol events for ftrace trampolines ftrace: Add perf text poke events for ftrace trampolines Hu Haowen (1): x86/perf: Fix a typo Kan Liang (27): perf/x86/intel/uncore: Add Comet Lake support perf/x86/intel/uncore: Fix oops when counting IMC uncore events on some TGL perf/x86/intel/uncore: Record the size of mapped area perf/x86/intel/uncore: Validate MMIO address before accessing x86/cpufeatures: Add Architectural LBRs feature bit perf/x86/intel/lbr: Add a function pointer for LBR reset perf/x86/intel/lbr: Add a function pointer for LBR read perf/x86/intel/lbr: Add the function pointers for LBR save and restore perf/x86/intel/lbr: Factor out a new struct for generic optimization perf/x86/intel/lbr: Use dynamic data structure for task_ctx x86/msr-index: Add bunch of MSRs for Arch LBR perf/x86: Expose CPUID enumeration bits for arch LBR perf/x86/intel/lbr: Support LBR_CTL perf/x86/intel/lbr: Unify the stored format of LBR information perf/x86/intel/lbr: Mark the {rd,wr}lbr_{to,from} wrappers __always_inline perf/x86/intel/lbr: Factor out rdlbr_all() and wrlbr_all() perf/x86/intel/lbr: Factor out intel_pmu_store_lbr perf/x86/intel/lbr: Support Architectural LBR perf/core: Factor out functions to allocate/free the task_ctx_data perf/core: Use kmem_cache to allocate the PMU specific data perf/x86/intel/lbr: Create kmem_cache for the LBR context data perf/x86: Remove task_ctx_size x86/fpu: Use proper mask to replace full instruction mask x86/fpu/xstate: Support dynamic supervisor feature for LBR x86/fpu/xstate: Add helpers for LBR dynamic supervisor feature perf/x86/intel/lbr: Support XSAVES/XRSTORS for LBR context switch perf/x86/intel/lbr: Support XSAVES for arch LBR read Like Xu (4): perf/x86/core: Refactor hw->idx checks and cleanup perf/x86/lbr: Add interface to get LBR information perf/x86: Add constraint to create guest LBR event without hw counter perf/x86: Keep LBR records unchanged in host context for guest usage Masami Hiramatsu (1): kprobes: Remove unnecessary module_mutex locking from kprobe_optimizer() Pu Wen (1): perf/x86/rapl: Add Hygon Fam18h RAPL support Randy Dunlap (1): perf: : drop a duplicated word Roman Sudarikov (3): perf/x86/intel/uncore: Expose an Uncore unit to PMON mapping perf/x86/intel/uncore: Wrap the max dies calculation into an accessor perf/x86/intel/uncore: Expose an Uncore unit to IIO PMON mapping Wei Wang (1): perf/x86: Fix variable types for LBR registers Documentation/ABI/testing/sysfs-devices-mapping | 33 ++ arch/x86/events/core.c | 28 +- arch/x86/events/intel/core.c | 127 ++-- arch/x86/events/intel/ds.c | 6 +- arch/x86/events/intel/lbr.c | 733 ++++++++++++++++++++---- arch/x86/events/intel/uncore.c | 26 +- arch/x86/events/intel/uncore.h | 37 ++ arch/x86/events/intel/uncore_snb.c | 80 ++- arch/x86/events/intel/uncore_snbep.c | 208 ++++++- arch/x86/events/perf_event.h | 125 +++- arch/x86/events/rapl.c | 3 +- arch/x86/events/zhaoxin/core.c | 2 +- arch/x86/include/asm/cpufeatures.h | 1 + arch/x86/include/asm/fpu/internal.h | 47 +- arch/x86/include/asm/fpu/types.h | 27 + arch/x86/include/asm/fpu/xstate.h | 36 ++ arch/x86/include/asm/kprobes.h | 2 + arch/x86/include/asm/msr-index.h | 16 + arch/x86/include/asm/perf_event.h | 82 ++- arch/x86/kernel/alternative.c | 37 +- arch/x86/kernel/fpu/core.c | 39 ++ arch/x86/kernel/fpu/xstate.c | 89 ++- arch/x86/kernel/kprobes/core.c | 15 +- arch/x86/kernel/kprobes/opt.c | 38 +- include/linux/ftrace.h | 12 +- include/linux/kprobes.h | 15 + include/linux/perf_event.h | 15 +- include/uapi/linux/perf_event.h | 26 +- kernel/events/core.c | 115 +++- kernel/kallsyms.c | 42 +- kernel/kprobes.c | 60 +- kernel/trace/ftrace.c | 101 +++- 32 files changed, 1943 insertions(+), 280 deletions(-) create mode 100644 Documentation/ABI/testing/sysfs-devices-mapping