From mboxrd@z Thu Jan 1 00:00:00 1970 Content-Type: multipart/mixed; boundary="===============5245037530806427287==" MIME-Version: 1.0 From: kernel test robot To: kbuild-all@lists.01.org Subject: [RFC PATCH intel-linux-intel-lts] drm: ddr_dev can be static Date: Wed, 05 Aug 2020 21:43:34 +0800 Message-ID: <20200805134334.GA14965@5d64e4070d3f> In-Reply-To: <202008052129.Lp5ZYazo%lkp@intel.com> List-Id: --===============5245037530806427287== Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Fixes: b8b4b73e4f7b ("drm: Add Keembay media codec driver") Signed-off-by: kernel test robot --- hantro.c | 8 ++++---- hantro_fence.c | 2 +- hantrodec.c | 12 ++++++------ hx280enc.c | 6 +++--- 4 files changed, 14 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/hantro_driver/hantro.c b/drivers/gpu/drm/hantr= o_driver/hantro.c index 5768b81d6d219..795981abc7c78 100644 --- a/drivers/gpu/drm/hantro_driver/hantro.c +++ b/drivers/gpu/drm/hantro_driver/hantro.c @@ -79,7 +79,7 @@ struct hantro_device_handle hantro_dev; = /* struct used for dynamic ddr allocations */ struct hantro_mem ddr1; -struct device *ddr_dev; +static struct device *ddr_dev; = #if KERNEL_VERSION(4, 13, 0) > LINUX_VERSION_CODE void debug_dma_alloc_coherent( @@ -1506,7 +1506,7 @@ static const struct file_operations hantro_fops =3D { .compat_ioctl =3D drm_compat_ioctl, }; = -void hantro_gem_vm_close(struct vm_area_struct *vma) +static void hantro_gem_vm_close(struct vm_area_struct *vma) { struct drm_gem_hantro_object *obj =3D (struct drm_gem_hantro_object *)vma->vm_private_data; @@ -1949,7 +1949,7 @@ static const struct platform_device_info hantro_platf= orm_info =3D { #if KERNEL_VERSION(4, 10, 0) > LINUX_VERSION_CODE static int hantro_major =3D 1; /* dynamic */ #endif -void __exit hantro_cleanup(void) +static void __exit hantro_cleanup(void) { #if USE_HW =3D=3D 1 /*hw cleanup*/ device_unregister(ddr1.dev); @@ -1971,7 +1971,7 @@ void __exit hantro_cleanup(void) platform_driver_unregister(&hantro_drm_platform_driver); } = -int __init hantro_init(void) +static int __init hantro_init(void) { int result; = diff --git a/drivers/gpu/drm/hantro_driver/hantro_fence.c b/drivers/gpu/drm= /hantro_driver/hantro_fence.c index 3244a63c15a2b..f80a32c440e85 100644 --- a/drivers/gpu/drm/hantro_driver/hantro_fence.c +++ b/drivers/gpu/drm/hantro_driver/hantro_fence.c @@ -116,7 +116,7 @@ int init_hantro_resv( return 0; } = -int hantro_waitfence(hantro_fence_t *pfence) +static int hantro_waitfence(hantro_fence_t *pfence) { if (test_bit(HANTRO_FENCE_FLAG_SIGNAL_BIT, &pfence->flags)) return 0; diff --git a/drivers/gpu/drm/hantro_driver/hantrodec.c b/drivers/gpu/drm/ha= ntro_driver/hantrodec.c index 100a34f126289..6d9472cf5929b 100644 --- a/drivers/gpu/drm/hantro_driver/hantrodec.c +++ b/drivers/gpu/drm/hantro_driver/hantrodec.c @@ -143,7 +143,7 @@ static const int DecHwId[] =3D { 0x8001 /* VDEC */ }; = -ulong multicorebase[HXDEC_MAX_CORES] =3D { +static ulong multicorebase[HXDEC_MAX_CORES] =3D { SOCLE_LOGIC_0_BASE, SOCLE_LOGIC_1_BASE }; @@ -165,7 +165,7 @@ static u8 *page_lut_regs_read; /* Because one core may contain multi-pipeline, * so multicore base may be changed */ -unsigned long multicorebase_actual[HXDEC_MAX_CORES]; +static unsigned long multicorebase_actual[HXDEC_MAX_CORES]; int elements =3D 2; static struct device *parent_dev; static int hantro_dbg =3D -1; @@ -219,8 +219,8 @@ static void dump_regs(struct hantrodec_t *dev); static irqreturn_t hantrodec_isr(int irq, void *dev_id); = static u32 dec_regs[HXDEC_MAX_CORES][DEC_IO_SIZE_MAX / 4]; -struct semaphore dec_core_sem; -struct semaphore pp_core_sem; +static struct semaphore dec_core_sem; +static struct semaphore pp_core_sem; = static int dec_irq; static int pp_irq; @@ -715,7 +715,7 @@ static void ReleasePostProcessor(struct hantrodec_t *de= v, long core) up(&pp_core_sem); } = -long ReserveDecPp(struct hantrodec_t *dev, struct file *filp, unsigned lon= g format) +static long ReserveDecPp(struct hantrodec_t *dev, struct file *filp, unsig= ned long format) { /* reserve core 0, DEC+PP for pipeline */ unsigned long flags; @@ -1300,7 +1300,7 @@ long hantrodec_ioctl(struct file *filp, unsigned int = cmd, unsigned long arg) *Return type : int *------------------------------------------------------------------------= ---- */ -int hantrodec_release(struct file *filp) +static int hantrodec_release(struct file *filp) { int n; struct hantrodec_t *dev =3D &hantrodec_data; diff --git a/drivers/gpu/drm/hantro_driver/hx280enc.c b/drivers/gpu/drm/han= tro_driver/hx280enc.c index d7d86dddb1edc..1cba74bf92edf 100644 --- a/drivers/gpu/drm/hantro_driver/hx280enc.c +++ b/drivers/gpu/drm/hantro_driver/hx280enc.c @@ -42,7 +42,7 @@ #include #include = -struct semaphore enc_core_sem; +static struct semaphore enc_core_sem; static DECLARE_WAIT_QUEUE_HEAD(enc_hw_queue); static DEFINE_SPINLOCK(enc_owner_lock); static DECLARE_WAIT_QUEUE_HEAD(enc_wait_queue); @@ -89,13 +89,13 @@ static DECLARE_WAIT_QUEUE_HEAD(enc_wait_queue); = /*for all cores, the core info should be listed here for subsequent use*/ /*base_addr, iosize, irq, resource_shared*/ -CORE_CONFIG core_array[] =3D { +static CORE_CONFIG core_array[] =3D { {CORE_0_IO_ADDR, CORE_0_IO_SIZE, INT_PIN_CORE_0, RESOURCE_SHARED_INTER_CO= RES}, /* core_0, hevc and avc */ {CORE_1_IO_ADDR, CORE_1_IO_SIZE, INT_PIN_CORE_1, RESOURCE_SHARED_INTER_CO= RES} /* core_1, jpeg */ }; = /* Interrupt Pin Name */ -const char *core_irq_names[] =3D { +static const char *core_irq_names[] =3D { "irq_hantro_videoencoder", /* core_0, hevc and avc */ "irq_hantro_jpegencoder" /* core_1, jpeg */ }; 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