From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-11.2 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_SANE_2 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C6548C433DF for ; Thu, 20 Aug 2020 08:08:41 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 7706E21744 for ; Thu, 20 Aug 2020 08:08:41 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="AECSlEtX" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 7706E21744 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=bootlin.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-i3c-bounces+linux-i3c=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Message-ID: Subject:To:From:Date:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=J65H7M6kDhSllFCkLKzTY1TIHAwYD8zzW62VQ0Vy6eU=; b=AECSlEtX8PkMqPJQv2hXKAYcQ XCuouqVSRIxW07V69yINEQAW/492ftFISD08LrmiRM0Szc2nJScTfrpxE4IptfpQ7YKMtxy61RtMA A8au40/lRHCD5QO9I/pasXYzz9G/zqnqDPmtHgHyTWC8LU0p8tz9XWfhHliX+K1Z9CLp5nmif9Zq9 A2cRMWQQnzKUsFGtXX9CHsnLRG7vFtTQK4IRD6lL413Y6DRQqnY+fZ5cRuk+ve7VSfz8xaqycBo0i XKjIQDBg9XIX1bFCUCQY4Vo8wfI5XsahmBMoxwnegyNtcVuOU84pr6DjT8GxSxhH5cm6lKu2Vtkm6 qFVDgRRkQ==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1k8fcm-00061b-KH for linux-i3c@archiver.kernel.org; Thu, 20 Aug 2020 08:08:40 +0000 Received: from relay7-d.mail.gandi.net ([217.70.183.200]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1k8fch-0005qH-Mj for linux-i3c@lists.infradead.org; Thu, 20 Aug 2020 08:08:38 +0000 X-Originating-IP: 91.224.148.103 Received: from xps13 (unknown [91.224.148.103]) (Authenticated sender: miquel.raynal@bootlin.com) by relay7-d.mail.gandi.net (Postfix) with ESMTPSA id 5F85520006; Thu, 20 Aug 2020 08:08:30 +0000 (UTC) Date: Thu, 20 Aug 2020 10:08:29 +0200 From: Miquel Raynal To: Nicolas Pitre Subject: Re: [PATCH 2/2] i3c/master: add the mipi-i3c-hci driver Message-ID: <20200820100829.0e44200a@xps13> In-Reply-To: <20200814034854.460830-3-nico@fluxnic.net> References: <20200814034854.460830-1-nico@fluxnic.net> <20200814034854.460830-3-nico@fluxnic.net> Organization: Bootlin X-Mailer: Claws Mail 3.17.4 (GTK+ 2.24.32; x86_64-pc-linux-gnu) MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200820_040835_952982_1C984003 X-CRM114-Status: GOOD ( 39.42 ) X-BeenThere: linux-i3c@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Robert Gough , Laura Nixon , Rob Herring , Boris Brezillon , Matthew Schnoor , Nicolas Pitre , linux-i3c@lists.infradead.org Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Sender: "linux-i3c" Errors-To: linux-i3c-bounces+linux-i3c=archiver.kernel.org@lists.infradead.org SGkgTmljb2xhcywKCk5pY29sYXMgUGl0cmUgPG5pY29AZmx1eG5pYy5uZXQ+IHdyb3RlIG9uIFRo dSwgMTMgQXVnIDIwMjAgMjM6NDg6NTQKLTA0MDA6Cgo+IEZyb206IE5pY29sYXMgUGl0cmUgPG5w aXRyZUBiYXlsaWJyZS5jb20+Cj4gCj4gVGhpcyBhZGRzIGJhc2ljIHN1cHBvcnQgZm9yIGhhcmR3 YXJlIGltcGxlbWVudGluZyB0aGUgTUlQSSBJM0MgSENJCj4gc3BlY2lmaWNhdGlvbi4gVGhpcyBk cml2ZXIgaXMgY3VycmVudGx5IGxpbWl0ZWQgYnkgdGhlIGNhcGFiaWxpdGllcwo+IG9mIHRoZSBJ M0Mgc3Vic3lzdGVtLCBtZWFuaW5nIHRoaW5ncyBsaWtlIHNjaGVkdWxlZCBjb21tYW5kcywKPiBh dXRvLWNvbW1hbmRzIGFuZCBOQ00gYXJlIG5vdCB5ZXQgc3VwcG9ydGVkLgo+IAo+IFRoaXMgc3Vw cG9ydHMgdmVyc2lvbiAxLjAgb2YgdGhlIE1JUEkgSTNDIEhDSSBzcGVjLCBhcyB3ZWxsIGFzIHRo ZQo+IGltbWluZW50IHJlbGVhc2Ugb2YgdmVyc2lvbiAxLjEuIFN1cHBvcnQgZm9yIGRyYWZ0IHZl cnNpb24gMi4wIG9mIHRoZQo+IHNwZWMgaXMgYWxzbyBwYXJ0aWFsbHkgaW5jbHVkZWQgYnV0IGlz IGd1YXJhbnRlZWQgdG8gY2hhbmdlIGFzIHRoZSBzcGVjCj4gaXMgc3RpbGwgYSB3b3JrIGluIHBy b2dyZXNzLgo+IAo+IFRoaXMgaXMgYWxzbyBsaWdodGx5IHRlc3RlZCBhcyBhY3R1YWwgaGFyZHdh cmUgaXMgc3RpbGwgdmVyeSBzY2Fyc2UsCj4gZXZlbiBmb3IgSENJIHYxLjAuIEZ1cnRoZXIgY29u dHJpYnV0aW9ucyB0byB0aGlzIGRyaXZlciBhcmUgZXhwZWN0ZWQKPiBvbmNlIHZlbmRvciBpbXBs ZW1lbnRhdGlvbnMgYW5kIG5ldyBJM0MgZGV2aWNlcyBiZWNvbWUgYXZhaWxhYmxlLgoKTmljZSB3 b3JrISBJIGhvbm5lc3RseSBkbyBub3Qga25vdyBhIGxvdCBhYm91dCBIQ0lzIGFuZCBJIGJhc2lj YWxseQpoYWQgb25seSBtaW5vciBuaXRzIHRvIHBvaW50IG91dCwgc2VlIGJlbG93LgoKPiAKPiBT aWduZWQtb2ZmLWJ5OiBOaWNvbGFzIFBpdHJlIDxucGl0cmVAYmF5bGlicmUuY29tPgo+IC0tLQo+ ICBkcml2ZXJzL2kzYy9tYXN0ZXIvS2NvbmZpZyAgICAgICAgICAgICAgICAgfCAgMTMgKwo+ICBk cml2ZXJzL2kzYy9tYXN0ZXIvTWFrZWZpbGUgICAgICAgICAgICAgICAgfCAgIDEgKwo+ICBkcml2 ZXJzL2kzYy9tYXN0ZXIvbWlwaS1pM2MtaGNpL01ha2VmaWxlICAgfCAgIDkgKwo+ICBkcml2ZXJz L2kzYy9tYXN0ZXIvbWlwaS1pM2MtaGNpL2NtZC5oICAgICAgfCAxMDYgKysrCj4gIGRyaXZlcnMv aTNjL21hc3Rlci9taXBpLWkzYy1oY2kvY21kX3YxLmMgICB8IDM2MiArKysrKysrKwo+ICBkcml2 ZXJzL2kzYy9tYXN0ZXIvbWlwaS1pM2MtaGNpL2NtZF92Mi5jICAgfCAyODAgKysrKysrCj4gIGRy aXZlcnMvaTNjL21hc3Rlci9taXBpLWkzYy1oY2kvY29yZS5jICAgICB8IDgwMSArKysrKysrKysr KysrKysrKwo+ICBkcml2ZXJzL2kzYy9tYXN0ZXIvbWlwaS1pM2MtaGNpL2RhdC5oICAgICAgfCAg MjggKwo+ICBkcml2ZXJzL2kzYy9tYXN0ZXIvbWlwaS1pM2MtaGNpL2RhdF92MS5jICAgfCAxNzAg KysrKwo+ICBkcml2ZXJzL2kzYy9tYXN0ZXIvbWlwaS1pM2MtaGNpL2RjdC5oICAgICAgfCAgMTYg Kwo+ICBkcml2ZXJzL2kzYy9tYXN0ZXIvbWlwaS1pM2MtaGNpL2RjdF92MS5jICAgfCAgMzYgKwo+ ICBkcml2ZXJzL2kzYy9tYXN0ZXIvbWlwaS1pM2MtaGNpL2RlYnVnLmMgICAgfCAgNzkgKysKPiAg ZHJpdmVycy9pM2MvbWFzdGVyL21pcGktaTNjLWhjaS9kZWJ1Zy5oICAgIHwgIDE3ICsKPiAgZHJp dmVycy9pM2MvbWFzdGVyL21pcGktaTNjLWhjaS9kbWEuYyAgICAgIHwgNzY3ICsrKysrKysrKysr KysrKysKPiAgZHJpdmVycy9pM2MvbWFzdGVyL21pcGktaTNjLWhjaS9leHRfY2Fwcy5jIHwgMjQ5 ICsrKysrKwo+ICBkcml2ZXJzL2kzYy9tYXN0ZXIvbWlwaS1pM2MtaGNpL2V4dF9jYXBzLmggfCAg MTkgKwo+ICBkcml2ZXJzL2kzYy9tYXN0ZXIvbWlwaS1pM2MtaGNpL2hjaS5oICAgICAgfCAxNTAg KysrKwo+ICBkcml2ZXJzL2kzYy9tYXN0ZXIvbWlwaS1pM2MtaGNpL2liaS5oICAgICAgfCAgNDIg Kwo+ICBkcml2ZXJzL2kzYy9tYXN0ZXIvbWlwaS1pM2MtaGNpL3Bpby5jICAgICAgfCA5NjEgKysr KysrKysrKysrKysrKysrKysrCj4gIDE5IGZpbGVzIGNoYW5nZWQsIDQxMDYgaW5zZXJ0aW9ucygr KQo+ICBjcmVhdGUgbW9kZSAxMDA2NDQgZHJpdmVycy9pM2MvbWFzdGVyL21pcGktaTNjLWhjaS9N YWtlZmlsZQo+ICBjcmVhdGUgbW9kZSAxMDA2NDQgZHJpdmVycy9pM2MvbWFzdGVyL21pcGktaTNj LWhjaS9jbWQuaAo+ICBjcmVhdGUgbW9kZSAxMDA2NDQgZHJpdmVycy9pM2MvbWFzdGVyL21pcGkt aTNjLWhjaS9jbWRfdjEuYwo+ICBjcmVhdGUgbW9kZSAxMDA2NDQgZHJpdmVycy9pM2MvbWFzdGVy L21pcGktaTNjLWhjaS9jbWRfdjIuYwo+ICBjcmVhdGUgbW9kZSAxMDA2NDQgZHJpdmVycy9pM2Mv bWFzdGVyL21pcGktaTNjLWhjaS9jb3JlLmMKPiAgY3JlYXRlIG1vZGUgMTAwNjQ0IGRyaXZlcnMv aTNjL21hc3Rlci9taXBpLWkzYy1oY2kvZGF0LmgKPiAgY3JlYXRlIG1vZGUgMTAwNjQ0IGRyaXZl cnMvaTNjL21hc3Rlci9taXBpLWkzYy1oY2kvZGF0X3YxLmMKPiAgY3JlYXRlIG1vZGUgMTAwNjQ0 IGRyaXZlcnMvaTNjL21hc3Rlci9taXBpLWkzYy1oY2kvZGN0LmgKPiAgY3JlYXRlIG1vZGUgMTAw NjQ0IGRyaXZlcnMvaTNjL21hc3Rlci9taXBpLWkzYy1oY2kvZGN0X3YxLmMKPiAgY3JlYXRlIG1v ZGUgMTAwNjQ0IGRyaXZlcnMvaTNjL21hc3Rlci9taXBpLWkzYy1oY2kvZGVidWcuYwo+ICBjcmVh dGUgbW9kZSAxMDA2NDQgZHJpdmVycy9pM2MvbWFzdGVyL21pcGktaTNjLWhjaS9kZWJ1Zy5oCj4g IGNyZWF0ZSBtb2RlIDEwMDY0NCBkcml2ZXJzL2kzYy9tYXN0ZXIvbWlwaS1pM2MtaGNpL2RtYS5j Cj4gIGNyZWF0ZSBtb2RlIDEwMDY0NCBkcml2ZXJzL2kzYy9tYXN0ZXIvbWlwaS1pM2MtaGNpL2V4 dF9jYXBzLmMKPiAgY3JlYXRlIG1vZGUgMTAwNjQ0IGRyaXZlcnMvaTNjL21hc3Rlci9taXBpLWkz Yy1oY2kvZXh0X2NhcHMuaAo+ICBjcmVhdGUgbW9kZSAxMDA2NDQgZHJpdmVycy9pM2MvbWFzdGVy L21pcGktaTNjLWhjaS9oY2kuaAo+ICBjcmVhdGUgbW9kZSAxMDA2NDQgZHJpdmVycy9pM2MvbWFz dGVyL21pcGktaTNjLWhjaS9pYmkuaAo+ICBjcmVhdGUgbW9kZSAxMDA2NDQgZHJpdmVycy9pM2Mv bWFzdGVyL21pcGktaTNjLWhjaS9waW8uYwo+IAo+IGRpZmYgLS1naXQgYS9kcml2ZXJzL2kzYy9t YXN0ZXIvS2NvbmZpZyBiL2RyaXZlcnMvaTNjL21hc3Rlci9LY29uZmlnCj4gaW5kZXggNGU4MGEx ZmNiZi4uZWI1ODMwOTIzZiAxMDA2NDQKPiAtLS0gYS9kcml2ZXJzL2kzYy9tYXN0ZXIvS2NvbmZp Zwo+ICsrKyBiL2RyaXZlcnMvaTNjL21hc3Rlci9LY29uZmlnCj4gQEAgLTIxLDMgKzIxLDE2IEBA IGNvbmZpZyBEV19JM0NfTUFTVEVSCj4gIAo+ICAJICBUaGlzIGRyaXZlciBjYW4gYWxzbyBiZSBi dWlsdCBhcyBhIG1vZHVsZS4gIElmIHNvLCB0aGUgbW9kdWxlCj4gIAkgIHdpbGwgYmUgY2FsbGVk IGR3LWkzYy1tYXN0ZXIuCj4gKwo+ICtjb25maWcgTUlQSV9JM0NfSENJCj4gKwl0cmlzdGF0ZSAi TUlQSSBJM0MgSG9zdCBDb250cm9sbGVyIEludGVyZmFjZSBkcml2ZXIiCj4gKwlkZXBlbmRzIG9u IEkzQwo+ICsJaGVscAo+ICsJICBTdXBwb3J0IGZvciBoYXJkd2FyZSBmb2xsb3dpbmcgdGhlIE1J UEkgQWxpYW5jZSdzIEkzQyBIb3N0IENvbnRyb2xsZXIKPiArCSAgSW50ZXJmYWNlIHNwZWNpZmlj YXRpb24uCj4gKwo+ICsJICBGb3IgZGV0YWlscyBwbGVhc2Ugc2VlOgo+ICsJICBodHRwczovL3d3 dy5taXBpLm9yZy9zcGVjaWZpY2F0aW9ucy9pM2MtaGNpCj4gKwo+ICsJICBUaGlzIGRyaXZlciBj YW4gYWxzbyBiZSBidWlsdCBhcyBhIG1vZHVsZS4gIElmIHNvLCB0aGUgbW9kdWxlIHdpbGwgYmUK PiArCSAgY2FsbGVkIG1pcGktaTNjLWhjaS4KPiBkaWZmIC0tZ2l0IGEvZHJpdmVycy9pM2MvbWFz dGVyL01ha2VmaWxlIGIvZHJpdmVycy9pM2MvbWFzdGVyL01ha2VmaWxlCj4gaW5kZXggN2VlYTll MDg2MS4uYjg5MmZkNGNhZiAxMDA2NDQKPiAtLS0gYS9kcml2ZXJzL2kzYy9tYXN0ZXIvTWFrZWZp bGUKPiArKysgYi9kcml2ZXJzL2kzYy9tYXN0ZXIvTWFrZWZpbGUKPiBAQCAtMSwzICsxLDQgQEAK PiAgIyBTUERYLUxpY2Vuc2UtSWRlbnRpZmllcjogR1BMLTIuMC1vbmx5Cj4gIG9iai0kKENPTkZJ R19DRE5TX0kzQ19NQVNURVIpCQkrPSBpM2MtbWFzdGVyLWNkbnMubwo+ICBvYmotJChDT05GSUdf RFdfSTNDX01BU1RFUikJCSs9IGR3LWkzYy1tYXN0ZXIubwo+ICtvYmotJChDT05GSUdfTUlQSV9J M0NfSENJKQkJKz0gbWlwaS1pM2MtaGNpLwo+IGRpZmYgLS1naXQgYS9kcml2ZXJzL2kzYy9tYXN0 ZXIvbWlwaS1pM2MtaGNpL01ha2VmaWxlIGIvZHJpdmVycy9pM2MvbWFzdGVyL21pcGktaTNjLWhj aS9NYWtlZmlsZQo+IG5ldyBmaWxlIG1vZGUgMTAwNjQ0Cj4gaW5kZXggMDAwMDAwMDAwMC4uODM0 OTk2MGM1Ygo+IC0tLSAvZGV2L251bGwKPiArKysgYi9kcml2ZXJzL2kzYy9tYXN0ZXIvbWlwaS1p M2MtaGNpL01ha2VmaWxlCj4gQEAgLTAsMCArMSw5IEBACj4gKyMgU1BEWC1MaWNlbnNlLUlkZW50 aWZpZXI6IEJTRC0zLUNsYXVzZQoKSnVzdCBvdXQgb2YgY3VyaW9zaXR5LCB3aHkgdGhpcyBsaWNl bnNlPwoKPiArCj4gKyNjY2ZsYWdzLXkgOj0gLURERUJVRwoKUHJvYmFibHkgYSBsZWZ0b3Zlcj8K Cj4gKwo+ICtvYmotJChDT05GSUdfTUlQSV9JM0NfSENJKQkJKz0gbWlwaS1pM2MtaGNpLm8KPiAr bWlwaS1pM2MtaGNpLXkJCQkJOj0gY29yZS5vIGV4dF9jYXBzLm8gcGlvLm8gZG1hLm8gXAo+ICsJ CQkJCSAgIGNtZF92MS5vIGNtZF92Mi5vIFwKPiArCQkJCQkgICBkYXRfdjEubyBkY3RfdjEubyBc Cj4gKwkJCQkJICAgZGVidWcubwoKWy4uLl0KCj4gKyNkZWZpbmUgQ01EX0MxX0RBVEFfTEVOR1RI KHYpCQlGSUVMRF9QUkVQKFcxX01BU0soNjMsIDQ4KSwgdikKPiArI2RlZmluZSBDTURfQzFfT0ZG U0VUKHYpCQlGSUVMRF9QUkVQKFcxX01BU0soNDcsIDMyKSwgdikKPiArI2RlZmluZSBDTURfQzBf VE9DCQkJICAgICAgICAgICBXMF9CSVRfKDMxKQo+ICsjZGVmaW5lIENNRF9DMF9ST0MJCQkgICAg ICAgICAgIFcwX0JJVF8oMzApCj4gKyNkZWZpbmUgQ01EX0MwX1JOVwkJCSAgICAgICAgICAgVzBf QklUXygyOSkKPiArI2RlZmluZSBDTURfQzBfTU9ERSh2KQkJCUZJRUxEX1BSRVAoVzBfTUFTSygy OCwgMjYpLCB2KQo+ICsjZGVmaW5lIENNRF9DMF8xNl9CSVRfU1VCT0ZGU0VUCQlXMF9iaXQoMjUp Cj4gKyNkZWZpbmUgQ01EX0MwX0ZJUlNUX1BIQVNFX01PREUJCSAgICAgICAgICAgVzBfQklUXygy NCkKPiArI2RlZmluZSBDTURfQzBfREFUQV9MRU5HVEhfUE9TSVRJT04odikJRklFTERfUFJFUChX MF9NQVNLKDIzLCAyMiksIHYpCj4gKyNkZWZpbmUgQ01EX0MwX0RFVl9JTkRFWCh2KQkJRklFTERf UFJFUChXMF9NQVNLKDIwLCAxNiksIHYpCj4gKyNkZWZpbmUgQ01EX0MwX0NQCQkJICAgICAgICAg ICBXMF9CSVRfKDE1KQo+ICsjZGVmaW5lIENNRF9DMF9DTUQodikJCQlGSUVMRF9QUkVQKFcwX01B U0soMTQsIDcpLCB2KQo+ICsjZGVmaW5lIENNRF9DMF9USUQodikJCQlGSUVMRF9QUkVQKFcwX01B U0soNiwgMyksIHYpCj4gKwo+ICsvKgo+ICsgKiBJbnRlcm5hbCBDb250cm9sIENvbW1hbmQKPiAr ICovCj4gKwo+ICsjZGVmaW5lIENNRF8wX0FUVFJfTQkJCUZJRUxEX1BSRVAoQ01EXzBfQVRUUiwg MHg3KQo+ICsKPiArI2RlZmluZSBDTURfTTFfVkVORE9SX1NQRUNJRklDCQkgICAgICAgICAgIFcx X01BU0soNjMsIDMyKQo+ICsjZGVmaW5lIENNRF9NMF9NSVBJX1JFU0VSVkVECQkgICAgICAgICAg IFcwX01BU0soMzEsIDEyKQo+ICsjZGVmaW5lIENNRF9NMF9NSVBJX0NNRAkJCSAgICAgICAgICAg VzBfTUFTSygxMSwgOCkKPiArI2RlZmluZSBDTURfTTBfVkVORE9SX0lORk9fUFJFU0VOVAkgICAg ICAgICAgIFcwX0JJVF8oNykKPiArI2RlZmluZSBDTURfTTBfVElEKHYpCQkJRklFTERfUFJFUChX MF9NQVNLKDYsIDMpLCB2KQo+ICsKPiArCj4gK3N0YXRpYyBpbnQgaGNpX2NtZF92MV9wcmVwX2Nj YyhzdHJ1Y3QgaTNjX2hjaSAqaGNpLAo+ICsJCQkgICAgICAgc3RydWN0IGhjaV94ZmVyICp4ZmVy LAo+ICsJCQkgICAgICAgdTggY2NjX2FkZHIsIHU4IGNjY19jbWQsIGJvb2wgcmF3KQo+ICt7Cj4g Kwl1X2ludCBkYXRfaWR4ID0gMDsKCkkgZ3Vlc3MgdV9pbnQgaGVyIGFuZCBiZWxvdyBpcyBub3Qg dGhlIHByZWZlcnJlZCB3YXkgdG8gZGVjbGFyZSBhbiB1bnNpZ25lZCBpbnQ/Cgo+ICsJaW50IG1v ZGUgPSBoY2lfZ2V0X2kzY19tb2RlKGhjaSk7Cj4gKwl1OCAqZGF0YSA9IHhmZXItPmRhdGE7Cj4g Kwl1X2ludCBkYXRhX2xlbiA9IHhmZXItPmRhdGFfbGVuOwo+ICsJYm9vbCBybncgPSB4ZmVyLT5y bnc7Cj4gKwlpbnQgcmV0Owo+ICsKPiArCUJVR19PTihyYXcpOwoKSXQgbG9va3MgbGlrZSAncmF3 JyBjYW5ub3QgYmUgdXNlZCB3aXRoIHYxIChhdCBsZWFzdCB5b3Ugc2VlbSB0byB0YWtlCmNhcmUg b2YgaXQgaW4gdjIpLCBzbyBtYXliZSBCVUdfT04gaXMgYSBiaXQgcmFkaWNhbCBoZXJlIGFuZCB5 b3UgY2FuCnNpbXBseSByZXR1cm4gYW4gZXJyb3I/IEkgdGhpbmsgdGhlIHVzZSBvZiBCVUcoKSBp cyBub3QgYXBwcmVjaWF0ZWQgaW4KZ2VuZXJhbC4KCj4gKwo+ICsJaWYgKGNjY19hZGRyICE9IEkz Q19CUk9BRENBU1RfQUREUikgewo+ICsJCXJldCA9IGkzY19oY2lfZGF0X2dldF9pbmRleChoY2ks IGNjY19hZGRyKTsKPiArCQlpZiAocmV0IDwgMCkKPiArCQkJcmV0dXJuIC1FTk9ERVY7Cj4gKwkJ ZGF0X2lkeCA9IHJldDsKPiArCX0KPiArCj4gKwl4ZmVyLT5jbWRfdGlkID0gaGNpX2dldF90aWQo NCk7Cj4gKwo+ICsJaWYgKCFybncgJiYgZGF0YV9sZW4gPD0gNCkgewo+ICsJCS8qIHdlIHVzZSBh biBJbW1lZGlhdGUgRGF0YSBUcmFuc2ZlciBDb21tYW5kICovCj4gKwkJeGZlci0+Y21kX2Rlc2Nb MF0gPQo+ICsJCQlDTURfMF9BVFRSX0kgfAo+ICsJCQlDTURfSTBfVElEKHhmZXItPmNtZF90aWQp IHwKPiArCQkJQ01EX0kwX0NNRChjY2NfY21kKSB8IENNRF9JMF9DUCB8Cj4gKwkJCUNNRF9JMF9E RVZfSU5ERVgoZGF0X2lkeCkgfAo+ICsJCQlDTURfSTBfRFRUKGRhdGFfbGVuKSB8Cj4gKwkJCUNN RF9JMF9NT0RFKG1vZGUpOwo+ICsJCXhmZXItPmNtZF9kZXNjWzFdID0gMDsKPiArCQlzd2l0Y2gg KGRhdGFfbGVuKSB7Cj4gKwkJY2FzZSA0Ogo+ICsJCQl4ZmVyLT5jbWRfZGVzY1sxXSB8PSBDTURf STFfREFUQV9CWVRFXzQoZGF0YVszXSk7Cj4gKwkJCWZhbGx0aHJvdWdoOwo+ICsJCWNhc2UgMzoK PiArCQkJeGZlci0+Y21kX2Rlc2NbMV0gfD0gQ01EX0kxX0RBVEFfQllURV8zKGRhdGFbMl0pOwo+ ICsJCQlmYWxsdGhyb3VnaDsKPiArCQljYXNlIDI6Cj4gKwkJCXhmZXItPmNtZF9kZXNjWzFdIHw9 IENNRF9JMV9EQVRBX0JZVEVfMihkYXRhWzFdKTsKPiArCQkJZmFsbHRocm91Z2g7Cj4gKwkJY2Fz ZSAxOgo+ICsJCQl4ZmVyLT5jbWRfZGVzY1sxXSB8PSBDTURfSTFfREFUQV9CWVRFXzEoZGF0YVsw XSk7Cj4gKwkJCWZhbGx0aHJvdWdoOwo+ICsJCWNhc2UgMDoKPiArCQkJYnJlYWs7Cj4gKwkJfQo+ ICsJCS8qIHdlIGNvbnN1bWVkIGFsbCB0aGUgZGF0YSBpbiB0aGUgY21kIGRlc2NyaXB0b3IgKi8K PiArCQl4ZmVyLT5kYXRhID0gTlVMTDsKPiArCX0gZWxzZSB7Cj4gKwkJLyogd2UgdXNlIGEgUmVn dWxhciBEYXRhIFRyYW5zZmVyIENvbW1hbmQgKi8KPiArCQl4ZmVyLT5jbWRfZGVzY1swXSA9Cj4g KwkJCUNNRF8wX0FUVFJfUiB8Cj4gKwkJCUNNRF9SMF9USUQoeGZlci0+Y21kX3RpZCkgfAo+ICsJ CQlDTURfUjBfQ01EKGNjY19jbWQpIHwgQ01EX1IwX0NQIHwKPiArCQkJQ01EX1IwX0RFVl9JTkRF WChkYXRfaWR4KSB8Cj4gKwkJCUNNRF9SMF9NT0RFKG1vZGUpIHwKPiArCQkJKHJudyA/IENNRF9S MF9STlcgOiAwKTsKPiArCQl4ZmVyLT5jbWRfZGVzY1sxXSA9Cj4gKwkJCUNNRF9SMV9EQVRBX0xF TkdUSChkYXRhX2xlbik7Cj4gKwl9Cj4gKwo+ICsJcmV0dXJuIDA7Cj4gK30KClsuLi5dCgo+ICtz dGF0aWMgaW50IGhjaV9jbWRfdjFfZGFhKHN0cnVjdCBpM2NfaGNpICpoY2kpCj4gK3sKPiArCXN0 cnVjdCBoY2lfeGZlciAqeGZlcjsKPiArCWludCByZXQsIGRhdF9pZHggPSAtMTsKPiArCXU4IG5l eHRfYWRkcjsKPiArCXU2NCBwaWQ7Cj4gKwl1X2ludCBkY3IsIGJjcjsKPiArCURFQ0xBUkVfQ09N UExFVElPTl9PTlNUQUNLKGRvbmUpOwo+ICsKPiArCXhmZXIgPSBoY2lfYWxsb2NfeGZlcigyKTsK PiArCWlmICgheGZlcikKPiArCQlyZXR1cm4gLUVOT01FTTsKPiArCj4gKwkvKgo+ICsJICogU2lt cGxlIGZvciBub3c6IHdlIGFsbG9jYXRlIGEgdGVtcG9yYXJ5IERBVCBlbnRyeSwgZG8gYSBzaW5n bGUKPiArCSAqIERBQSwgcmVnaXN0ZXIgdGhlIGRldmljZSB3aGljaCB3aWxsIGFsbG9jYXRlIGl0 cyBvd24gREFUIGVudHJ5Cj4gKwkgKiB2aWEgdGhlIGNvcmUgY2FsbGJhY2ssIHRoZW4gZnJlZSB0 aGUgdGVtcG9yYXJ5IERBVCBlbnRyeS4KPiArCSAqIExvb3AgdW50aWwgdGhlcmUgaXMgbm8gbW9y ZSBkZXZpY2VzIHRvIGFzc2lnbiBhbiBhZGRyZXNzIHRvLgo+ICsJICogWWVzLCB0aGVyZSBpcyBy b29tIGZvciBpbXByb3ZlbWVudHMuCj4gKwkgKi8KPiArCWZvciAoOzspIHsKPiArCQlyZXQgPSBp M2NfaGNpX2RhdF9hbGxvY19lbnRyeShoY2kpOwo+ICsJCWlmIChyZXQgPCAwKQo+ICsJCQlicmVh azsKPiArCQlkYXRfaWR4ID0gcmV0Owo+ICsJCXJldCA9IGkzY19tYXN0ZXJfZ2V0X2ZyZWVfYWRk cigmaGNpLT5tYXN0ZXIsIG5leHRfYWRkcik7Cj4gKwkJaWYgKHJldCA8IDApCj4gKwkJCWJyZWFr Owo+ICsJCW5leHRfYWRkciA9IHJldDsKPiArCj4gKwkJREJHKCJuZXh0X2FkZHIgPSAweCUwMngs IERBQSB1c2luZyBEQVQgJWQiLCBuZXh0X2FkZHIsIGRhdF9pZHgpOwo+ICsJCWkzY19oY2lfZGF0 X3NldF9keW5hbWljX2FkZHIoaGNpLCBkYXRfaWR4LCBuZXh0X2FkZHIpOwo+ICsJCWkzY19oY2lf ZGN0X2luZGV4X3Jlc2V0KGhjaSk7Cj4gKwo+ICsJCXhmZXItPmNtZF90aWQgPSBoY2lfZ2V0X3Rp ZCg0KTsKPiArCQl4ZmVyLT5jbWRfZGVzY1swXSA9Cj4gKwkJCUNNRF8wX0FUVFJfQSB8Cj4gKwkJ CUNNRF9BMF9USUQoeGZlci0+Y21kX3RpZCkgfAo+ICsJCQlDTURfQTBfQ01EKEkzQ19DQ0NfRU5U REFBKSB8Cj4gKwkJCUNNRF9BMF9ERVZfSU5ERVgoZGF0X2lkeCkgfAo+ICsJCQlDTURfQTBfREVW X0NPVU5UKDEpIHwKPiArCQkJQ01EX0EwX1JPQyB8IENNRF9BMF9UT0M7Cj4gKwkJeGZlci0+Y21k X2Rlc2NbMV0gPSAwOwo+ICsJCWhjaS0+aW8tPnF1ZXVlX3hmZXIoaGNpLCB4ZmVyLCAxKTsKPiAr CQlpZiAoIXdhaXRfZm9yX2NvbXBsZXRpb25fdGltZW91dCgmZG9uZSwgSFopICYmCj4gKwkJICAg IGhjaS0+aW8tPmRlcXVldWVfeGZlcihoY2ksIHhmZXIsIDEpKSB7Cj4gKwkJCXJldCA9IC1FVElN RTsKPiArCQkJYnJlYWs7Cj4gKwkJfQo+ICsJCWlmIChSRVNQX1NUQVRVUyh4ZmVyWzBdLnJlc3Bv bnNlKSA9PSBSRVNQX0VSUl9OQUNLICYmCj4gKwkJICAgIFJFU1BfU1RBVFVTKHhmZXJbMF0ucmVz cG9uc2UpID09IDEpIHsKPiArCQkJcmV0ID0gMDsgIC8qIG5vIG1vcmUgZGV2aWNlcyB0byBiZSBh c3NpZ25lZCAqLwo+ICsJCQlicmVhazsKPiArCQl9Cj4gKwkJaWYgKFJFU1BfU1RBVFVTKHhmZXJb MF0ucmVzcG9uc2UpICE9IFJFU1BfU1VDQ0VTUykgewo+ICsJCQlyZXQgPSAtRUlPOwo+ICsJCQli cmVhazsKPiArCQl9Cj4gKwo+ICsJCWkzY19oY2lfZGN0X2dldF92YWwoaGNpLCAwLCAmcGlkLCAm ZGNyLCAmYmNyKTsKPiArCQlEQkcoImFzc2lnbmVkIGFkZHJlc3MgJSN4IHRvIGRldmljZSBQSUQ9 MHglbGx4IERDUj0lI3ggQkNSPSUjeCIsCj4gKwkJICAgIG5leHRfYWRkciwgcGlkLCBkY3IsIGJj cik7Cj4gKwo+ICsJCWkzY19oY2lfZGF0X2ZyZWVfZW50cnkoaGNpLCBkYXRfaWR4KTsKPiArCQlk YXRfaWR4ID0gLTE7Cj4gKwo+ICsJCS8qCj4gKwkJICogVE9ETzogRXh0ZW5kIHRoZSBzdWJzeXN0 ZW0gbGF5ZXIgdG8gYWxsb3cgZm9yIHJlZ2lzdGVyaW5nCj4gKwkJICogbmV3IGRldmljZSBhbmQg cHJvdmlkZSBCQ1IvRENSL1BJRCBhdCB0aGUgc2FtZSB0aW1lLgoKTm90IHN1cmUgdGhpcyBpcyBu ZWVkZWQgaWYgeW91IGRvbid0IHVzZSBpdCBkaXJlY3RseSBhcyB0aGUgY29yZSB3aWxsCmFueXdh eSAoaW4gaXRzIGN1cnJlbnQgZm9ybSkgc2VuZCB0aGUgcmVsZXZhbnQgQ0NDIHRvIHJlYWQgdGhl c2UKcmVnaXN0ZXJzLgoKPiArCQkgKi8KPiArCQlyZXQgPSBpM2NfbWFzdGVyX2FkZF9pM2NfZGV2 X2xvY2tlZCgmaGNpLT5tYXN0ZXIsIG5leHRfYWRkcik7Cj4gKwkJaWYgKHJldCkKPiArCQkJYnJl YWs7Cj4gKwl9Cj4gKwo+ICsJaWYgKGRhdF9pZHggPj0gMCkKPiArCQlpM2NfaGNpX2RhdF9mcmVl X2VudHJ5KGhjaSwgZGF0X2lkeCk7Cj4gKwloY2lfZnJlZV94ZmVyKHhmZXIsIDEpOwo+ICsJcmV0 dXJuIHJldDsKPiArfQo+ICsKPiArY29uc3Qgc3RydWN0IGhjaV9jbWRfb3BzIGkzY19oY2lfY21k X3YxID0gewo+ICsJLnByZXBfY2NjCQk9IGhjaV9jbWRfdjFfcHJlcF9jY2MsCj4gKwkucHJlcF9p M2NfeGZlcgkJPSBoY2lfY21kX3YxX3ByZXBfaTNjX3hmZXIsCj4gKwkucHJlcF9pMmNfeGZlcgkJ PSBoY2lfY21kX3YxX3ByZXBfaTJjX3hmZXIsCj4gKwkucGVyZm9ybV9kYWEJCT0gaGNpX2NtZF92 MV9kYWEsCgpJIGtub3cgQm9yaXMgZG9lcyBub3QgbGlrZSBzdWNoIHNwYWNlIGFsaWdubWVudCA6 KQoKPiArfTsKClsuLi5dCgo+ICt2b2lkIGkzY19oY2lfcmVzdW1lKHN0cnVjdCBpM2NfaGNpICpo Y2kpCj4gK3sKPiArCS8qIHRoZSBIQ19DT05UUk9MX1JFU1VNRSBiaXQgaXMgUi9XMUMgc28ganVz dCByZWFkIGFuZCB3cml0ZSBiYWNrICovCj4gKwlyZWdfd3JpdGUoSENfQ09OVFJPTCwgcmVnX3Jl YWQoSENfQ09OVFJPTCkpOwo+ICt9Cj4gKwo+ICsvKiBsb2NhdGVkIGhlcmUgcmF0aGVyIHRoYW4g cGlvLmMgYmVjYXVzZSBuZWVkZWQgYml0cyBhcmUgaW4gY29yZSByZWcgc3BhY2UgKi8KPiArdm9p ZCBpM2NfaGNpX3Bpb19yZXNldChzdHJ1Y3QgaTNjX2hjaSAqaGNpKQo+ICt7Cj4gKwlyZWdfd3Jp dGUoUkVTRVRfQ09OVFJPTCwgUlhfRklGT19SU1R8VFhfRklGT19SU1R8UkVTUF9RVUVVRV9SU1Qp OwoKU3R5bGUgd2l0aCBtaXNzaW5nIHNwYWNlcyAgICAgICAgICAgICAgICAgIF4gXgoKPiArfQo+ ICsKPiArLyogbG9jYXRlZCBoZXJlIHJhdGhlciB0aGFuIGRjdC5jIGJlY2F1c2UgbmVlZGVkIGJp dHMgYXJlIGluIGNvcmUgcmVnIHNwYWNlICovCj4gK3ZvaWQgaTNjX2hjaV9kY3RfaW5kZXhfcmVz ZXQoc3RydWN0IGkzY19oY2kgKmhjaSkKPiArewo+ICsJcmVnX3dyaXRlKERDVF9TRUNUSU9OX09G RlNFVCwgRklFTERfUFJFUChEQ1RfVEFCTEVfSU5ERVgsIDApKTsKPiArfQo+ICsKPiArc3RhdGlj IGludCBpM2NfaGNpX3NlbmRfY2NjX2NtZChzdHJ1Y3QgaTNjX21hc3Rlcl9jb250cm9sbGVyICpt LAo+ICsJCQkJc3RydWN0IGkzY19jY2NfY21kICpjY2MpCj4gK3sKPiArCXN0cnVjdCBpM2NfaGNp ICpoY2kgPSB0b19pM2NfaGNpKG0pOwo+ICsJc3RydWN0IGhjaV94ZmVyICp4ZmVyOwo+ICsJYm9v bCByYXcgPSAhIShoY2ktPnF1aXJrcyAmIEhDSV9RVUlSS19SQVdfQ0NDKTsKPiArCWJvb2wgcHJl Zml4ZWQgPSByYXcgJiYgISEoY2NjLT5pZCAmIEkzQ19DQ0NfRElSRUNUKTsKPiArCXVfaW50IG54 ZmVycyA9IGNjYy0+bmRlc3RzICsgcHJlZml4ZWQ7Cj4gKwlERUNMQVJFX0NPTVBMRVRJT05fT05T VEFDSyhkb25lKTsKPiArCWludCBpLCBsYXN0LCByZXQgPSAwOwo+ICsKPiArCURCRygiY21kPSUj eCBybnc9JWQgbmRlc3RzPSVkIGRhdGFbMF0ubGVuPSVkIiwKPiArCSAgICBjY2MtPmlkLCBjY2Mt PnJudywgY2NjLT5uZGVzdHMsIGNjYy0+ZGVzdHNbMF0ucGF5bG9hZC5sZW4pOwo+ICsKPiArCXhm ZXIgPSBoY2lfYWxsb2NfeGZlcihueGZlcnMpOwo+ICsJaWYgKCF4ZmVyKQo+ICsJCXJldHVybiAt RU5PTUVNOwo+ICsKPiArCWlmIChwcmVmaXhlZCkgewo+ICsJCXhmZXItPmRhdGEgPSBOVUxMOwo+ ICsJCXhmZXItPmRhdGFfbGVuID0gMDsKPiArCQl4ZmVyLT5ybncgPSBmYWxzZTsKPiArCQloY2kt PmNtZC0+cHJlcF9jY2MoaGNpLCB4ZmVyLCBJM0NfQlJPQURDQVNUX0FERFIsCj4gKwkJCQkgICBj Y2MtPmlkLCB0cnVlKTsKPiArCQl4ZmVyKys7Cj4gKwl9Cj4gKwo+ICsJZm9yIChpID0gMDsgaSA8 IG54ZmVycyAtIHByZWZpeGVkOyBpKyspIHsKPiArCQl4ZmVyW2ldLmRhdGEgPSBjY2MtPmRlc3Rz W2ldLnBheWxvYWQuZGF0YTsKPiArCQl4ZmVyW2ldLmRhdGFfbGVuID0gY2NjLT5kZXN0c1tpXS5w YXlsb2FkLmxlbjsKPiArCQl4ZmVyW2ldLnJudyA9IGNjYy0+cm53Owo+ICsJCXJldCA9IGhjaS0+ Y21kLT5wcmVwX2NjYyhoY2ksICZ4ZmVyW2ldLCBjY2MtPmRlc3RzW2ldLmFkZHIsCj4gKwkJCQkJ IGNjYy0+aWQsIHJhdyk7Cj4gKwkJaWYgKHJldCkKPiArCQkJZ290byBvdXQ7Cj4gKwkJeGZlcltp XS5jbWRfZGVzY1swXSB8PSBDTURfMF9ST0M7Cj4gKwl9Cj4gKwlsYXN0ID0gaSAtIDE7Cj4gKwl4 ZmVyW2xhc3RdLmNtZF9kZXNjWzBdIHw9IENNRF8wX1RPQzsKPiArCXhmZXJbbGFzdF0uY29tcGxl dGlvbiA9ICZkb25lOwo+ICsKPiArCWlmIChwcmVmaXhlZCkKPiArCQl4ZmVyLS07Cj4gKwo+ICsJ cmV0ID0gaGNpLT5pby0+cXVldWVfeGZlcihoY2ksIHhmZXIsIG54ZmVycyk7Cj4gKwlpZiAocmV0 KQo+ICsJCWdvdG8gb3V0Owo+ICsJaWYgKCF3YWl0X2Zvcl9jb21wbGV0aW9uX3RpbWVvdXQoJmRv bmUsIEhaKSAmJgo+ICsJICAgIGhjaS0+aW8tPmRlcXVldWVfeGZlcihoY2ksIHhmZXIsIG54ZmVy cykpIHsKPiArCQlyZXQgPSAtRVRJTUU7Cj4gKwkJZ290byBvdXQ7Cj4gKwl9Cj4gKwlmb3IgKGkg PSBwcmVmaXhlZDsgaSA8IG54ZmVyczsgaSsrKSB7Cj4gKwkJaWYgKGNjYy0+cm53KQo+ICsJCQlj Y2MtPmRlc3RzW2kgLSBwcmVmaXhlZF0ucGF5bG9hZC5sZW4gPQo+ICsJCQkJUkVTUF9EQVRBX0xF TkdUSCh4ZmVyW2ldLnJlc3BvbnNlKTsKPiArCQlpZiAoUkVTUF9TVEFUVVMoeGZlcltpXS5yZXNw b25zZSkgIT0gUkVTUF9TVUNDRVNTKSB7Cj4gKwkJCXJldCA9IC1FSU87Cj4gKwkJCWdvdG8gb3V0 Owo+ICsJCX0KPiArCX0KPiArCj4gKyNpZiAwCj4gKwlpZiAoY2NjLT5ybncpIHsKPiArCQlIRVhE VU1QKCJnb3Q6ICIsIGNjYy0+ZGVzdHNbMF0ucGF5bG9hZC5kYXRhLAo+ICsJCQkJIGNjYy0+ZGVz dHNbMF0ucGF5bG9hZC5sZW4pOwo+ICsJfQo+ICsjZW5kaWYKCkkgZ3Vlc3MgdGhpcyBkZWJ1ZyBi bG9jayBjYW4gYmUgZHJvcHBlZCB0b28gKHRoZXJlIGFyZSBtYW55IGRlYnVnCmluZm9ybWF0aW9u IHRoZSBzaG91bGQgcHJvYmFibHkgYmUgZHJvcHBlZCBvciB0dXJuZWQgaW50byBkZXZfaW5mbygp Cm9yIHNpbWlsYXIpLgoKPiArCj4gK291dDoKPiArCWhjaV9mcmVlX3hmZXIoeGZlciwgbnhmZXJz KTsKPiArCXJldHVybiByZXQ7Cj4gK30KPiArCj4gK3N0YXRpYyBpbnQgaTNjX2hjaV9kYWEoc3Ry dWN0IGkzY19tYXN0ZXJfY29udHJvbGxlciAqbSkKPiArewo+ICsJc3RydWN0IGkzY19oY2kgKmhj aSA9IHRvX2kzY19oY2kobSk7Cj4gKwo+ICsJREJHKCIiKTsKPiArCj4gKwlyZXR1cm4gaGNpLT5j bWQtPnBlcmZvcm1fZGFhKGhjaSk7Cj4gK30KClsuLi5dCgo+IGRpZmYgLS1naXQgYS9kcml2ZXJz L2kzYy9tYXN0ZXIvbWlwaS1pM2MtaGNpL2RlYnVnLmMgYi9kcml2ZXJzL2kzYy9tYXN0ZXIvbWlw aS1pM2MtaGNpL2RlYnVnLmMKPiBuZXcgZmlsZSBtb2RlIDEwMDY0NAo+IGluZGV4IDAwMDAwMDAw MDAuLjM4ODU0OTkxMTkKPiAtLS0gL2Rldi9udWxsCj4gKysrIGIvZHJpdmVycy9pM2MvbWFzdGVy L21pcGktaTNjLWhjaS9kZWJ1Zy5jCj4gQEAgLTAsMCArMSw3OSBAQAo+ICsvLyBTUERYLUxpY2Vu c2UtSWRlbnRpZmllcjogQlNELTMtQ2xhdXNlCj4gKy8qCj4gKyAqIENvcHlyaWdodCAoYykgMjAy MCwgTUlQSSBBbGxpYW5jZSwgSW5jLgo+ICsgKgo+ICsgKiBBdXRob3I6IE5pY29sYXMgUGl0cmUg PG5waXRyZUBiYXlsaWJyZS5jb20+Cj4gKyAqLwo+ICsKPiArI2luY2x1ZGUgPGxpbnV4L2Rldmlj ZS5oPgo+ICsjaW5jbHVkZSA8bGludXgvaW8uaD4KPiArI2luY2x1ZGUgPGxpbnV4L2kzYy9tYXN0 ZXIuaD4KPiArI2luY2x1ZGUgPGxpbnV4L3ByaW50ay5oPgo+ICsKPiArI2luY2x1ZGUgImhjaS5o Igo+ICsjaW5jbHVkZSAiZGVidWcuaCIKPiArCj4gKy8qCj4gKyAqIFBhdWwgS2ltZWxtYW4ncyBk ZWJ1ZyB0cmFjZSBsb2cgZmFjaWxpdHkuCj4gKyAqIFRoaXMgaXMgY29tcGxldGVseSB2ZW5kb3Ig YW5kIGhhcmR3YXJlIHNwZWNpZmljLgo+ICsgKi8KPiArdm9pZCBfX1BLX2RlYnVnX3RyYWNlKHN0 cnVjdCBpM2NfaGNpICpoY2ksIGNvbnN0IGNoYXIgKmZ1bmMpCj4gK3sKPiArCXZvaWQgX19pb21l bSAqdHJjcCA9ICh2b2lkIF9faW9tZW0gKiloY2ktPnZlbmRvcl9kYXRhICsgNyo0OwoKTWF5YmUg eW91IG5lZWQgdG8gZGVmaW5lIHdoYXQgaXMgNyo0ICwgMCo0IGJlbG93LCB2ID4+IDI3LCBldGMK CkFsc28gdGhlcmUgYXJlIG1hbnkgbWlzc2luZyBzcGFjZXMgYmV0d2VlbiBvcGVyYXRvcnMgKDcg KiA0LHcgJiAoMSA8PDkpLgoKPiArCXVpbnQzMl90IGlkeCwgY3ljbGVzLCBtYXRjaDsKPiArCXVp bnQzMl90IHRyYWNlX2Z1bGwgPSAxOwo+ICsKPiArCWlmICghaGNpLT52ZW5kb3JfZGF0YSkKPiAr CQlyZXR1cm47Cj4gKwo+ICsJaWR4ID0gcmVhZGwodHJjcCArIDAqNCk7Cj4gKwljeWNsZXMgPSBp ZHg+PjE2Owo+ICsJaWR4ICY9IDB4RkZGRjsKPiArCWlmIChpZHggPiAweEZGRikgewo+ICsJCXBy X2luZm8oIlRyYWNlIGNvdW50PSVkLCBzdG9yZWQ9JWQ7IGN5Y2xlcz0lZFxuIiwgaWR4LCAweEZG RiwgY3ljbGVzKTsKPiArCQltYXRjaCA9IChpZHgtMSkgJiAweEZGRjsKPiArCX0gZWxzZSB7Cj4g KwkJcHJfaW5mbygiVHJhY2UgY291bnQ9JWQ7IGN5Y2xlcz0lZFxuIiwgaWR4LCBjeWNsZXMpOwo+ ICsJCW1hdGNoID0gaWR4Owo+ICsJCWlkeCA9IDA7Cj4gKwl9Cj4gKwo+ICsJd3JpdGVsKGlkeCB8 ICh0cmFjZV9mdWxsIDw8IDMxKSwgdHJjcCArIDEqNCk7IC8vIDFzdCB0byByZWFkCj4gKwlmb3Ig KDsgaWR4ICE9IG1hdGNoOyBpZHggPSAoaWR4KzEpJjB4RkZGKSB7IC8vIHJpbmcgdGhyb3VnaCBp dAo+ICsJCXVpbnQzMl90IHYgPSByZWFkbCh0cmNwICsgMSo0KTsgLy8gZ2V0IHRyYWNlIHdvcmQK PiArCQl1aW50MzJfdCB1cCA9IHRyYWNlX2Z1bGwgPyByZWFkbCh0cmNwICsgMSo0KSA6IDA7Cj4g KwkJY2hhciAqZTIgPSAodiYoMTw8OSkpPyIvTkFDSyI6IiI7Cj4gKwkJY2hhciAqZTMgPSAodiYo MTw8MTApKT8iL1dSQUJUIjoiIjsKPiArCQljaGFyICplNCA9ICh2JigxPDwxMSkpPyIvVEVSTSI6 IiI7Cj4gKwkJY2hhciAqZTUgPSAodiAmICgxPDw3KSkgPyAiL0lOVlJFUSIgOiAiIjsKPiArCQlj aGFyICplNiA9ICh2ICYgKDE8PDgpKSA/ICIvVElNRU9VVCIgOiAiIjsKPiArCQlpZiAodHJhY2Vf ZnVsbCkgewo+ICsJCQl1aW50MzJfdCBjbWQgPSB1cCA+PiAxNjsKPiArCQkJcHJfaW5mbygiJS01 ZDogIiwgdXAgJiAweEZGRkYpOwo+ICsJCQlpZiAoY21kKQo+ICsJCQkJcHJfaW5mbygiY21kPSVz IHRpZD0lMDJYLCBUT0M9JWQsIFJPQz0lZCwgJXMgJXMgYWRkcj0lWFxuLS0tIiwKPiArCQkJCQko Y21kICYgKDE8PDIpKSA/ICJDbWQiIDogIkRBQSIsCj4gKwkJCQkJKGNtZCA+PiAzKSAmIDB4Riwg Y21kID4+IDMxLCAoY21kID4+IDMwKSAmIDEsCj4gKwkJCQkJKChjbWQgPj4gNykgJiAxKSA/ICJJ MkMiIDogIkkzQyIsCj4gKwkJCQkJKGNtZCAmICgxPDw4KSk/IlJlYWQgIjoiV3JpdGUiLAo+ICsJ CQkJCShjbWQgPj4gOSkgJiAweDdGKTsKPiArCQkJZWxzZQo+ICsJCQkJcHJfY29udCgiXG4tLS0t Iik7Cj4gKwkJfSBlbHNlCj4gKwkJCXByX2luZm8oIiUwOFg6ICIsIHYpOwo+ICsJCXByX2NvbnQo IiMlM1g6IHN0PSUwM1gsc3RhdHVzPSUwMlglcyVzJXMlcyVzJXMlcyVzJXMlcyVzJXNcbiIsIGlk eCwKPiArCQkJdiAmIDB4N0YsICh2ID4+IDEyKSAmIDB4RkZGLCAoKHYgPj4gMjQpICYgMSkgPyAi LCBjbHJzIiA6ICIiLAo+ICsJCQkoKHYgPj4gMjUpICYgMSkgPyAiLCBFUlJPUiIgOiAiIiwgZTIs IGUzLCBlNCwgZTUsIGU2LAo+ICsJCQkoKHYgPj4gMjYpICYgMSkgPyAiLGNscmUiIDogIiIsICgo diA+PiAyNykgJiAxKSA/ICIsIE5BQ0siIDogIiIsCj4gKwkJCSgodiA+PiAyOCkgJiAxKSA/ICIs IElOX0RBQSIgOiAiIiwKPiArCQkJKCh2ID4+IDI5KSAmIDEpID8gIiwgSVJRIiA6ICIiLCAoKHYg Pj4gMzApICYgMSkgPyAiLCBjUlNQIiA6ICIiKTsKPiArCX0KPiArCS8vIGNsZWFyIHRyYWNlIGlu ZGV4IHNvIGNhbiB0ZWxsIHdoZW4gd2UgaGF2ZSBuZXcgb25lcwo+ICsJd3JpdGVsKDAsIHRyY3Ag KyAwKjQpOwo+ICt9CgpbLi4uXQoKPiArc3RhdGljIHZvaWQgaGNpX2RtYV9jbGVhbnVwKHN0cnVj dCBpM2NfaGNpICpoY2kpCj4gK3sKPiArCXN0cnVjdCBoY2lfcmluZ3NfZGF0YSAqcmluZ3MgPSBo Y2ktPmlvX2RhdGE7Cj4gKwlzdHJ1Y3QgaGNpX3JoX2RhdGEgKnJoOwo+ICsJdV9pbnQgaTsKPiAr Cj4gKwlpZiAoIXJpbmdzKQo+ICsJCXJldHVybjsKPiArCj4gKwlmb3IgKGkgPSAwOyBpIDwgcmlu Z3MtPnRvdGFsOyBpKyspIHsKPiArCQlyaCA9ICZyaW5ncy0+aGVhZGVyc1tpXTsKPiArCj4gKwkJ cmhfcmVnX3dyaXRlKFJJTkdfQ09OVFJPTCwgMCk7Cj4gKwkJcmhfcmVnX3dyaXRlKENSX1NFVFVQ LCAwKTsKPiArCQlyaF9yZWdfd3JpdGUoSUJJX1NFVFVQLCAwKTsKPiArCQlyaF9yZWdfd3JpdGUo SU5UUl9TSUdOQUxfRU5BQkxFLCAwKTsKPiArCj4gKwkJaWYgKHJoLT54ZmVyKQo+ICsJCQlkbWFf ZnJlZV9jb2hlcmVudCgmaGNpLT5tYXN0ZXIuZGV2LAo+ICsJCQkJCSAgcmgtPnhmZXJfc3RydWN0 X3N6ICogcmgtPnhmZXJfZW50cmllcywKPiArCQkJCQkgIHJoLT54ZmVyLCByaC0+eGZlcl9waHlz KTsKPiArCQlpZiAocmgtPnJlc3ApCj4gKwkJCWRtYV9mcmVlX2NvaGVyZW50KCZoY2ktPm1hc3Rl ci5kZXYsCj4gKwkJCQkJICByaC0+cmVzcF9zdHJ1Y3Rfc3ogKiByaC0+eGZlcl9lbnRyaWVzLAo+ ICsJCQkJCSAgcmgtPnJlc3AsIHJoLT5yZXNwX3BoeXMpOwo+ICsJCWtmcmVlKHJoLT5zcmNfeGZl cnMpOwo+ICsJCWlmIChyaC0+aWJpX3N0YXR1cykKPiArCQkJZG1hX2ZyZWVfY29oZXJlbnQoJmhj aS0+bWFzdGVyLmRldiwKPiArCQkJCQkgIHJoLT5pYmlfc3RhdHVzX3N6ICogcmgtPmliaV9zdGF0 dXNfZW50cmllcywKPiArCQkJCQkgIHJoLT5pYmlfc3RhdHVzLCByaC0+aWJpX3N0YXR1c19waHlz KTsKPiArCQlpZiAocmgtPmliaV9kYXRhX3BoeXMpCgpJIHdhcyB0b2xkIHRoYXQgX3BoeXMgd2Fz IGEgdmVyeSBiYWQgc3VmZml4IGZvciBzb21ldGhpbmcgd2hpY2ggaXMgYQpETUEgYWRkcmVzcyBh biBub3QgZm9jaWJseSBhIHBoeXNpY2FsIGFkZHJlc3MuCgo+ICsJCQlkbWFfdW5tYXBfc2luZ2xl KCZoY2ktPm1hc3Rlci5kZXYsIHJoLT5pYmlfZGF0YV9waHlzLAo+ICsJCQkJCSByaC0+aWJpX2No dW5rX3N6ICogcmgtPmliaV9jaHVua3NfdG90YWwsCj4gKwkJCQkJIERNQV9GUk9NX0RFVklDRSk7 Cj4gKwkJa2ZyZWUocmgtPmliaV9kYXRhKTsKPiArCX0KPiArCj4gKwlyaHNfcmVnX3dyaXRlKENP TlRST0wsIDApOwo+ICsKPiArCWtmcmVlKHJpbmdzKTsKPiArCWhjaS0+aW9fZGF0YSA9IE5VTEw7 Cj4gK30KClsuLi5dCgo+ICtzdGF0aWMgYm9vbCBoY2lfZG1hX2RlcXVldWVfeGZlcihzdHJ1Y3Qg aTNjX2hjaSAqaGNpLAo+ICsJCQkJIHN0cnVjdCBoY2lfeGZlciAqeGZlcl9saXN0LCBpbnQgbikK PiArewo+ICsJc3RydWN0IGhjaV9yaW5nc19kYXRhICpyaW5ncyA9IGhjaS0+aW9fZGF0YTsKPiAr CXN0cnVjdCBoY2lfcmhfZGF0YSAqcmggPSAmcmluZ3MtPmhlYWRlcnNbeGZlcl9saXN0WzBdLnJp bmddOwo+ICsJdV9pbnQgaTsKPiArCWJvb2wgZGlkX3VucXVldWUgPSBmYWxzZTsKPiArCj4gKwkv KiBzdG9wIHRoZSByaW5nICovCj4gKwlyaF9yZWdfd3JpdGUoUklOR19DT05UUk9MLCBSSU5HX0NU UkxfQUJPUlQpOwo+ICsJaWYgKHdhaXRfZm9yX2NvbXBsZXRpb25fdGltZW91dCgmcmgtPm9wX2Rv bmUsIEhaKSA9PSAwKSB7Cj4gKwkJLyoKPiArCQkgKiBXZSdyZSBkZWVwIGluIGl0IGlmIGV2ZXIg dGhpcyBjb25kaXRpb24gaXMgZXZlciBtZXQuCj4gKwkJICogSGFyZHdhcmUgbWlnaHQgc3RpbGwg YmUgd3JpdGluZyB0byBtZW1vcnksIGV0Yy4KPiArCQkgKi8KPiArCQlFUlIoInVuYWJsZSB0byBh Ym9ydCB0aGUgcmluZyIpOwo+ICsJCUJVRygpOwoKV2h5IG5vdCBqdXN0IHRyZWF0aW5nIHRoZSBl cnJvciBhcyBhbHdheXM/Cgo+ICsJfQo+ICsKPiArCWZvciAoaSA9IDA7IGkgPCBuOyBpKyspIHsK PiArCQlzdHJ1Y3QgaGNpX3hmZXIgKnhmZXIgPSB4ZmVyX2xpc3QgKyBpOwo+ICsJCWludCBpZHgg PSB4ZmVyLT5yaW5nX2VudHJ5Owo+ICsKPiArCQkvKgo+ICsJCSAqIEF0IHRoZSB0aW1lIHRoZSBh Ym9ydCBoYXBwZW5lZCwgdGhlIHhmZXIgbWlnaHQgaGF2ZQo+ICsJCSAqIGNvbXBsZXRlZCBhbHJl YWR5LiBJZiBub3QgdGhlbiByZXBsYWNlIGNvcnJlc3BvbmRpbmcKPiArCQkgKiBkZXNjcmlwdG9y IGVudHJpZXMgd2l0aCBhIG5vLW9wLgo+ICsJCSAqLwo+ICsJCWlmIChpZHggPj0gMCkgewo+ICsJ CQl1MzIgKnJpbmdfZGF0YSA9IHJoLT54ZmVyICsgcmgtPnhmZXJfc3RydWN0X3N6ICogaWR4Owo+ ICsKPiArCQkJLyogc3RvcmUgbm8tb3AgY21kIGRlc2NyaXB0b3IgKi8KPiArCQkJKnJpbmdfZGF0 YSsrID0gRklFTERfUFJFUChDTURfMF9BVFRSLCAweDcpOwo+ICsJCQkqcmluZ19kYXRhKysgPSAw Owo+ICsJCQlpZiAoaGNpLT5jbWQgPT0gJmkzY19oY2lfY21kX3YyKSB7Cj4gKwkJCQkqcmluZ19k YXRhKysgPSAwOwo+ICsJCQkJKnJpbmdfZGF0YSsrID0gMDsKPiArCQkJfQo+ICsKPiArCQkJLyog ZGlzYXNzb2NpYXRlIHRoaXMgeGZlciBzdHJ1Y3QgKi8KPiArCQkJcmgtPnNyY194ZmVyc1tpZHhd ID0gTlVMTDsKPiArCj4gKwkJCS8qIGFuZCB1bm1hcCBpdCAqLwo+ICsJCQloY2lfZG1hX3VubWFw X3hmZXIoaGNpLCB4ZmVyLCAxKTsKPiArCj4gKwkJCWRpZF91bnF1ZXVlID0gdHJ1ZTsKPiArCQl9 Cj4gKwl9Cj4gKwo+ICsJLyogcmVzdGFydCB0aGUgcmluZyAqLwo+ICsJcmhfcmVnX3dyaXRlKFJJ TkdfQ09OVFJPTCwgUklOR19DVFJMX0VOQUJMRSk7Cj4gKwo+ICsJcmV0dXJuIGRpZF91bnF1ZXVl Owo+ICt9CgpbLi4uXQoKPiArLyoKPiArICogU3RydWN0dXJlIHRvIHJlcHJlc2VudCBhIG1hc3Rl ciBpbml0aWF0ZWQgdHJhbnNmZXIuCj4gKyAqIFRoZSBybncsIGRhdGEgYW5kIGRhdGFfbGVuIGZp ZWxkcyBtdXN0IGJlIGluaXRpYWxpemVkIGJlZm9yZSBjYWxsaW5nIGFueQo+ICsgKiBoY2ktPmNt ZC0+KigpIG1ldGhvZC4gVGhlIGNtZCBtZXRob2Qgd2lsbCBpbml0aWFsaXplIGNtZF9kZXNjW10g YW5kCj4gKyAqIHBvc3NpYmx5IG1vZGlmeSAoY2xlYXIpIHRoZSBkYXRhIGZpZWxkLiBUaGVuIHhm ZXItPmNtZF9kZXNjWzBdIGNhbgo+ICsgKiBiZSBhdWdtZW50ZWQgd2l0aCBDTURfMF9ST0MgYW5k L29yIENNRF8wX1RPQy4KPiArICogVGhlIGNvbXBsZXRpb24gZmllbGQgbmVlZHMgdG8gYmUgaW5p dGlhbGl6ZWQgYmVmb3JlIHF1ZXVlaW5nIHdpdGgKPiArICogaGNpLT5pby0+cXVldWVfeGZlcigp LCBhbmQgcmVxdWlyZXMgQ01EXzBfUk9DIHRvIGJlIHNldC4KPiArICovCj4gK3N0cnVjdCBoY2lf eGZlciB7Cj4gKwl1MzIgY21kX2Rlc2NbNF07Cj4gKwl1MzIgcmVzcG9uc2U7Cj4gKwlib29sIHJu dzsKPiArCXZvaWQgKmRhdGE7Cj4gKwl1X2ludCBkYXRhX2xlbjsKPiArCXVfaW50IGNtZF90aWQ7 Cj4gKwlzdHJ1Y3QgY29tcGxldGlvbiAqY29tcGxldGlvbjsKPiArCXVuaW9uIHsKPiArCQlzdHJ1 Y3Qgewo+ICsJCQkvKiBQSU8gc3BlY2lmaWMgKi8KPiArCQkJc3RydWN0IGhjaV94ZmVyICpuZXh0 X3hmZXI7Cj4gKwkJCXN0cnVjdCBoY2lfeGZlciAqbmV4dF9kYXRhOwo+ICsJCQlzdHJ1Y3QgaGNp X3hmZXIgKm5leHRfcmVzcDsKPiArCQkJdV9pbnQgZGF0YV9sZWZ0Owo+ICsJCQl1MzIgZGF0YV93 b3JkX2JlZm9yZV9wYXJ0aWFsOwo+ICsJCX07CgpJIHRoaW5rIGFub255bW91cyB1bmlvbnMgYXJl IHByb2hpYml0ZWQgYmVjYXVzZSB0aGUga2VybmVsIGlzIHN1cHBvc2VkCnRvIGJlIGJ1aWx0IHdp dGggb2xkIGdjYyB2ZXJzaW9ucyB3aGljaCBkbyBub3Qgc3VwcG9ydCBpdC4KCj4gKwkJc3RydWN0 IHsKPiArCQkJLyogRE1BIHNwZWNpZmljICovCj4gKwkJCWRtYV9hZGRyX3QgZGF0YV9waHlzOwo+ ICsJCQl1X2ludCByaW5nOwo+ICsJCQlpbnQgcmluZ19lbnRyeTsKPiArCQl9Owo+ICsJfTsKPiAr fTsKPiArCj4gK3N0YXRpYyBpbmxpbmUgc3RydWN0IGhjaV94ZmVyICpoY2lfYWxsb2NfeGZlcih1 X2ludCBuKQo+ICt7Cj4gKwlyZXR1cm4ga3phbGxvYyhzaXplb2Yoc3RydWN0IGhjaV94ZmVyKSAq IG4sIEdGUF9LRVJORUwpOwo+ICt9Cj4gKwo+ICtzdGF0aWMgaW5saW5lIHZvaWQgaGNpX2ZyZWVf eGZlcihzdHJ1Y3QgaGNpX3hmZXIgKnhmZXIsIHVfaW50IG4pCj4gK3sKPiArCWtmcmVlKHhmZXIp Owo+ICt9Cj4gKwo+ICsKCgpUaGFua3MsCk1pcXXDqGwKCi0tIApsaW51eC1pM2MgbWFpbGluZyBs aXN0CmxpbnV4LWkzY0BsaXN0cy5pbmZyYWRlYWQub3JnCmh0dHA6Ly9saXN0cy5pbmZyYWRlYWQu b3JnL21haWxtYW4vbGlzdGluZm8vbGludXgtaTNjCg== From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-11.2 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_SANE_2 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 54967C433E1 for ; Thu, 20 Aug 2020 08:09:33 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 27EB12080C for ; Thu, 20 Aug 2020 08:09:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725834AbgHTIJG convert rfc822-to-8bit (ORCPT ); Thu, 20 Aug 2020 04:09:06 -0400 Received: from relay7-d.mail.gandi.net ([217.70.183.200]:43255 "EHLO relay7-d.mail.gandi.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726664AbgHTIIh (ORCPT ); Thu, 20 Aug 2020 04:08:37 -0400 X-Originating-IP: 91.224.148.103 Received: from xps13 (unknown [91.224.148.103]) (Authenticated sender: miquel.raynal@bootlin.com) by relay7-d.mail.gandi.net (Postfix) with ESMTPSA id 5F85520006; Thu, 20 Aug 2020 08:08:30 +0000 (UTC) Date: Thu, 20 Aug 2020 10:08:29 +0200 From: Miquel Raynal To: Nicolas Pitre Cc: Boris Brezillon , linux-i3c@lists.infradead.org, devicetree@vger.kernel.org, Laura Nixon , Robert Gough , Rob Herring , Matthew Schnoor , Nicolas Pitre Subject: Re: [PATCH 2/2] i3c/master: add the mipi-i3c-hci driver Message-ID: <20200820100829.0e44200a@xps13> In-Reply-To: <20200814034854.460830-3-nico@fluxnic.net> References: <20200814034854.460830-1-nico@fluxnic.net> <20200814034854.460830-3-nico@fluxnic.net> Organization: Bootlin X-Mailer: Claws Mail 3.17.4 (GTK+ 2.24.32; x86_64-pc-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8BIT Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Hi Nicolas, Nicolas Pitre wrote on Thu, 13 Aug 2020 23:48:54 -0400: > From: Nicolas Pitre > > This adds basic support for hardware implementing the MIPI I3C HCI > specification. This driver is currently limited by the capabilities > of the I3C subsystem, meaning things like scheduled commands, > auto-commands and NCM are not yet supported. > > This supports version 1.0 of the MIPI I3C HCI spec, as well as the > imminent release of version 1.1. Support for draft version 2.0 of the > spec is also partially included but is guaranteed to change as the spec > is still a work in progress. > > This is also lightly tested as actual hardware is still very scarse, > even for HCI v1.0. Further contributions to this driver are expected > once vendor implementations and new I3C devices become available. Nice work! I honnestly do not know a lot about HCIs and I basically had only minor nits to point out, see below. > > Signed-off-by: Nicolas Pitre > --- > drivers/i3c/master/Kconfig | 13 + > drivers/i3c/master/Makefile | 1 + > drivers/i3c/master/mipi-i3c-hci/Makefile | 9 + > drivers/i3c/master/mipi-i3c-hci/cmd.h | 106 +++ > drivers/i3c/master/mipi-i3c-hci/cmd_v1.c | 362 ++++++++ > drivers/i3c/master/mipi-i3c-hci/cmd_v2.c | 280 ++++++ > drivers/i3c/master/mipi-i3c-hci/core.c | 801 +++++++++++++++++ > drivers/i3c/master/mipi-i3c-hci/dat.h | 28 + > drivers/i3c/master/mipi-i3c-hci/dat_v1.c | 170 ++++ > drivers/i3c/master/mipi-i3c-hci/dct.h | 16 + > drivers/i3c/master/mipi-i3c-hci/dct_v1.c | 36 + > drivers/i3c/master/mipi-i3c-hci/debug.c | 79 ++ > drivers/i3c/master/mipi-i3c-hci/debug.h | 17 + > drivers/i3c/master/mipi-i3c-hci/dma.c | 767 ++++++++++++++++ > drivers/i3c/master/mipi-i3c-hci/ext_caps.c | 249 ++++++ > drivers/i3c/master/mipi-i3c-hci/ext_caps.h | 19 + > drivers/i3c/master/mipi-i3c-hci/hci.h | 150 ++++ > drivers/i3c/master/mipi-i3c-hci/ibi.h | 42 + > drivers/i3c/master/mipi-i3c-hci/pio.c | 961 +++++++++++++++++++++ > 19 files changed, 4106 insertions(+) > create mode 100644 drivers/i3c/master/mipi-i3c-hci/Makefile > create mode 100644 drivers/i3c/master/mipi-i3c-hci/cmd.h > create mode 100644 drivers/i3c/master/mipi-i3c-hci/cmd_v1.c > create mode 100644 drivers/i3c/master/mipi-i3c-hci/cmd_v2.c > create mode 100644 drivers/i3c/master/mipi-i3c-hci/core.c > create mode 100644 drivers/i3c/master/mipi-i3c-hci/dat.h > create mode 100644 drivers/i3c/master/mipi-i3c-hci/dat_v1.c > create mode 100644 drivers/i3c/master/mipi-i3c-hci/dct.h > create mode 100644 drivers/i3c/master/mipi-i3c-hci/dct_v1.c > create mode 100644 drivers/i3c/master/mipi-i3c-hci/debug.c > create mode 100644 drivers/i3c/master/mipi-i3c-hci/debug.h > create mode 100644 drivers/i3c/master/mipi-i3c-hci/dma.c > create mode 100644 drivers/i3c/master/mipi-i3c-hci/ext_caps.c > create mode 100644 drivers/i3c/master/mipi-i3c-hci/ext_caps.h > create mode 100644 drivers/i3c/master/mipi-i3c-hci/hci.h > create mode 100644 drivers/i3c/master/mipi-i3c-hci/ibi.h > create mode 100644 drivers/i3c/master/mipi-i3c-hci/pio.c > > diff --git a/drivers/i3c/master/Kconfig b/drivers/i3c/master/Kconfig > index 4e80a1fcbf..eb5830923f 100644 > --- a/drivers/i3c/master/Kconfig > +++ b/drivers/i3c/master/Kconfig > @@ -21,3 +21,16 @@ config DW_I3C_MASTER > > This driver can also be built as a module. If so, the module > will be called dw-i3c-master. > + > +config MIPI_I3C_HCI > + tristate "MIPI I3C Host Controller Interface driver" > + depends on I3C > + help > + Support for hardware following the MIPI Aliance's I3C Host Controller > + Interface specification. > + > + For details please see: > + https://www.mipi.org/specifications/i3c-hci > + > + This driver can also be built as a module. If so, the module will be > + called mipi-i3c-hci. > diff --git a/drivers/i3c/master/Makefile b/drivers/i3c/master/Makefile > index 7eea9e0861..b892fd4caf 100644 > --- a/drivers/i3c/master/Makefile > +++ b/drivers/i3c/master/Makefile > @@ -1,3 +1,4 @@ > # SPDX-License-Identifier: GPL-2.0-only > obj-$(CONFIG_CDNS_I3C_MASTER) += i3c-master-cdns.o > obj-$(CONFIG_DW_I3C_MASTER) += dw-i3c-master.o > +obj-$(CONFIG_MIPI_I3C_HCI) += mipi-i3c-hci/ > diff --git a/drivers/i3c/master/mipi-i3c-hci/Makefile b/drivers/i3c/master/mipi-i3c-hci/Makefile > new file mode 100644 > index 0000000000..8349960c5b > --- /dev/null > +++ b/drivers/i3c/master/mipi-i3c-hci/Makefile > @@ -0,0 +1,9 @@ > +# SPDX-License-Identifier: BSD-3-Clause Just out of curiosity, why this license? > + > +#ccflags-y := -DDEBUG Probably a leftover? > + > +obj-$(CONFIG_MIPI_I3C_HCI) += mipi-i3c-hci.o > +mipi-i3c-hci-y := core.o ext_caps.o pio.o dma.o \ > + cmd_v1.o cmd_v2.o \ > + dat_v1.o dct_v1.o \ > + debug.o [...] > +#define CMD_C1_DATA_LENGTH(v) FIELD_PREP(W1_MASK(63, 48), v) > +#define CMD_C1_OFFSET(v) FIELD_PREP(W1_MASK(47, 32), v) > +#define CMD_C0_TOC W0_BIT_(31) > +#define CMD_C0_ROC W0_BIT_(30) > +#define CMD_C0_RNW W0_BIT_(29) > +#define CMD_C0_MODE(v) FIELD_PREP(W0_MASK(28, 26), v) > +#define CMD_C0_16_BIT_SUBOFFSET W0_bit(25) > +#define CMD_C0_FIRST_PHASE_MODE W0_BIT_(24) > +#define CMD_C0_DATA_LENGTH_POSITION(v) FIELD_PREP(W0_MASK(23, 22), v) > +#define CMD_C0_DEV_INDEX(v) FIELD_PREP(W0_MASK(20, 16), v) > +#define CMD_C0_CP W0_BIT_(15) > +#define CMD_C0_CMD(v) FIELD_PREP(W0_MASK(14, 7), v) > +#define CMD_C0_TID(v) FIELD_PREP(W0_MASK(6, 3), v) > + > +/* > + * Internal Control Command > + */ > + > +#define CMD_0_ATTR_M FIELD_PREP(CMD_0_ATTR, 0x7) > + > +#define CMD_M1_VENDOR_SPECIFIC W1_MASK(63, 32) > +#define CMD_M0_MIPI_RESERVED W0_MASK(31, 12) > +#define CMD_M0_MIPI_CMD W0_MASK(11, 8) > +#define CMD_M0_VENDOR_INFO_PRESENT W0_BIT_(7) > +#define CMD_M0_TID(v) FIELD_PREP(W0_MASK(6, 3), v) > + > + > +static int hci_cmd_v1_prep_ccc(struct i3c_hci *hci, > + struct hci_xfer *xfer, > + u8 ccc_addr, u8 ccc_cmd, bool raw) > +{ > + u_int dat_idx = 0; I guess u_int her and below is not the preferred way to declare an unsigned int? > + int mode = hci_get_i3c_mode(hci); > + u8 *data = xfer->data; > + u_int data_len = xfer->data_len; > + bool rnw = xfer->rnw; > + int ret; > + > + BUG_ON(raw); It looks like 'raw' cannot be used with v1 (at least you seem to take care of it in v2), so maybe BUG_ON is a bit radical here and you can simply return an error? I think the use of BUG() is not appreciated in general. > + > + if (ccc_addr != I3C_BROADCAST_ADDR) { > + ret = i3c_hci_dat_get_index(hci, ccc_addr); > + if (ret < 0) > + return -ENODEV; > + dat_idx = ret; > + } > + > + xfer->cmd_tid = hci_get_tid(4); > + > + if (!rnw && data_len <= 4) { > + /* we use an Immediate Data Transfer Command */ > + xfer->cmd_desc[0] = > + CMD_0_ATTR_I | > + CMD_I0_TID(xfer->cmd_tid) | > + CMD_I0_CMD(ccc_cmd) | CMD_I0_CP | > + CMD_I0_DEV_INDEX(dat_idx) | > + CMD_I0_DTT(data_len) | > + CMD_I0_MODE(mode); > + xfer->cmd_desc[1] = 0; > + switch (data_len) { > + case 4: > + xfer->cmd_desc[1] |= CMD_I1_DATA_BYTE_4(data[3]); > + fallthrough; > + case 3: > + xfer->cmd_desc[1] |= CMD_I1_DATA_BYTE_3(data[2]); > + fallthrough; > + case 2: > + xfer->cmd_desc[1] |= CMD_I1_DATA_BYTE_2(data[1]); > + fallthrough; > + case 1: > + xfer->cmd_desc[1] |= CMD_I1_DATA_BYTE_1(data[0]); > + fallthrough; > + case 0: > + break; > + } > + /* we consumed all the data in the cmd descriptor */ > + xfer->data = NULL; > + } else { > + /* we use a Regular Data Transfer Command */ > + xfer->cmd_desc[0] = > + CMD_0_ATTR_R | > + CMD_R0_TID(xfer->cmd_tid) | > + CMD_R0_CMD(ccc_cmd) | CMD_R0_CP | > + CMD_R0_DEV_INDEX(dat_idx) | > + CMD_R0_MODE(mode) | > + (rnw ? CMD_R0_RNW : 0); > + xfer->cmd_desc[1] = > + CMD_R1_DATA_LENGTH(data_len); > + } > + > + return 0; > +} [...] > +static int hci_cmd_v1_daa(struct i3c_hci *hci) > +{ > + struct hci_xfer *xfer; > + int ret, dat_idx = -1; > + u8 next_addr; > + u64 pid; > + u_int dcr, bcr; > + DECLARE_COMPLETION_ONSTACK(done); > + > + xfer = hci_alloc_xfer(2); > + if (!xfer) > + return -ENOMEM; > + > + /* > + * Simple for now: we allocate a temporary DAT entry, do a single > + * DAA, register the device which will allocate its own DAT entry > + * via the core callback, then free the temporary DAT entry. > + * Loop until there is no more devices to assign an address to. > + * Yes, there is room for improvements. > + */ > + for (;;) { > + ret = i3c_hci_dat_alloc_entry(hci); > + if (ret < 0) > + break; > + dat_idx = ret; > + ret = i3c_master_get_free_addr(&hci->master, next_addr); > + if (ret < 0) > + break; > + next_addr = ret; > + > + DBG("next_addr = 0x%02x, DAA using DAT %d", next_addr, dat_idx); > + i3c_hci_dat_set_dynamic_addr(hci, dat_idx, next_addr); > + i3c_hci_dct_index_reset(hci); > + > + xfer->cmd_tid = hci_get_tid(4); > + xfer->cmd_desc[0] = > + CMD_0_ATTR_A | > + CMD_A0_TID(xfer->cmd_tid) | > + CMD_A0_CMD(I3C_CCC_ENTDAA) | > + CMD_A0_DEV_INDEX(dat_idx) | > + CMD_A0_DEV_COUNT(1) | > + CMD_A0_ROC | CMD_A0_TOC; > + xfer->cmd_desc[1] = 0; > + hci->io->queue_xfer(hci, xfer, 1); > + if (!wait_for_completion_timeout(&done, HZ) && > + hci->io->dequeue_xfer(hci, xfer, 1)) { > + ret = -ETIME; > + break; > + } > + if (RESP_STATUS(xfer[0].response) == RESP_ERR_NACK && > + RESP_STATUS(xfer[0].response) == 1) { > + ret = 0; /* no more devices to be assigned */ > + break; > + } > + if (RESP_STATUS(xfer[0].response) != RESP_SUCCESS) { > + ret = -EIO; > + break; > + } > + > + i3c_hci_dct_get_val(hci, 0, &pid, &dcr, &bcr); > + DBG("assigned address %#x to device PID=0x%llx DCR=%#x BCR=%#x", > + next_addr, pid, dcr, bcr); > + > + i3c_hci_dat_free_entry(hci, dat_idx); > + dat_idx = -1; > + > + /* > + * TODO: Extend the subsystem layer to allow for registering > + * new device and provide BCR/DCR/PID at the same time. Not sure this is needed if you don't use it directly as the core will anyway (in its current form) send the relevant CCC to read these registers. > + */ > + ret = i3c_master_add_i3c_dev_locked(&hci->master, next_addr); > + if (ret) > + break; > + } > + > + if (dat_idx >= 0) > + i3c_hci_dat_free_entry(hci, dat_idx); > + hci_free_xfer(xfer, 1); > + return ret; > +} > + > +const struct hci_cmd_ops i3c_hci_cmd_v1 = { > + .prep_ccc = hci_cmd_v1_prep_ccc, > + .prep_i3c_xfer = hci_cmd_v1_prep_i3c_xfer, > + .prep_i2c_xfer = hci_cmd_v1_prep_i2c_xfer, > + .perform_daa = hci_cmd_v1_daa, I know Boris does not like such space alignment :) > +}; [...] > +void i3c_hci_resume(struct i3c_hci *hci) > +{ > + /* the HC_CONTROL_RESUME bit is R/W1C so just read and write back */ > + reg_write(HC_CONTROL, reg_read(HC_CONTROL)); > +} > + > +/* located here rather than pio.c because needed bits are in core reg space */ > +void i3c_hci_pio_reset(struct i3c_hci *hci) > +{ > + reg_write(RESET_CONTROL, RX_FIFO_RST|TX_FIFO_RST|RESP_QUEUE_RST); Style with missing spaces ^ ^ > +} > + > +/* located here rather than dct.c because needed bits are in core reg space */ > +void i3c_hci_dct_index_reset(struct i3c_hci *hci) > +{ > + reg_write(DCT_SECTION_OFFSET, FIELD_PREP(DCT_TABLE_INDEX, 0)); > +} > + > +static int i3c_hci_send_ccc_cmd(struct i3c_master_controller *m, > + struct i3c_ccc_cmd *ccc) > +{ > + struct i3c_hci *hci = to_i3c_hci(m); > + struct hci_xfer *xfer; > + bool raw = !!(hci->quirks & HCI_QUIRK_RAW_CCC); > + bool prefixed = raw && !!(ccc->id & I3C_CCC_DIRECT); > + u_int nxfers = ccc->ndests + prefixed; > + DECLARE_COMPLETION_ONSTACK(done); > + int i, last, ret = 0; > + > + DBG("cmd=%#x rnw=%d ndests=%d data[0].len=%d", > + ccc->id, ccc->rnw, ccc->ndests, ccc->dests[0].payload.len); > + > + xfer = hci_alloc_xfer(nxfers); > + if (!xfer) > + return -ENOMEM; > + > + if (prefixed) { > + xfer->data = NULL; > + xfer->data_len = 0; > + xfer->rnw = false; > + hci->cmd->prep_ccc(hci, xfer, I3C_BROADCAST_ADDR, > + ccc->id, true); > + xfer++; > + } > + > + for (i = 0; i < nxfers - prefixed; i++) { > + xfer[i].data = ccc->dests[i].payload.data; > + xfer[i].data_len = ccc->dests[i].payload.len; > + xfer[i].rnw = ccc->rnw; > + ret = hci->cmd->prep_ccc(hci, &xfer[i], ccc->dests[i].addr, > + ccc->id, raw); > + if (ret) > + goto out; > + xfer[i].cmd_desc[0] |= CMD_0_ROC; > + } > + last = i - 1; > + xfer[last].cmd_desc[0] |= CMD_0_TOC; > + xfer[last].completion = &done; > + > + if (prefixed) > + xfer--; > + > + ret = hci->io->queue_xfer(hci, xfer, nxfers); > + if (ret) > + goto out; > + if (!wait_for_completion_timeout(&done, HZ) && > + hci->io->dequeue_xfer(hci, xfer, nxfers)) { > + ret = -ETIME; > + goto out; > + } > + for (i = prefixed; i < nxfers; i++) { > + if (ccc->rnw) > + ccc->dests[i - prefixed].payload.len = > + RESP_DATA_LENGTH(xfer[i].response); > + if (RESP_STATUS(xfer[i].response) != RESP_SUCCESS) { > + ret = -EIO; > + goto out; > + } > + } > + > +#if 0 > + if (ccc->rnw) { > + HEXDUMP("got: ", ccc->dests[0].payload.data, > + ccc->dests[0].payload.len); > + } > +#endif I guess this debug block can be dropped too (there are many debug information the should probably be dropped or turned into dev_info() or similar). > + > +out: > + hci_free_xfer(xfer, nxfers); > + return ret; > +} > + > +static int i3c_hci_daa(struct i3c_master_controller *m) > +{ > + struct i3c_hci *hci = to_i3c_hci(m); > + > + DBG(""); > + > + return hci->cmd->perform_daa(hci); > +} [...] > diff --git a/drivers/i3c/master/mipi-i3c-hci/debug.c b/drivers/i3c/master/mipi-i3c-hci/debug.c > new file mode 100644 > index 0000000000..3885499119 > --- /dev/null > +++ b/drivers/i3c/master/mipi-i3c-hci/debug.c > @@ -0,0 +1,79 @@ > +// SPDX-License-Identifier: BSD-3-Clause > +/* > + * Copyright (c) 2020, MIPI Alliance, Inc. > + * > + * Author: Nicolas Pitre > + */ > + > +#include > +#include > +#include > +#include > + > +#include "hci.h" > +#include "debug.h" > + > +/* > + * Paul Kimelman's debug trace log facility. > + * This is completely vendor and hardware specific. > + */ > +void __PK_debug_trace(struct i3c_hci *hci, const char *func) > +{ > + void __iomem *trcp = (void __iomem *)hci->vendor_data + 7*4; Maybe you need to define what is 7*4 , 0*4 below, v >> 27, etc Also there are many missing spaces between operators (7 * 4,w & (1 <<9). > + uint32_t idx, cycles, match; > + uint32_t trace_full = 1; > + > + if (!hci->vendor_data) > + return; > + > + idx = readl(trcp + 0*4); > + cycles = idx>>16; > + idx &= 0xFFFF; > + if (idx > 0xFFF) { > + pr_info("Trace count=%d, stored=%d; cycles=%d\n", idx, 0xFFF, cycles); > + match = (idx-1) & 0xFFF; > + } else { > + pr_info("Trace count=%d; cycles=%d\n", idx, cycles); > + match = idx; > + idx = 0; > + } > + > + writel(idx | (trace_full << 31), trcp + 1*4); // 1st to read > + for (; idx != match; idx = (idx+1)&0xFFF) { // ring through it > + uint32_t v = readl(trcp + 1*4); // get trace word > + uint32_t up = trace_full ? readl(trcp + 1*4) : 0; > + char *e2 = (v&(1<<9))?"/NACK":""; > + char *e3 = (v&(1<<10))?"/WRABT":""; > + char *e4 = (v&(1<<11))?"/TERM":""; > + char *e5 = (v & (1<<7)) ? "/INVREQ" : ""; > + char *e6 = (v & (1<<8)) ? "/TIMEOUT" : ""; > + if (trace_full) { > + uint32_t cmd = up >> 16; > + pr_info("%-5d: ", up & 0xFFFF); > + if (cmd) > + pr_info("cmd=%s tid=%02X, TOC=%d, ROC=%d, %s %s addr=%X\n---", > + (cmd & (1<<2)) ? "Cmd" : "DAA", > + (cmd >> 3) & 0xF, cmd >> 31, (cmd >> 30) & 1, > + ((cmd >> 7) & 1) ? "I2C" : "I3C", > + (cmd & (1<<8))?"Read ":"Write", > + (cmd >> 9) & 0x7F); > + else > + pr_cont("\n----"); > + } else > + pr_info("%08X: ", v); > + pr_cont("#%3X: st=%03X,status=%02X%s%s%s%s%s%s%s%s%s%s%s%s\n", idx, > + v & 0x7F, (v >> 12) & 0xFFF, ((v >> 24) & 1) ? ", clrs" : "", > + ((v >> 25) & 1) ? ", ERROR" : "", e2, e3, e4, e5, e6, > + ((v >> 26) & 1) ? ",clre" : "", ((v >> 27) & 1) ? ", NACK" : "", > + ((v >> 28) & 1) ? ", IN_DAA" : "", > + ((v >> 29) & 1) ? ", IRQ" : "", ((v >> 30) & 1) ? ", cRSP" : ""); > + } > + // clear trace index so can tell when we have new ones > + writel(0, trcp + 0*4); > +} [...] > +static void hci_dma_cleanup(struct i3c_hci *hci) > +{ > + struct hci_rings_data *rings = hci->io_data; > + struct hci_rh_data *rh; > + u_int i; > + > + if (!rings) > + return; > + > + for (i = 0; i < rings->total; i++) { > + rh = &rings->headers[i]; > + > + rh_reg_write(RING_CONTROL, 0); > + rh_reg_write(CR_SETUP, 0); > + rh_reg_write(IBI_SETUP, 0); > + rh_reg_write(INTR_SIGNAL_ENABLE, 0); > + > + if (rh->xfer) > + dma_free_coherent(&hci->master.dev, > + rh->xfer_struct_sz * rh->xfer_entries, > + rh->xfer, rh->xfer_phys); > + if (rh->resp) > + dma_free_coherent(&hci->master.dev, > + rh->resp_struct_sz * rh->xfer_entries, > + rh->resp, rh->resp_phys); > + kfree(rh->src_xfers); > + if (rh->ibi_status) > + dma_free_coherent(&hci->master.dev, > + rh->ibi_status_sz * rh->ibi_status_entries, > + rh->ibi_status, rh->ibi_status_phys); > + if (rh->ibi_data_phys) I was told that _phys was a very bad suffix for something which is a DMA address an not focibly a physical address. > + dma_unmap_single(&hci->master.dev, rh->ibi_data_phys, > + rh->ibi_chunk_sz * rh->ibi_chunks_total, > + DMA_FROM_DEVICE); > + kfree(rh->ibi_data); > + } > + > + rhs_reg_write(CONTROL, 0); > + > + kfree(rings); > + hci->io_data = NULL; > +} [...] > +static bool hci_dma_dequeue_xfer(struct i3c_hci *hci, > + struct hci_xfer *xfer_list, int n) > +{ > + struct hci_rings_data *rings = hci->io_data; > + struct hci_rh_data *rh = &rings->headers[xfer_list[0].ring]; > + u_int i; > + bool did_unqueue = false; > + > + /* stop the ring */ > + rh_reg_write(RING_CONTROL, RING_CTRL_ABORT); > + if (wait_for_completion_timeout(&rh->op_done, HZ) == 0) { > + /* > + * We're deep in it if ever this condition is ever met. > + * Hardware might still be writing to memory, etc. > + */ > + ERR("unable to abort the ring"); > + BUG(); Why not just treating the error as always? > + } > + > + for (i = 0; i < n; i++) { > + struct hci_xfer *xfer = xfer_list + i; > + int idx = xfer->ring_entry; > + > + /* > + * At the time the abort happened, the xfer might have > + * completed already. If not then replace corresponding > + * descriptor entries with a no-op. > + */ > + if (idx >= 0) { > + u32 *ring_data = rh->xfer + rh->xfer_struct_sz * idx; > + > + /* store no-op cmd descriptor */ > + *ring_data++ = FIELD_PREP(CMD_0_ATTR, 0x7); > + *ring_data++ = 0; > + if (hci->cmd == &i3c_hci_cmd_v2) { > + *ring_data++ = 0; > + *ring_data++ = 0; > + } > + > + /* disassociate this xfer struct */ > + rh->src_xfers[idx] = NULL; > + > + /* and unmap it */ > + hci_dma_unmap_xfer(hci, xfer, 1); > + > + did_unqueue = true; > + } > + } > + > + /* restart the ring */ > + rh_reg_write(RING_CONTROL, RING_CTRL_ENABLE); > + > + return did_unqueue; > +} [...] > +/* > + * Structure to represent a master initiated transfer. > + * The rnw, data and data_len fields must be initialized before calling any > + * hci->cmd->*() method. The cmd method will initialize cmd_desc[] and > + * possibly modify (clear) the data field. Then xfer->cmd_desc[0] can > + * be augmented with CMD_0_ROC and/or CMD_0_TOC. > + * The completion field needs to be initialized before queueing with > + * hci->io->queue_xfer(), and requires CMD_0_ROC to be set. > + */ > +struct hci_xfer { > + u32 cmd_desc[4]; > + u32 response; > + bool rnw; > + void *data; > + u_int data_len; > + u_int cmd_tid; > + struct completion *completion; > + union { > + struct { > + /* PIO specific */ > + struct hci_xfer *next_xfer; > + struct hci_xfer *next_data; > + struct hci_xfer *next_resp; > + u_int data_left; > + u32 data_word_before_partial; > + }; I think anonymous unions are prohibited because the kernel is supposed to be built with old gcc versions which do not support it. > + struct { > + /* DMA specific */ > + dma_addr_t data_phys; > + u_int ring; > + int ring_entry; > + }; > + }; > +}; > + > +static inline struct hci_xfer *hci_alloc_xfer(u_int n) > +{ > + return kzalloc(sizeof(struct hci_xfer) * n, GFP_KERNEL); > +} > + > +static inline void hci_free_xfer(struct hci_xfer *xfer, u_int n) > +{ > + kfree(xfer); > +} > + > + Thanks, Miquèl