[Linux-kernel-mentees] [RFC PATCH v5 12/23] PCI: Add ASPM and CLOCK PM states to struct pci_dev

["Saheed O. Bolarinwa" <refactormyself@gmail.com>]

Move all struct pcie_link_state information to struct pci_dev

Signed-off-by: Saheed O. Bolarinwa <refactormyself@gmail.com>
---
 drivers/pci/pcie/aspm.c |  5 -----
 include/linux/pci.h     | 32 ++++++++++++++++++++++++++++++++
 2 files changed, 32 insertions(+), 5 deletions(-)

diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c
index 4cff11dc8d83..d9c17093b250 100644
--- a/drivers/pci/pcie/aspm.c
+++ b/drivers/pci/pcie/aspm.c
@@ -41,11 +41,6 @@
 #define ASPM_STATE_ALL		(ASPM_STATE_L0S | ASPM_STATE_L1 |	\
 				 ASPM_STATE_L1SS)
 
-struct aspm_latency {
-	u32 l0s;			/* L0s latency (nsec) */
-	u32 l1;				/* L1 latency (nsec) */
-};
-
 struct pcie_link_state {
 	struct pci_dev *pdev;		/* Upstream component of the Link */
 	struct pci_dev *downstream;	/* Downstream component, function 0 */
diff --git a/include/linux/pci.h b/include/linux/pci.h
index fa114c5d01e7..1daf5fe0b913 100644
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -305,6 +305,11 @@ struct pci_vpd;
 struct pci_sriov;
 struct pci_p2pdma;
 
+struct aspm_latency {
+	u32 l0s;			/* L0s latency (nsec) */
+	u32 l1;				/* L1 latency (nsec) */
+};
+
 /* The pci_dev structure describes PCI devices */
 struct pci_dev {
 	struct list_head bus_list;	/* Node in per-bus list */
@@ -383,6 +388,33 @@ struct pci_dev {
 					   supported from root to here */
 	int		l1ss_cap_ptr;	/* L1SS cap ptr, 0 if not supported */
 	u32		l1ss_cap;	/* L1 PM substate Capabilities */
+
+	struct pci_dev	*parent;	/* pointer to the parent */
+	struct pci_dev	*root;		/* pointer to the root port */
+	struct pci_dev	*downstream;	/* Downstream component, function 0 */
+	struct list_head sibling;	/* node in link_list */
+
+	/* ASPM state */
+	u32 aspm_support:7;             /* Supported ASPM state */
+	u32 aspm_enabled:7;             /* Enabled ASPM state */
+	u32 aspm_capable:7;             /* Capable ASPM state with latency */
+	u32 aspm_default:7;             /* Default ASPM state by BIOS */
+	u32 aspm_disable:7;             /* Disabled ASPM state */
+
+	/* Clock PM state */
+	u32 clkpm_capable:1;            /* Clock PM capable? */
+	u32 clkpm_enabled:1;            /* Current Clock PM state */
+	u32 clkpm_default:1;            /* Default Clock PM state by BIOS */
+	u32 clkpm_disable:1;            /* Clock PM disabled */
+
+	/* Exit latencies */
+	struct aspm_latency latency_up;	/* Upstream direction exit latency */
+	struct aspm_latency latency_dw;	/* Downstream direction exit latency */
+	/*
+	 * Endpoint acceptable latencies. A pcie downstream port only
+	 * has one slot under it, so at most there are 8 functions.
+	 */
+	struct aspm_latency acceptable[8];
 #endif
 	unsigned int	eetlp_prefix_path:1;	/* End-to-End TLP Prefix */
 
-- 
2.18.4

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