From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-10.1 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1EEDDC433E2 for ; Tue, 1 Sep 2020 03:52:22 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id E0E852083B for ; Tue, 1 Sep 2020 03:52:21 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="dyaEu3K2" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726117AbgIADwV (ORCPT ); Mon, 31 Aug 2020 23:52:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59450 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726105AbgIADwV (ORCPT ); Mon, 31 Aug 2020 23:52:21 -0400 Received: from mail-oo1-xc44.google.com (mail-oo1-xc44.google.com [IPv6:2607:f8b0:4864:20::c44]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CFB60C0612FF for ; Mon, 31 Aug 2020 20:52:20 -0700 (PDT) Received: by mail-oo1-xc44.google.com with SMTP id k63so2020839oob.1 for ; Mon, 31 Aug 2020 20:52:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to; bh=DHgd1Cn7DbLEoeK4tX+vty8BzXm7n6usmD/UeI07Mrk=; b=dyaEu3K2fa7X2g3Iy4XaFmUwFb2VziG9VK8UPB8GwRUXnqKa7ib6yl+CECA0Q1vPLz IjQ+mn612HdIbhc5odg6OfaT3Qb/TYbaI5T/zWIex5gVUoWgirWjKb0AvwZRDaqbzzCO Y1OtNL+0UUlSJmpsQ0sd9QBKMSwBu6kJ5paH3wPa4P9agbIv6yxHgu7afTYDTEwIeYGH DJZ6IsI3RU6NTWK8tqqEnwY3s/hCocMGlybV+ffvg6CgjQt6J50QWplKw+lBIr/ief3F psjjzA+evsRqJDJS9fx7ldrRPcAmxLmEOhyENyNuK+ikFrDogOJS+r6DRfJGytxsSq3x WDZA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=DHgd1Cn7DbLEoeK4tX+vty8BzXm7n6usmD/UeI07Mrk=; b=uMmDzZ5+TmBgExWJnvMrEu/l1DmwKE+Smp8sRpj9e01Qft1zhczedOVtL4L6U/4LhM 7oMPiyC6M72jJ3HPN3eTgUhRf89VrxG78xZjkFheWx1O9K1Ueo5qCFfwhoGjGM45xpgd WHjxH8ecgot92LX3lFIlG5j0wp7LtyTmRIMXnbvRwWWAbxzf8X0HTaUU1HzdD/mGY9sY /UXvqVsAu/p6xX5wUJTJy2R/QJykJvBVFS5sy9PzUq577bBjeob4m6BNmJBCF/3SbIVJ cF8Yg2gJeZFS+8iqdKc2JX3yyich3DVLj0bJgUJCrnCCQXs9y+589tBiazyKtfjMypv3 46OQ== X-Gm-Message-State: AOAM531mQPGlRkqPJAx3e08WiLYlDkPu1A4HtvCnjRqq44Wo7O/MwEcm A0GXF4uP34P/2D4q2jMvdwBNZA== X-Google-Smtp-Source: ABdhPJyW82+oNd0uKsSlubviePmT2U0GHcTQ3RDx78hC9s24SzOxGZRfPqGKe1d6Eg2D6goGkTWR0w== X-Received: by 2002:a4a:aec3:: with SMTP id v3mr2968825oon.69.1598932339869; Mon, 31 Aug 2020 20:52:19 -0700 (PDT) Received: from yoga ([2605:6000:e5cb:c100:8898:14ff:fe6d:34e]) by smtp.gmail.com with ESMTPSA id u19sm2067501oic.10.2020.08.31.20.52.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 31 Aug 2020 20:52:19 -0700 (PDT) Date: Mon, 31 Aug 2020 22:52:16 -0500 From: Bjorn Andersson To: Rob Clark Cc: dri-devel@lists.freedesktop.org, iommu@lists.linux-foundation.org, linux-arm-msm@vger.kernel.org, Sai Prakash Ranjan , Will Deacon , freedreno@lists.freedesktop.org, Sibi Sankar , Vivek Gautam , Stephen Boyd , Robin Murphy , Joerg Roedel , linux-arm-kernel@lists.infradead.org, Rob Clark , open list Subject: Re: [PATCH 05/19] iommu: add private interface for adreno-smmu Message-ID: <20200901035216.GM3715@yoga> References: <20200810222657.1841322-1-jcrouse@codeaurora.org> <20200814024114.1177553-6-robdclark@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20200814024114.1177553-6-robdclark@gmail.com> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On Thu 13 Aug 21:41 CDT 2020, Rob Clark wrote: > From: Rob Clark > > This interface will be used for drm/msm to coordinate with the > qcom_adreno_smmu_impl to enable/disable TTBR0 translation. > > Once TTBR0 translation is enabled, the GPU's CP (Command Processor) > will directly switch TTBR0 pgtables (and do the necessary TLB inv) > synchronized to the GPU's operation. But help from the SMMU driver > is needed to initially bootstrap TTBR0 translation, which cannot be > done from the GPU. > > Since this is a very special case, a private interface is used to > avoid adding highly driver specific things to the public iommu > interface. > > Signed-off-by: Rob Clark Reviewed-by: Bjorn Andersson > --- > include/linux/adreno-smmu-priv.h | 36 ++++++++++++++++++++++++++++++++ > 1 file changed, 36 insertions(+) > create mode 100644 include/linux/adreno-smmu-priv.h > > diff --git a/include/linux/adreno-smmu-priv.h b/include/linux/adreno-smmu-priv.h > new file mode 100644 > index 000000000000..a889f28afb42 > --- /dev/null > +++ b/include/linux/adreno-smmu-priv.h > @@ -0,0 +1,36 @@ > +// SPDX-License-Identifier: GPL-2.0-only > +/* > + * Copyright (C) 2020 Google, Inc > + */ > + > +#ifndef __ADRENO_SMMU_PRIV_H > +#define __ADRENO_SMMU_PRIV_H > + > +#include > + > +/** > + * struct adreno_smmu_priv - private interface between adreno-smmu and GPU > + * > + * @cookie: An opque token provided by adreno-smmu and passed > + * back into the callbacks > + * @get_ttbr1_cfg: Get the TTBR1 config for the GPUs context-bank > + * @set_ttbr0_cfg: Set the TTBR0 config for the GPUs context bank. A > + * NULL config disables TTBR0 translation, otherwise > + * TTBR0 translation is enabled with the specified cfg > + * > + * The GPU driver (drm/msm) and adreno-smmu work together for controlling > + * the GPU's SMMU instance. This is by necessity, as the GPU is directly > + * updating the SMMU for context switches, while on the other hand we do > + * not want to duplicate all of the initial setup logic from arm-smmu. > + * > + * This private interface is used for the two drivers to coordinate. The > + * cookie and callback functions are populated when the GPU driver attaches > + * it's domain. > + */ > +struct adreno_smmu_priv { > + const void *cookie; > + const struct io_pgtable_cfg *(*get_ttbr1_cfg)(const void *cookie); > + int (*set_ttbr0_cfg)(const void *cookie, const struct io_pgtable_cfg *cfg); > +}; > + > +#endif /* __ADRENO_SMMU_PRIV_H */ > \ No newline at end of file > -- > 2.26.2 > From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A25DAC433E2 for ; Tue, 1 Sep 2020 03:57:58 +0000 (UTC) Received: from whitealder.osuosl.org (smtp1.osuosl.org [140.211.166.138]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 6FA782078B for ; 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Mon, 31 Aug 2020 20:52:19 -0700 (PDT) Received: from yoga ([2605:6000:e5cb:c100:8898:14ff:fe6d:34e]) by smtp.gmail.com with ESMTPSA id u19sm2067501oic.10.2020.08.31.20.52.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 31 Aug 2020 20:52:19 -0700 (PDT) Date: Mon, 31 Aug 2020 22:52:16 -0500 From: Bjorn Andersson To: Rob Clark Subject: Re: [PATCH 05/19] iommu: add private interface for adreno-smmu Message-ID: <20200901035216.GM3715@yoga> References: <20200810222657.1841322-1-jcrouse@codeaurora.org> <20200814024114.1177553-6-robdclark@gmail.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20200814024114.1177553-6-robdclark@gmail.com> Cc: Rob Clark , open list , Will Deacon , linux-arm-msm@vger.kernel.org, Robin Murphy , dri-devel@lists.freedesktop.org, Stephen Boyd , iommu@lists.linux-foundation.org, Sibi Sankar , Vivek Gautam , freedreno@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org X-BeenThere: iommu@lists.linux-foundation.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Development issues for Linux IOMMU support List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: iommu-bounces@lists.linux-foundation.org Sender: "iommu" On Thu 13 Aug 21:41 CDT 2020, Rob Clark wrote: > From: Rob Clark > > This interface will be used for drm/msm to coordinate with the > qcom_adreno_smmu_impl to enable/disable TTBR0 translation. > > Once TTBR0 translation is enabled, the GPU's CP (Command Processor) > will directly switch TTBR0 pgtables (and do the necessary TLB inv) > synchronized to the GPU's operation. But help from the SMMU driver > is needed to initially bootstrap TTBR0 translation, which cannot be > done from the GPU. > > Since this is a very special case, a private interface is used to > avoid adding highly driver specific things to the public iommu > interface. > > Signed-off-by: Rob Clark Reviewed-by: Bjorn Andersson > --- > include/linux/adreno-smmu-priv.h | 36 ++++++++++++++++++++++++++++++++ > 1 file changed, 36 insertions(+) > create mode 100644 include/linux/adreno-smmu-priv.h > > diff --git a/include/linux/adreno-smmu-priv.h b/include/linux/adreno-smmu-priv.h > new file mode 100644 > index 000000000000..a889f28afb42 > --- /dev/null > +++ b/include/linux/adreno-smmu-priv.h > @@ -0,0 +1,36 @@ > +// SPDX-License-Identifier: GPL-2.0-only > +/* > + * Copyright (C) 2020 Google, Inc > + */ > + > +#ifndef __ADRENO_SMMU_PRIV_H > +#define __ADRENO_SMMU_PRIV_H > + > +#include > + > +/** > + * struct adreno_smmu_priv - private interface between adreno-smmu and GPU > + * > + * @cookie: An opque token provided by adreno-smmu and passed > + * back into the callbacks > + * @get_ttbr1_cfg: Get the TTBR1 config for the GPUs context-bank > + * @set_ttbr0_cfg: Set the TTBR0 config for the GPUs context bank. A > + * NULL config disables TTBR0 translation, otherwise > + * TTBR0 translation is enabled with the specified cfg > + * > + * The GPU driver (drm/msm) and adreno-smmu work together for controlling > + * the GPU's SMMU instance. This is by necessity, as the GPU is directly > + * updating the SMMU for context switches, while on the other hand we do > + * not want to duplicate all of the initial setup logic from arm-smmu. > + * > + * This private interface is used for the two drivers to coordinate. The > + * cookie and callback functions are populated when the GPU driver attaches > + * it's domain. > + */ > +struct adreno_smmu_priv { > + const void *cookie; > + const struct io_pgtable_cfg *(*get_ttbr1_cfg)(const void *cookie); > + int (*set_ttbr0_cfg)(const void *cookie, const struct io_pgtable_cfg *cfg); > +}; > + > +#endif /* __ADRENO_SMMU_PRIV_H */ > \ No newline at end of file > -- > 2.26.2 > _______________________________________________ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-10.0 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7CB95C433E2 for ; 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Mon, 31 Aug 2020 20:52:19 -0700 (PDT) Received: from yoga ([2605:6000:e5cb:c100:8898:14ff:fe6d:34e]) by smtp.gmail.com with ESMTPSA id u19sm2067501oic.10.2020.08.31.20.52.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 31 Aug 2020 20:52:19 -0700 (PDT) Date: Mon, 31 Aug 2020 22:52:16 -0500 From: Bjorn Andersson To: Rob Clark Subject: Re: [PATCH 05/19] iommu: add private interface for adreno-smmu Message-ID: <20200901035216.GM3715@yoga> References: <20200810222657.1841322-1-jcrouse@codeaurora.org> <20200814024114.1177553-6-robdclark@gmail.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20200814024114.1177553-6-robdclark@gmail.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200831_235222_316343_8DE07F51 X-CRM114-Status: GOOD ( 27.83 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Rob Clark , Sai Prakash Ranjan , open list , Will Deacon , linux-arm-msm@vger.kernel.org, Joerg Roedel , Robin Murphy , dri-devel@lists.freedesktop.org, Stephen Boyd , iommu@lists.linux-foundation.org, Sibi Sankar , Vivek Gautam , freedreno@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu 13 Aug 21:41 CDT 2020, Rob Clark wrote: > From: Rob Clark > > This interface will be used for drm/msm to coordinate with the > qcom_adreno_smmu_impl to enable/disable TTBR0 translation. > > Once TTBR0 translation is enabled, the GPU's CP (Command Processor) > will directly switch TTBR0 pgtables (and do the necessary TLB inv) > synchronized to the GPU's operation. But help from the SMMU driver > is needed to initially bootstrap TTBR0 translation, which cannot be > done from the GPU. > > Since this is a very special case, a private interface is used to > avoid adding highly driver specific things to the public iommu > interface. > > Signed-off-by: Rob Clark Reviewed-by: Bjorn Andersson > --- > include/linux/adreno-smmu-priv.h | 36 ++++++++++++++++++++++++++++++++ > 1 file changed, 36 insertions(+) > create mode 100644 include/linux/adreno-smmu-priv.h > > diff --git a/include/linux/adreno-smmu-priv.h b/include/linux/adreno-smmu-priv.h > new file mode 100644 > index 000000000000..a889f28afb42 > --- /dev/null > +++ b/include/linux/adreno-smmu-priv.h > @@ -0,0 +1,36 @@ > +// SPDX-License-Identifier: GPL-2.0-only > +/* > + * Copyright (C) 2020 Google, Inc > + */ > + > +#ifndef __ADRENO_SMMU_PRIV_H > +#define __ADRENO_SMMU_PRIV_H > + > +#include > + > +/** > + * struct adreno_smmu_priv - private interface between adreno-smmu and GPU > + * > + * @cookie: An opque token provided by adreno-smmu and passed > + * back into the callbacks > + * @get_ttbr1_cfg: Get the TTBR1 config for the GPUs context-bank > + * @set_ttbr0_cfg: Set the TTBR0 config for the GPUs context bank. A > + * NULL config disables TTBR0 translation, otherwise > + * TTBR0 translation is enabled with the specified cfg > + * > + * The GPU driver (drm/msm) and adreno-smmu work together for controlling > + * the GPU's SMMU instance. This is by necessity, as the GPU is directly > + * updating the SMMU for context switches, while on the other hand we do > + * not want to duplicate all of the initial setup logic from arm-smmu. > + * > + * This private interface is used for the two drivers to coordinate. The > + * cookie and callback functions are populated when the GPU driver attaches > + * it's domain. > + */ > +struct adreno_smmu_priv { > + const void *cookie; > + const struct io_pgtable_cfg *(*get_ttbr1_cfg)(const void *cookie); > + int (*set_ttbr0_cfg)(const void *cookie, const struct io_pgtable_cfg *cfg); > +}; > + > +#endif /* __ADRENO_SMMU_PRIV_H */ > \ No newline at end of file > -- > 2.26.2 > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E3B89C433E2 for ; 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Mon, 31 Aug 2020 20:52:19 -0700 (PDT) Received: from yoga ([2605:6000:e5cb:c100:8898:14ff:fe6d:34e]) by smtp.gmail.com with ESMTPSA id u19sm2067501oic.10.2020.08.31.20.52.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 31 Aug 2020 20:52:19 -0700 (PDT) Date: Mon, 31 Aug 2020 22:52:16 -0500 From: Bjorn Andersson To: Rob Clark Subject: Re: [PATCH 05/19] iommu: add private interface for adreno-smmu Message-ID: <20200901035216.GM3715@yoga> References: <20200810222657.1841322-1-jcrouse@codeaurora.org> <20200814024114.1177553-6-robdclark@gmail.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20200814024114.1177553-6-robdclark@gmail.com> X-Mailman-Approved-At: Tue, 01 Sep 2020 07:31:54 +0000 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Rob Clark , Sai Prakash Ranjan , open list , Will Deacon , linux-arm-msm@vger.kernel.org, Joerg Roedel , Robin Murphy , dri-devel@lists.freedesktop.org, Stephen Boyd , iommu@lists.linux-foundation.org, Sibi Sankar , Vivek Gautam , freedreno@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" On Thu 13 Aug 21:41 CDT 2020, Rob Clark wrote: > From: Rob Clark > > This interface will be used for drm/msm to coordinate with the > qcom_adreno_smmu_impl to enable/disable TTBR0 translation. > > Once TTBR0 translation is enabled, the GPU's CP (Command Processor) > will directly switch TTBR0 pgtables (and do the necessary TLB inv) > synchronized to the GPU's operation. But help from the SMMU driver > is needed to initially bootstrap TTBR0 translation, which cannot be > done from the GPU. > > Since this is a very special case, a private interface is used to > avoid adding highly driver specific things to the public iommu > interface. > > Signed-off-by: Rob Clark Reviewed-by: Bjorn Andersson > --- > include/linux/adreno-smmu-priv.h | 36 ++++++++++++++++++++++++++++++++ > 1 file changed, 36 insertions(+) > create mode 100644 include/linux/adreno-smmu-priv.h > > diff --git a/include/linux/adreno-smmu-priv.h b/include/linux/adreno-smmu-priv.h > new file mode 100644 > index 000000000000..a889f28afb42 > --- /dev/null > +++ b/include/linux/adreno-smmu-priv.h > @@ -0,0 +1,36 @@ > +// SPDX-License-Identifier: GPL-2.0-only > +/* > + * Copyright (C) 2020 Google, Inc > + */ > + > +#ifndef __ADRENO_SMMU_PRIV_H > +#define __ADRENO_SMMU_PRIV_H > + > +#include > + > +/** > + * struct adreno_smmu_priv - private interface between adreno-smmu and GPU > + * > + * @cookie: An opque token provided by adreno-smmu and passed > + * back into the callbacks > + * @get_ttbr1_cfg: Get the TTBR1 config for the GPUs context-bank > + * @set_ttbr0_cfg: Set the TTBR0 config for the GPUs context bank. A > + * NULL config disables TTBR0 translation, otherwise > + * TTBR0 translation is enabled with the specified cfg > + * > + * The GPU driver (drm/msm) and adreno-smmu work together for controlling > + * the GPU's SMMU instance. This is by necessity, as the GPU is directly > + * updating the SMMU for context switches, while on the other hand we do > + * not want to duplicate all of the initial setup logic from arm-smmu. > + * > + * This private interface is used for the two drivers to coordinate. The > + * cookie and callback functions are populated when the GPU driver attaches > + * it's domain. > + */ > +struct adreno_smmu_priv { > + const void *cookie; > + const struct io_pgtable_cfg *(*get_ttbr1_cfg)(const void *cookie); > + int (*set_ttbr0_cfg)(const void *cookie, const struct io_pgtable_cfg *cfg); > +}; > + > +#endif /* __ADRENO_SMMU_PRIV_H */ > \ No newline at end of file > -- > 2.26.2 > _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel