From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-10.1 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DBC25C433E6 for ; Tue, 1 Sep 2020 05:31:53 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id AF5682098B for ; Tue, 1 Sep 2020 05:31:53 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="EmSH5izG" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726512AbgIAFbv (ORCPT ); Tue, 1 Sep 2020 01:31:51 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46480 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726352AbgIAFbu (ORCPT ); Tue, 1 Sep 2020 01:31:50 -0400 Received: from mail-ot1-x343.google.com (mail-ot1-x343.google.com [IPv6:2607:f8b0:4864:20::343]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 24F9FC0612A0 for ; Mon, 31 Aug 2020 22:31:50 -0700 (PDT) Received: by mail-ot1-x343.google.com with SMTP id y5so143181otg.5 for ; Mon, 31 Aug 2020 22:31:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to; bh=ah4wulanW6w834elfegUZ00h7caLTkMycV73Sq0JJsc=; b=EmSH5izGYAYMIMbM05yD68/xN+pZG9cT5IEu4PC7V5EdHFWAtW1dw/0ERlIeS3MK0m hvKbP2VsYz1kPp88xPbs0rKAV0sC2BgYo3p9odC4ZXDU47xgDpmlYYQyn+xg5CmrR9Dd cNXatf9NQdMCm/EInmMdCFU7ot7LCEPW+ajWkr7YCtfJA7bB2LtV7/BGYyh8+jgzHz2+ CbGk8kZ0J/YJA8aVUce4DkurE5IzgQ0aRY9uVoUIYsUNOPzs9LjTh85QDcLM9++dKY6L LymH66Xyc6UIg5Zg5aUChODTVVDgpIcZizLEKqk8/3xNheD5RQ2xW/sP8vQBiDfoioAn pbKQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=ah4wulanW6w834elfegUZ00h7caLTkMycV73Sq0JJsc=; b=oep9+hVlSNxe1T+pl7B7Pr5fLOWzloTvAoefC49ksTxiO6itQRmKEJQjT0G4GB0wG5 TJuBnk1ViobCcot279uPW1WJThxmoppFYbF67thT8a/XV8KKNFM32L5BKLTS2tRD73Ac 7RHpkWhsyUwg95k/K+rHjcwkt+AuarJdAkAqEEN20TrpsFZtC9jZlQhGMZ2Zr2kdAfkO WAGPjaS0njt2w+vO6lYYqLiTr6oR/OC3Ty6IUrTGSR5mqidcRkCMrK5oXrbXJDStAkGO QK0bKCMmTR5vueo5V/JZ8thcHvgGX9pfkl4g68WQ7xW78SpTaimtnfLkoEi8XafaRTvn SlgA== X-Gm-Message-State: AOAM532iZvNTTclbAnLQCL7Z5qkCxyRvH0VFAgaQT4bCu8bSHDUrTPcs 6yPZnuSG8iDZXq6EM0POcqtDSQ== X-Google-Smtp-Source: ABdhPJwrHsRNsq+ddPo5+Vm3z1aTAOZfNB+Y5KDPl/h6cDxgUxeU167eyc1o9QYOLAnmTJw0ENBBWg== X-Received: by 2002:a9d:238b:: with SMTP id t11mr225178otb.60.1598938309430; Mon, 31 Aug 2020 22:31:49 -0700 (PDT) Received: from yoga ([2605:6000:e5cb:c100:8898:14ff:fe6d:34e]) by smtp.gmail.com with ESMTPSA id i23sm2099742oii.53.2020.08.31.22.31.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 31 Aug 2020 22:31:48 -0700 (PDT) Date: Tue, 1 Sep 2020 00:31:45 -0500 From: Bjorn Andersson To: Rob Clark Cc: dri-devel@lists.freedesktop.org, iommu@lists.linux-foundation.org, linux-arm-msm@vger.kernel.org, Sai Prakash Ranjan , Will Deacon , freedreno@lists.freedesktop.org, Sibi Sankar , Vivek Gautam , Stephen Boyd , Robin Murphy , Joerg Roedel , linux-arm-kernel@lists.infradead.org, Rob Clark , Jordan Crouse , Greg Kroah-Hartman , Thierry Reding , Krishna Reddy , Jon Hunter , open list Subject: Re: [PATCH 18/19] iommu/arm-smmu: add a way for implementations to influence SCTLR Message-ID: <20200901053145.GX3715@yoga> References: <20200810222657.1841322-1-jcrouse@codeaurora.org> <20200814024114.1177553-19-robdclark@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20200814024114.1177553-19-robdclark@gmail.com> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On Thu 13 Aug 21:41 CDT 2020, Rob Clark wrote: > From: Rob Clark > > For the Adreno GPU's SMMU, we want SCTLR.HUPCF set to ensure that > pending translations are not terminated on iova fault. Otherwise > a terminated CP read could hang the GPU by returning invalid > command-stream data. > Reviewed-by: Bjorn Andersson > Signed-off-by: Rob Clark > --- > drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 6 ++++++ > drivers/iommu/arm/arm-smmu/arm-smmu.c | 3 +++ > drivers/iommu/arm/arm-smmu/arm-smmu.h | 3 +++ > 3 files changed, 12 insertions(+) > > diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c > index 5640d9960610..2aa6249050ff 100644 > --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c > +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c > @@ -127,6 +127,12 @@ static int qcom_adreno_smmu_init_context(struct arm_smmu_domain *smmu_domain, > (smmu_domain->cfg.fmt == ARM_SMMU_CTX_FMT_AARCH64)) > pgtbl_cfg->quirks |= IO_PGTABLE_QUIRK_ARM_TTBR1; > > + /* > + * On the GPU device we want to process subsequent transactions after a > + * fault to keep the GPU from hanging > + */ > + smmu_domain->cfg.sctlr_set |= ARM_SMMU_SCTLR_HUPCF; > + > /* > * Initialize private interface with GPU: > */ > diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.c b/drivers/iommu/arm/arm-smmu/arm-smmu.c > index e63a480d7f71..bbec5793faf8 100644 > --- a/drivers/iommu/arm/arm-smmu/arm-smmu.c > +++ b/drivers/iommu/arm/arm-smmu/arm-smmu.c > @@ -617,6 +617,9 @@ void arm_smmu_write_context_bank(struct arm_smmu_device *smmu, int idx) > if (IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)) > reg |= ARM_SMMU_SCTLR_E; > > + reg |= cfg->sctlr_set; > + reg &= ~cfg->sctlr_clr; > + > arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_SCTLR, reg); > } > > diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.h b/drivers/iommu/arm/arm-smmu/arm-smmu.h > index cd75a33967bb..2df3a70a8a41 100644 > --- a/drivers/iommu/arm/arm-smmu/arm-smmu.h > +++ b/drivers/iommu/arm/arm-smmu/arm-smmu.h > @@ -144,6 +144,7 @@ enum arm_smmu_cbar_type { > #define ARM_SMMU_CB_SCTLR 0x0 > #define ARM_SMMU_SCTLR_S1_ASIDPNE BIT(12) > #define ARM_SMMU_SCTLR_CFCFG BIT(7) > +#define ARM_SMMU_SCTLR_HUPCF BIT(8) > #define ARM_SMMU_SCTLR_CFIE BIT(6) > #define ARM_SMMU_SCTLR_CFRE BIT(5) > #define ARM_SMMU_SCTLR_E BIT(4) > @@ -341,6 +342,8 @@ struct arm_smmu_cfg { > u16 asid; > u16 vmid; > }; > + u32 sctlr_set; /* extra bits to set in SCTLR */ > + u32 sctlr_clr; /* bits to mask in SCTLR */ > enum arm_smmu_cbar_type cbar; > enum arm_smmu_context_fmt fmt; > }; > -- > 2.26.2 > From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 41718C43461 for ; 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Mon, 31 Aug 2020 22:31:49 -0700 (PDT) Received: from yoga ([2605:6000:e5cb:c100:8898:14ff:fe6d:34e]) by smtp.gmail.com with ESMTPSA id i23sm2099742oii.53.2020.08.31.22.31.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 31 Aug 2020 22:31:48 -0700 (PDT) Date: Tue, 1 Sep 2020 00:31:45 -0500 From: Bjorn Andersson To: Rob Clark Subject: Re: [PATCH 18/19] iommu/arm-smmu: add a way for implementations to influence SCTLR Message-ID: <20200901053145.GX3715@yoga> References: <20200810222657.1841322-1-jcrouse@codeaurora.org> <20200814024114.1177553-19-robdclark@gmail.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20200814024114.1177553-19-robdclark@gmail.com> Cc: Rob Clark , open list , Will Deacon , linux-arm-msm@vger.kernel.org, Robin Murphy , dri-devel@lists.freedesktop.org, Stephen Boyd , iommu@lists.linux-foundation.org, Sibi Sankar , Vivek Gautam , Greg Kroah-Hartman , Jon Hunter , Thierry Reding , freedreno@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org X-BeenThere: iommu@lists.linux-foundation.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Development issues for Linux IOMMU support List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: iommu-bounces@lists.linux-foundation.org Sender: "iommu" On Thu 13 Aug 21:41 CDT 2020, Rob Clark wrote: > From: Rob Clark > > For the Adreno GPU's SMMU, we want SCTLR.HUPCF set to ensure that > pending translations are not terminated on iova fault. Otherwise > a terminated CP read could hang the GPU by returning invalid > command-stream data. > Reviewed-by: Bjorn Andersson > Signed-off-by: Rob Clark > --- > drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 6 ++++++ > drivers/iommu/arm/arm-smmu/arm-smmu.c | 3 +++ > drivers/iommu/arm/arm-smmu/arm-smmu.h | 3 +++ > 3 files changed, 12 insertions(+) > > diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c > index 5640d9960610..2aa6249050ff 100644 > --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c > +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c > @@ -127,6 +127,12 @@ static int qcom_adreno_smmu_init_context(struct arm_smmu_domain *smmu_domain, > (smmu_domain->cfg.fmt == ARM_SMMU_CTX_FMT_AARCH64)) > pgtbl_cfg->quirks |= IO_PGTABLE_QUIRK_ARM_TTBR1; > > + /* > + * On the GPU device we want to process subsequent transactions after a > + * fault to keep the GPU from hanging > + */ > + smmu_domain->cfg.sctlr_set |= ARM_SMMU_SCTLR_HUPCF; > + > /* > * Initialize private interface with GPU: > */ > diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.c b/drivers/iommu/arm/arm-smmu/arm-smmu.c > index e63a480d7f71..bbec5793faf8 100644 > --- a/drivers/iommu/arm/arm-smmu/arm-smmu.c > +++ b/drivers/iommu/arm/arm-smmu/arm-smmu.c > @@ -617,6 +617,9 @@ void arm_smmu_write_context_bank(struct arm_smmu_device *smmu, int idx) > if (IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)) > reg |= ARM_SMMU_SCTLR_E; > > + reg |= cfg->sctlr_set; > + reg &= ~cfg->sctlr_clr; > + > arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_SCTLR, reg); > } > > diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.h b/drivers/iommu/arm/arm-smmu/arm-smmu.h > index cd75a33967bb..2df3a70a8a41 100644 > --- a/drivers/iommu/arm/arm-smmu/arm-smmu.h > +++ b/drivers/iommu/arm/arm-smmu/arm-smmu.h > @@ -144,6 +144,7 @@ enum arm_smmu_cbar_type { > #define ARM_SMMU_CB_SCTLR 0x0 > #define ARM_SMMU_SCTLR_S1_ASIDPNE BIT(12) > #define ARM_SMMU_SCTLR_CFCFG BIT(7) > +#define ARM_SMMU_SCTLR_HUPCF BIT(8) > #define ARM_SMMU_SCTLR_CFIE BIT(6) > #define ARM_SMMU_SCTLR_CFRE BIT(5) > #define ARM_SMMU_SCTLR_E BIT(4) > @@ -341,6 +342,8 @@ struct arm_smmu_cfg { > u16 asid; > u16 vmid; > }; > + u32 sctlr_set; /* extra bits to set in SCTLR */ > + u32 sctlr_clr; /* bits to mask in SCTLR */ > enum arm_smmu_cbar_type cbar; > enum arm_smmu_context_fmt fmt; > }; > -- > 2.26.2 > _______________________________________________ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-10.0 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1217BC433E2 for ; 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Mon, 31 Aug 2020 22:31:49 -0700 (PDT) Received: from yoga ([2605:6000:e5cb:c100:8898:14ff:fe6d:34e]) by smtp.gmail.com with ESMTPSA id i23sm2099742oii.53.2020.08.31.22.31.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 31 Aug 2020 22:31:48 -0700 (PDT) Date: Tue, 1 Sep 2020 00:31:45 -0500 From: Bjorn Andersson To: Rob Clark Subject: Re: [PATCH 18/19] iommu/arm-smmu: add a way for implementations to influence SCTLR Message-ID: <20200901053145.GX3715@yoga> References: <20200810222657.1841322-1-jcrouse@codeaurora.org> <20200814024114.1177553-19-robdclark@gmail.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20200814024114.1177553-19-robdclark@gmail.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200901_013151_304521_78265667 X-CRM114-Status: GOOD ( 21.97 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Rob Clark , Sai Prakash Ranjan , Jordan Crouse , open list , Will Deacon , linux-arm-msm@vger.kernel.org, Joerg Roedel , Robin Murphy , dri-devel@lists.freedesktop.org, Stephen Boyd , iommu@lists.linux-foundation.org, Sibi Sankar , Vivek Gautam , Greg Kroah-Hartman , Jon Hunter , Thierry Reding , freedreno@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu 13 Aug 21:41 CDT 2020, Rob Clark wrote: > From: Rob Clark > > For the Adreno GPU's SMMU, we want SCTLR.HUPCF set to ensure that > pending translations are not terminated on iova fault. Otherwise > a terminated CP read could hang the GPU by returning invalid > command-stream data. > Reviewed-by: Bjorn Andersson > Signed-off-by: Rob Clark > --- > drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 6 ++++++ > drivers/iommu/arm/arm-smmu/arm-smmu.c | 3 +++ > drivers/iommu/arm/arm-smmu/arm-smmu.h | 3 +++ > 3 files changed, 12 insertions(+) > > diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c > index 5640d9960610..2aa6249050ff 100644 > --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c > +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c > @@ -127,6 +127,12 @@ static int qcom_adreno_smmu_init_context(struct arm_smmu_domain *smmu_domain, > (smmu_domain->cfg.fmt == ARM_SMMU_CTX_FMT_AARCH64)) > pgtbl_cfg->quirks |= IO_PGTABLE_QUIRK_ARM_TTBR1; > > + /* > + * On the GPU device we want to process subsequent transactions after a > + * fault to keep the GPU from hanging > + */ > + smmu_domain->cfg.sctlr_set |= ARM_SMMU_SCTLR_HUPCF; > + > /* > * Initialize private interface with GPU: > */ > diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.c b/drivers/iommu/arm/arm-smmu/arm-smmu.c > index e63a480d7f71..bbec5793faf8 100644 > --- a/drivers/iommu/arm/arm-smmu/arm-smmu.c > +++ b/drivers/iommu/arm/arm-smmu/arm-smmu.c > @@ -617,6 +617,9 @@ void arm_smmu_write_context_bank(struct arm_smmu_device *smmu, int idx) > if (IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)) > reg |= ARM_SMMU_SCTLR_E; > > + reg |= cfg->sctlr_set; > + reg &= ~cfg->sctlr_clr; > + > arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_SCTLR, reg); > } > > diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.h b/drivers/iommu/arm/arm-smmu/arm-smmu.h > index cd75a33967bb..2df3a70a8a41 100644 > --- a/drivers/iommu/arm/arm-smmu/arm-smmu.h > +++ b/drivers/iommu/arm/arm-smmu/arm-smmu.h > @@ -144,6 +144,7 @@ enum arm_smmu_cbar_type { > #define ARM_SMMU_CB_SCTLR 0x0 > #define ARM_SMMU_SCTLR_S1_ASIDPNE BIT(12) > #define ARM_SMMU_SCTLR_CFCFG BIT(7) > +#define ARM_SMMU_SCTLR_HUPCF BIT(8) > #define ARM_SMMU_SCTLR_CFIE BIT(6) > #define ARM_SMMU_SCTLR_CFRE BIT(5) > #define ARM_SMMU_SCTLR_E BIT(4) > @@ -341,6 +342,8 @@ struct arm_smmu_cfg { > u16 asid; > u16 vmid; > }; > + u32 sctlr_set; /* extra bits to set in SCTLR */ > + u32 sctlr_clr; /* bits to mask in SCTLR */ > enum arm_smmu_cbar_type cbar; > enum arm_smmu_context_fmt fmt; > }; > -- > 2.26.2 > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E525AC433E7 for ; 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Mon, 31 Aug 2020 22:31:49 -0700 (PDT) Received: from yoga ([2605:6000:e5cb:c100:8898:14ff:fe6d:34e]) by smtp.gmail.com with ESMTPSA id i23sm2099742oii.53.2020.08.31.22.31.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 31 Aug 2020 22:31:48 -0700 (PDT) Date: Tue, 1 Sep 2020 00:31:45 -0500 From: Bjorn Andersson To: Rob Clark Subject: Re: [PATCH 18/19] iommu/arm-smmu: add a way for implementations to influence SCTLR Message-ID: <20200901053145.GX3715@yoga> References: <20200810222657.1841322-1-jcrouse@codeaurora.org> <20200814024114.1177553-19-robdclark@gmail.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20200814024114.1177553-19-robdclark@gmail.com> X-Mailman-Approved-At: Tue, 01 Sep 2020 07:31:54 +0000 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Rob Clark , Sai Prakash Ranjan , open list , Will Deacon , linux-arm-msm@vger.kernel.org, Joerg Roedel , Robin Murphy , dri-devel@lists.freedesktop.org, Stephen Boyd , iommu@lists.linux-foundation.org, Krishna Reddy , Sibi Sankar , Vivek Gautam , Greg Kroah-Hartman , Jon Hunter , Thierry Reding , freedreno@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" On Thu 13 Aug 21:41 CDT 2020, Rob Clark wrote: > From: Rob Clark > > For the Adreno GPU's SMMU, we want SCTLR.HUPCF set to ensure that > pending translations are not terminated on iova fault. Otherwise > a terminated CP read could hang the GPU by returning invalid > command-stream data. > Reviewed-by: Bjorn Andersson > Signed-off-by: Rob Clark > --- > drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 6 ++++++ > drivers/iommu/arm/arm-smmu/arm-smmu.c | 3 +++ > drivers/iommu/arm/arm-smmu/arm-smmu.h | 3 +++ > 3 files changed, 12 insertions(+) > > diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c > index 5640d9960610..2aa6249050ff 100644 > --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c > +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c > @@ -127,6 +127,12 @@ static int qcom_adreno_smmu_init_context(struct arm_smmu_domain *smmu_domain, > (smmu_domain->cfg.fmt == ARM_SMMU_CTX_FMT_AARCH64)) > pgtbl_cfg->quirks |= IO_PGTABLE_QUIRK_ARM_TTBR1; > > + /* > + * On the GPU device we want to process subsequent transactions after a > + * fault to keep the GPU from hanging > + */ > + smmu_domain->cfg.sctlr_set |= ARM_SMMU_SCTLR_HUPCF; > + > /* > * Initialize private interface with GPU: > */ > diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.c b/drivers/iommu/arm/arm-smmu/arm-smmu.c > index e63a480d7f71..bbec5793faf8 100644 > --- a/drivers/iommu/arm/arm-smmu/arm-smmu.c > +++ b/drivers/iommu/arm/arm-smmu/arm-smmu.c > @@ -617,6 +617,9 @@ void arm_smmu_write_context_bank(struct arm_smmu_device *smmu, int idx) > if (IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)) > reg |= ARM_SMMU_SCTLR_E; > > + reg |= cfg->sctlr_set; > + reg &= ~cfg->sctlr_clr; > + > arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_SCTLR, reg); > } > > diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.h b/drivers/iommu/arm/arm-smmu/arm-smmu.h > index cd75a33967bb..2df3a70a8a41 100644 > --- a/drivers/iommu/arm/arm-smmu/arm-smmu.h > +++ b/drivers/iommu/arm/arm-smmu/arm-smmu.h > @@ -144,6 +144,7 @@ enum arm_smmu_cbar_type { > #define ARM_SMMU_CB_SCTLR 0x0 > #define ARM_SMMU_SCTLR_S1_ASIDPNE BIT(12) > #define ARM_SMMU_SCTLR_CFCFG BIT(7) > +#define ARM_SMMU_SCTLR_HUPCF BIT(8) > #define ARM_SMMU_SCTLR_CFIE BIT(6) > #define ARM_SMMU_SCTLR_CFRE BIT(5) > #define ARM_SMMU_SCTLR_E BIT(4) > @@ -341,6 +342,8 @@ struct arm_smmu_cfg { > u16 asid; > u16 vmid; > }; > + u32 sctlr_set; /* extra bits to set in SCTLR */ > + u32 sctlr_clr; /* bits to mask in SCTLR */ > enum arm_smmu_cbar_type cbar; > enum arm_smmu_context_fmt fmt; > }; > -- > 2.26.2 > _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel