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Iglesias" To: Richard Henderson Subject: Re: [PATCH v2 04/12] target/microblaze: Rename mmu structs Message-ID: <20200904121031.GM14249@toto> References: <20200903072650.1360454-1-richard.henderson@linaro.org> <20200903072650.1360454-5-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20200903072650.1360454-5-richard.henderson@linaro.org> User-Agent: Mutt/1.10.1 (2018-07-13) X-RCIS-Action: ALLOW X-TM-AS-Product-Ver: IMSS-7.1.0.1224-8.2.0.1013-23620.005 X-TM-AS-User-Approved-Sender: Yes;Yes X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 62ea571c-e35a-4cd5-4aec-08d850cb8950 X-MS-TrafficTypeDiagnostic: BYAPR02MB5654: X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Oob-TLC-OOBClassifiers: OLM:2657; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 6A2+jEp0de6MyqdxsOrSJDp7YGwYbxLqllBDRv7Oi6OIeuxp9BJNzEqFfDm6YGpYzj4uf/IZFFbNIsyNcDTB+SJoz1NXWYtSOMuBTFrT5HyHazirwmfx+9laJZllsgf4mrh8D4AJQjAqN+y7Wr54t7gKm3ScS5JEh2Jo6xkFL0zaX3bhXzOwjYPBzcxMWL8zdaJPF5egp3KQSuzYprK23fFcmuo6ufe3EGG/P/tt91XVJdA47YRztg2ouf3QHZdV5P1wOEhEhePbMcKC5nHCwSmpxq/kCL0/paMD9YlsXIyg6RcSq26psU0rtWvCuF8wSbOoSg2/bfBM+7M6MTrwMWzP/DMelSR32aQN6aAMCHv5lhpQWf0QX9uL58dYqG77xca+mU4TUf1s/8a6xS9ykQ== X-Forefront-Antispam-Report: CIP:149.199.60.83; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:xsj-pvapsmtpgw01; PTR:unknown-60-83.xilinx.com; CAT:NONE; SFS:(7916004)(39860400002)(396003)(346002)(376002)(136003)(46966005)(2906002)(82310400003)(6666004)(47076004)(316002)(9786002)(33656002)(356005)(4326008)(33716001)(9686003)(8936002)(83380400001)(82740400003)(5660300002)(1076003)(81166007)(426003)(478600001)(8676002)(26005)(70206006)(70586007)(186003)(6916009)(336012); DIR:OUT; SFP:1101; X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Sep 2020 12:10:38.5189 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 62ea571c-e35a-4cd5-4aec-08d850cb8950 X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c; Ip=[149.199.60.83]; Helo=[xsj-pvapsmtpgw01] X-MS-Exchange-CrossTenant-AuthSource: SN1NAM02FT031.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BYAPR02MB5654 Received-SPF: pass client-ip=40.107.223.89; envelope-from=edgar@xilinx.com; helo=NAM11-DM6-obe.outbound.protection.outlook.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/09/04 08:10:39 X-ACL-Warn: Detected OS = Windows NT kernel [generic] [fuzzy] X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: thuth@redhat.com, qemu-devel@nongnu.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Thu, Sep 03, 2020 at 12:26:42AM -0700, Richard Henderson wrote: > Introduce typedefs and follow CODING_STYLE for naming. > Rename struct microblaze_mmu to MicroBlazeMMU. > Rename struct microblaze_mmu_lookup to MicroBlazeMMULookup. > > Signed-off-by: Richard Henderson Reviewed-by: Edgar E. Iglesias > --- > target/microblaze/cpu.h | 2 +- > target/microblaze/mmu.h | 15 ++++++--------- > target/microblaze/helper.c | 4 ++-- > target/microblaze/mmu.c | 11 +++++------ > 4 files changed, 14 insertions(+), 18 deletions(-) > > diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h > index 32811f773d..20c2979396 100644 > --- a/target/microblaze/cpu.h > +++ b/target/microblaze/cpu.h > @@ -278,7 +278,7 @@ struct CPUMBState { > > #if !defined(CONFIG_USER_ONLY) > /* Unified MMU. */ > - struct microblaze_mmu mmu; > + MicroBlazeMMU mmu; > #endif > > /* Fields up to this point are cleared by a CPU reset */ > diff --git a/target/microblaze/mmu.h b/target/microblaze/mmu.h > index 75e5301c79..c1feb811b9 100644 > --- a/target/microblaze/mmu.h > +++ b/target/microblaze/mmu.h > @@ -63,8 +63,7 @@ > > #define TLB_ENTRIES 64 > > -struct microblaze_mmu > -{ > +typedef struct { > /* Data and tag brams. */ > uint64_t rams[2][TLB_ENTRIES]; > /* We keep a separate ram for the tids to avoid the 48 bit tag width. */ > @@ -76,10 +75,9 @@ struct microblaze_mmu > int c_mmu_tlb_access; > int c_mmu_zones; > uint64_t c_addr_mask; /* Mask to apply to physical addresses. */ > -}; > +} MicroBlazeMMU; > > -struct microblaze_mmu_lookup > -{ > +typedef struct { > uint32_t paddr; > uint32_t vaddr; > unsigned int size; > @@ -88,13 +86,12 @@ struct microblaze_mmu_lookup > enum { > ERR_PROT, ERR_MISS, ERR_HIT > } err; > -}; > +} MicroBlazeMMULookup; > > -unsigned int mmu_translate(struct microblaze_mmu *mmu, > - struct microblaze_mmu_lookup *lu, > +unsigned int mmu_translate(MicroBlazeMMU *mmu, MicroBlazeMMULookup *lu, > target_ulong vaddr, int rw, int mmu_idx); > uint32_t mmu_read(CPUMBState *env, bool ea, uint32_t rn); > void mmu_write(CPUMBState *env, bool ea, uint32_t rn, uint32_t v); > -void mmu_init(struct microblaze_mmu *mmu); > +void mmu_init(MicroBlazeMMU *mmu); > > #endif > diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c > index 27a24bb99a..3c2fd388fb 100644 > --- a/target/microblaze/helper.c > +++ b/target/microblaze/helper.c > @@ -52,7 +52,7 @@ bool mb_cpu_tlb_fill(CPUState *cs, vaddr address, int size, > { > MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs); > CPUMBState *env = &cpu->env; > - struct microblaze_mmu_lookup lu; > + MicroBlazeMMULookup lu; > unsigned int hit; > int prot; > > @@ -235,7 +235,7 @@ hwaddr mb_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) > MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs); > CPUMBState *env = &cpu->env; > target_ulong vaddr, paddr = 0; > - struct microblaze_mmu_lookup lu; > + MicroBlazeMMULookup lu; > int mmu_idx = cpu_mmu_index(env, false); > unsigned int hit; > > diff --git a/target/microblaze/mmu.c b/target/microblaze/mmu.c > index 6e583d78d9..0546cfd0bc 100644 > --- a/target/microblaze/mmu.c > +++ b/target/microblaze/mmu.c > @@ -35,7 +35,7 @@ static unsigned int tlb_decode_size(unsigned int f) > static void mmu_flush_idx(CPUMBState *env, unsigned int idx) > { > CPUState *cs = env_cpu(env); > - struct microblaze_mmu *mmu = &env->mmu; > + MicroBlazeMMU *mmu = &env->mmu; > unsigned int tlb_size; > uint32_t tlb_tag, end, t; > > @@ -55,7 +55,7 @@ static void mmu_flush_idx(CPUMBState *env, unsigned int idx) > > static void mmu_change_pid(CPUMBState *env, unsigned int newpid) > { > - struct microblaze_mmu *mmu = &env->mmu; > + MicroBlazeMMU *mmu = &env->mmu; > unsigned int i; > uint32_t t; > > @@ -73,8 +73,7 @@ static void mmu_change_pid(CPUMBState *env, unsigned int newpid) > } > > /* rw - 0 = read, 1 = write, 2 = fetch. */ > -unsigned int mmu_translate(struct microblaze_mmu *mmu, > - struct microblaze_mmu_lookup *lu, > +unsigned int mmu_translate(MicroBlazeMMU *mmu, MicroBlazeMMULookup *lu, > target_ulong vaddr, int rw, int mmu_idx) > { > unsigned int i, hit = 0; > @@ -290,7 +289,7 @@ void mmu_write(CPUMBState *env, bool ext, uint32_t rn, uint32_t v) > break; > case MMU_R_TLBSX: > { > - struct microblaze_mmu_lookup lu; > + MicroBlazeMMULookup lu; > int hit; > > if (env->mmu.c_mmu_tlb_access <= 1) { > @@ -314,7 +313,7 @@ void mmu_write(CPUMBState *env, bool ext, uint32_t rn, uint32_t v) > } > } > > -void mmu_init(struct microblaze_mmu *mmu) > +void mmu_init(MicroBlazeMMU *mmu) > { > int i; > for (i = 0; i < ARRAY_SIZE(mmu->regs); i++) { > -- > 2.25.1 >