From: Kim Phillips <kim.phillips@amd.com>
To: Borislav Petkov <bp@alien8.de>, Borislav Petkov <bp@suse.de>,
Peter Zijlstra <peterz@infradead.org>,
Ingo Molnar <mingo@kernel.org>, Ingo Molnar <mingo@redhat.com>,
Thomas Gleixner <tglx@linutronix.de>,
kim.phillips@amd.com
Cc: Stephane Eranian <eranian@google.com>,
Alexander Shishkin <alexander.shishkin@linux.intel.com>,
Arnaldo Carvalho de Melo <acme@kernel.org>,
"H. Peter Anvin" <hpa@zytor.com>, Jiri Olsa <jolsa@redhat.com>,
Mark Rutland <mark.rutland@arm.com>,
Michael Petlan <mpetlan@redhat.com>,
Namhyung Kim <namhyung@kernel.org>,
LKML <linux-kernel@vger.kernel.org>, x86 <x86@kernel.org>,
stable@vger.kernel.org
Subject: [PATCH v2 1/7] perf/amd/uncore: Set all slices and threads to restore perf stat -a behaviour
Date: Tue, 8 Sep 2020 16:47:34 -0500 [thread overview]
Message-ID: <20200908214740.18097-2-kim.phillips@amd.com> (raw)
In-Reply-To: <20200908214740.18097-1-kim.phillips@amd.com>
Commit 2f217d58a8a0 ("perf/x86/amd/uncore: Set the thread mask for
F17h L3 PMCs") inadvertently changed the uncore driver's behaviour
wrt perf tool invocations with or without a CPU list, specified with
-C / --cpu=.
Change the behaviour of the driver to assume the former all-cpu (-a)
case, which is the more commonly desired default. This fixes
'-a -A' invocations without explicit cpu lists (-C) to not count
L3 events only on behalf of the first thread of the first core
in the L3 domain.
BEFORE:
Activity performed by the first thread of the last core (CPU#43) in
CPU#40's L3 domain is not reported by CPU#40:
sudo perf stat -a -A -e l3_request_g1.caching_l3_cache_accesses taskset -c 43 perf bench mem memcpy -s 32mb -l 100 -f default
...
CPU36 21,835 l3_request_g1.caching_l3_cache_accesses
CPU40 87,066 l3_request_g1.caching_l3_cache_accesses
CPU44 17,360 l3_request_g1.caching_l3_cache_accesses
...
AFTER:
The L3 domain activity is now reported by CPU#40:
sudo perf stat -a -A -e l3_request_g1.caching_l3_cache_accesses taskset -c 43 perf bench mem memcpy -s 32mb -l 100 -f default
...
CPU36 354,891 l3_request_g1.caching_l3_cache_accesses
CPU40 1,780,870 l3_request_g1.caching_l3_cache_accesses
CPU44 315,062 l3_request_g1.caching_l3_cache_accesses
...
Signed-off-by: Kim Phillips <kim.phillips@amd.com>
Fixes: 2f217d58a8a0 ("perf/x86/amd/uncore: Set the thread mask for F17h L3 PMCs")
Cc: Stephane Eranian <eranian@google.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Ingo Molnar <mingo@kernel.org>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Borislav Petkov <bp@alien8.de>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Arnaldo Carvalho de Melo <acme@kernel.org>
Cc: "H. Peter Anvin" <hpa@zytor.com>
Cc: Jiri Olsa <jolsa@redhat.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Michael Petlan <mpetlan@redhat.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: LKML <linux-kernel@vger.kernel.org>
Cc: x86 <x86@kernel.org>
Cc: stable@vger.kernel.org
---
v2: no changes.
Original submission:
https://lore.kernel.org/lkml/20200323233159.19601-1-kim.phillips@amd.com/
arch/x86/events/amd/uncore.c | 28 ++++++++--------------------
1 file changed, 8 insertions(+), 20 deletions(-)
diff --git a/arch/x86/events/amd/uncore.c b/arch/x86/events/amd/uncore.c
index 76400c052b0e..e7e61c8b56bd 100644
--- a/arch/x86/events/amd/uncore.c
+++ b/arch/x86/events/amd/uncore.c
@@ -181,28 +181,16 @@ static void amd_uncore_del(struct perf_event *event, int flags)
}
/*
- * Convert logical CPU number to L3 PMC Config ThreadMask format
+ * Return a full thread and slice mask until per-CPU is
+ * properly supported.
*/
-static u64 l3_thread_slice_mask(int cpu)
+static u64 l3_thread_slice_mask(void)
{
- u64 thread_mask, core = topology_core_id(cpu);
- unsigned int shift, thread = 0;
+ if (boot_cpu_data.x86 <= 0x18)
+ return AMD64_L3_SLICE_MASK | AMD64_L3_THREAD_MASK;
- if (topology_smt_supported() && !topology_is_primary_thread(cpu))
- thread = 1;
-
- if (boot_cpu_data.x86 <= 0x18) {
- shift = AMD64_L3_THREAD_SHIFT + 2 * (core % 4) + thread;
- thread_mask = BIT_ULL(shift);
-
- return AMD64_L3_SLICE_MASK | thread_mask;
- }
-
- core = (core << AMD64_L3_COREID_SHIFT) & AMD64_L3_COREID_MASK;
- shift = AMD64_L3_THREAD_SHIFT + thread;
- thread_mask = BIT_ULL(shift);
-
- return AMD64_L3_EN_ALL_SLICES | core | thread_mask;
+ return AMD64_L3_EN_ALL_SLICES | AMD64_L3_EN_ALL_CORES |
+ AMD64_L3_F19H_THREAD_MASK;
}
static int amd_uncore_event_init(struct perf_event *event)
@@ -232,7 +220,7 @@ static int amd_uncore_event_init(struct perf_event *event)
* For other events, the two fields do not affect the count.
*/
if (l3_mask && is_llc_event(event))
- hwc->config |= l3_thread_slice_mask(event->cpu);
+ hwc->config |= l3_thread_slice_mask();
uncore = event_to_amd_uncore(event);
if (!uncore)
--
2.27.0
next prev parent reply other threads:[~2020-09-08 21:48 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-09-08 21:47 [PATCH v2 0/7] perf/x86/amd: Miscellaneous updates Kim Phillips
2020-09-08 21:47 ` Kim Phillips [this message]
2020-09-10 16:34 ` [PATCH v2 1/7] perf/amd/uncore: Set all slices and threads to restore perf stat -a behaviour Sasha Levin
2020-09-11 7:02 ` [tip: perf/core] " tip-bot2 for Kim Phillips
2020-09-08 21:47 ` [PATCH v2 2/7] perf/x86/amd: Fix sampling Large Increment per Cycle events Kim Phillips
2020-09-08 21:47 ` [PATCH v2 3/7] arch/x86/amd/ibs: Fix re-arming IBS Fetch Kim Phillips
2020-09-10 8:32 ` peterz
2020-09-10 8:50 ` peterz
2020-09-10 15:58 ` Kim Phillips
2020-09-08 21:47 ` [PATCH v2 4/7] perf/x86/amd/ibs: Don't include randomized bits in get_ibs_op_count() Kim Phillips
2020-09-08 21:47 ` [PATCH v2 5/7] perf/x86/amd/ibs: Fix raw sample data accumulation Kim Phillips
2020-09-11 7:02 ` [tip: perf/core] " tip-bot2 for Kim Phillips
2020-09-08 21:47 ` [PATCH v2 6/7] perf/x86/amd/ibs: Support 27-bit extended Op/cycle counter Kim Phillips
2020-09-11 7:02 ` [tip: perf/core] " tip-bot2 for Kim Phillips
2020-09-08 21:47 ` [PATCH v2 7/7] perf/x86/rapl: Add AMD Fam19h RAPL support Kim Phillips
2020-09-11 7:02 ` [tip: perf/core] " tip-bot2 for Kim Phillips
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