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From: Jani Nikula <jani.nikula@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: jani.nikula@intel.com
Subject: [Intel-gfx] [PATCH 2/3] drm/i915: move gen4 GCDGMBUS save/restore to display save/restore
Date: Thu, 10 Sep 2020 12:52:26 +0300	[thread overview]
Message-ID: <20200910095227.9466-2-jani.nikula@intel.com> (raw)
In-Reply-To: <20200910095227.9466-1-jani.nikula@intel.com>

Logically part of the display save/restore. No functional changes.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/i915_suspend.c | 21 ++++++++++++---------
 1 file changed, 12 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c
index ed2be3489f8e..4a93247942b7 100644
--- a/drivers/gpu/drm/i915/i915_suspend.c
+++ b/drivers/gpu/drm/i915/i915_suspend.c
@@ -34,6 +34,8 @@
 
 static void i915_save_display(struct drm_i915_private *dev_priv)
 {
+	struct pci_dev *pdev = dev_priv->drm.pdev;
+
 	/* Display arbitration control */
 	if (INTEL_GEN(dev_priv) <= 4)
 		dev_priv->regfile.saveDSPARB = I915_READ(DSPARB);
@@ -41,10 +43,20 @@ static void i915_save_display(struct drm_i915_private *dev_priv)
 	/* save FBC interval */
 	if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) <= 4 && !IS_G4X(dev_priv))
 		dev_priv->regfile.saveFBC_CONTROL = I915_READ(FBC_CONTROL);
+
+	if (IS_GEN(dev_priv, 4))
+		pci_read_config_word(pdev, GCDGMBUS,
+				     &dev_priv->regfile.saveGCDGMBUS);
 }
 
 static void i915_restore_display(struct drm_i915_private *dev_priv)
 {
+	struct pci_dev *pdev = dev_priv->drm.pdev;
+
+	if (IS_GEN(dev_priv, 4))
+		pci_write_config_word(pdev, GCDGMBUS,
+				      dev_priv->regfile.saveGCDGMBUS);
+
 	/* Display arbitration */
 	if (INTEL_GEN(dev_priv) <= 4)
 		I915_WRITE(DSPARB, dev_priv->regfile.saveDSPARB);
@@ -61,15 +73,10 @@ static void i915_restore_display(struct drm_i915_private *dev_priv)
 
 int i915_save_state(struct drm_i915_private *dev_priv)
 {
-	struct pci_dev *pdev = dev_priv->drm.pdev;
 	int i;
 
 	i915_save_display(dev_priv);
 
-	if (IS_GEN(dev_priv, 4))
-		pci_read_config_word(pdev, GCDGMBUS,
-				     &dev_priv->regfile.saveGCDGMBUS);
-
 	/* Cache mode state */
 	if (INTEL_GEN(dev_priv) < 7)
 		dev_priv->regfile.saveCACHE_MODE_0 = I915_READ(CACHE_MODE_0);
@@ -102,12 +109,8 @@ int i915_save_state(struct drm_i915_private *dev_priv)
 
 int i915_restore_state(struct drm_i915_private *dev_priv)
 {
-	struct pci_dev *pdev = dev_priv->drm.pdev;
 	int i;
 
-	if (IS_GEN(dev_priv, 4))
-		pci_write_config_word(pdev, GCDGMBUS,
-				      dev_priv->regfile.saveGCDGMBUS);
 	i915_restore_display(dev_priv);
 
 	/* Cache mode state */
-- 
2.20.1

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  reply	other threads:[~2020-09-10  9:52 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-09-10  9:52 [Intel-gfx] [PATCH 1/3] drm/i915: disable all display features when no display Jani Nikula
2020-09-10  9:52 ` Jani Nikula [this message]
2020-09-10 10:46   ` [Intel-gfx] [PATCH 2/3] drm/i915: move gen4 GCDGMBUS save/restore to display save/restore Ville Syrjälä
2020-09-10  9:52 ` [Intel-gfx] [PATCH 3/3] drm/i915: move gmbus restore to i915_restore_display Jani Nikula
2020-09-10 10:50   ` Ville Syrjälä
2020-09-10 10:02 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/3] drm/i915: disable all display features when no display Patchwork
2020-09-10 10:28 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-09-10 10:44 ` [Intel-gfx] [PATCH 1/3] " Ville Syrjälä
2020-09-11 11:02   ` Jani Nikula
2020-09-10 11:27 ` [Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/3] " Patchwork
2020-09-10 14:51 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/3] drm/i915: disable all display features when no display (rev2) Patchwork
2020-09-10 15:15 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-09-10 16:57 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork

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