From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-10.3 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,MENTIONS_GIT_HOSTING, SPF_HELO_NONE,SPF_PASS,USER_AGENT_SANE_2 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 89853C433E2 for ; Mon, 14 Sep 2020 08:14:31 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 442DC217BA for ; Mon, 14 Sep 2020 08:14:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726230AbgININ7 (ORCPT ); Mon, 14 Sep 2020 04:13:59 -0400 Received: from lhrrgout.huawei.com ([185.176.76.210]:2810 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726187AbgINIGk (ORCPT ); Mon, 14 Sep 2020 04:06:40 -0400 Received: from lhreml710-chm.china.huawei.com (unknown [172.18.7.107]) by Forcepoint Email with ESMTP id 82ED0EA4F23BCF2D226D; Mon, 14 Sep 2020 09:06:25 +0100 (IST) Received: from localhost (10.52.126.156) by lhreml710-chm.china.huawei.com (10.201.108.61) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1913.5; Mon, 14 Sep 2020 09:06:24 +0100 Date: Mon, 14 Sep 2020 09:04:48 +0100 From: Jonathan Cameron To: Atish Patra CC: , Albert Ou , Andrew Morton , Anshuman Khandual , Anup Patel , "Arnd Bergmann" , Catalin Marinas , "David Hildenbrand" , Greentime Hu , Bjorn Helgaas , Greg Kroah-Hartman , Jia He , , , "Mike Rapoport" , Nicolas Saenz Julienne , Palmer Dabbelt , "Paul Walmsley" , "Rafael J. Wysocki" , Steven Price , Will Deacon , Zong Li Subject: Re: [RFC/RFT PATCH v2 0/5] Unify NUMA implementation between ARM64 & RISC-V Message-ID: <20200914090448.00001f7f@Huawei.com> In-Reply-To: <20200912013441.9730-1-atish.patra@wdc.com> References: <20200912013441.9730-1-atish.patra@wdc.com> Organization: Huawei Technologies Research and Development (UK) Ltd. X-Mailer: Claws Mail 3.17.4 (GTK+ 2.24.32; i686-w64-mingw32) MIME-Version: 1.0 Content-Type: text/plain; charset="US-ASCII" Content-Transfer-Encoding: 7bit X-Originating-IP: [10.52.126.156] X-ClientProxiedBy: lhreml717-chm.china.huawei.com (10.201.108.68) To lhreml710-chm.china.huawei.com (10.201.108.61) X-CFilter-Loop: Reflected Sender: linux-arch-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arch@vger.kernel.org On Fri, 11 Sep 2020 18:34:36 -0700 Atish Patra wrote: Hi Atish, I'm not seeing a change log from v1. Putting one in makes it easier for people who reviewed v1 to remember what to look for when looking at v2. Either here, or individual patches after the --- is fine. Thanks, Jonathan > This series attempts to move the ARM64 numa implementation to common > code so that RISC-V can leverage that as well instead of reimplementing > it again. > > RISC-V specific bits are based on initial work done by Greentime Hu [1] but > modified to reuse the common implementation to avoid duplication. > > [1] https://lkml.org/lkml/2020/1/10/233 > > This series has been tested on qemu with numa enabled for both RISC-V & ARM64. > It would be great if somebody can test it on numa capable ARM64 hardware platforms. > This patch series doesn't modify the maintainers list for the common code (arch_numa) > as I am not sure if somebody from ARM64 community or Greg should take up the > maintainership. Ganapatrao was the original author of the arm64 version. > I would be happy to update that in the next revision once it is decided. > > # numactl --hardware > available: 2 nodes (0-1) > node 0 cpus: 0 1 2 3 > node 0 size: 486 MB > node 0 free: 470 MB > node 1 cpus: 4 5 6 7 > node 1 size: 424 MB > node 1 free: 408 MB > node distances: > node 0 1 > 0: 10 20 > 1: 20 10 > # numactl -show > policy: default > preferred node: current > physcpubind: 0 1 2 3 4 5 6 7 > cpubind: 0 1 > nodebind: 0 1 > membind: 0 1 > > For RISC-V, the following qemu series is a pre-requisite(already available in upstream) > to test the patches in Qemu and 2 socket OmniXtend FPGA. > > https://patchwork.kernel.org/project/qemu-devel/list/?series=303313 > > The patches are also available at > > https://github.com/atishp04/linux/tree/5.10_numa_unified_v2 > > There may be some minor conflicts with Mike's cleanup series [2] depending on the > order in which these two series are being accepted. I can rebase on top his series > if required. > > [2] https://lkml.org/lkml/2020/8/18/754 > > Atish Patra (4): > numa: Move numa implementation to common code > arm64, numa: Change the numa init function name to be generic > riscv: Separate memory init from paging init > riscv: Add numa support for riscv64 platform > > Greentime Hu (1): > riscv: Add support pte_protnone and pmd_protnone if > CONFIG_NUMA_BALANCING > > arch/arm64/Kconfig | 1 + > arch/arm64/include/asm/numa.h | 45 +---------------- > arch/arm64/kernel/acpi_numa.c | 13 ----- > arch/arm64/mm/Makefile | 1 - > arch/arm64/mm/init.c | 4 +- > arch/riscv/Kconfig | 31 +++++++++++- > arch/riscv/include/asm/mmzone.h | 13 +++++ > arch/riscv/include/asm/numa.h | 8 +++ > arch/riscv/include/asm/pci.h | 14 ++++++ > arch/riscv/include/asm/pgtable.h | 21 ++++++++ > arch/riscv/kernel/setup.c | 11 ++++- > arch/riscv/kernel/smpboot.c | 12 ++++- > arch/riscv/mm/init.c | 10 +++- > drivers/base/Kconfig | 6 +++ > drivers/base/Makefile | 1 + > .../mm/numa.c => drivers/base/arch_numa.c | 29 +++++++++-- > include/asm-generic/numa.h | 49 +++++++++++++++++++ > 17 files changed, 200 insertions(+), 69 deletions(-) > create mode 100644 arch/riscv/include/asm/mmzone.h > create mode 100644 arch/riscv/include/asm/numa.h > rename arch/arm64/mm/numa.c => drivers/base/arch_numa.c (95%) > create mode 100644 include/asm-generic/numa.h > > -- > 2.24.0 > From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.0 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, MENTIONS_GIT_HOSTING,SPF_HELO_NONE,SPF_PASS,USER_AGENT_SANE_2 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0A848C2BC11 for ; Mon, 14 Sep 2020 08:07:13 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 8E46C21741 for ; Mon, 14 Sep 2020 08:07:12 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="xVRSXAq3" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 8E46C21741 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=Huawei.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Message-ID: Subject:To:From:Date:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=D5Py5Ltp7lU/5USV/73IAfXins5wnQeIoH8G8XD7rnQ=; b=xVRSXAq3laxQHnhql4G0KsXtm rGk3DkEKX08VRePHOvaM1BhleGKcbA6VU5zR9mBCzWlXxp5wTXTlDx/o3JKeOK7hz4lyaFOcRJuIY D25puejmfUiwZWreehfQBf/J/B+YJGGlncB0rMAoenKnzU0SjaMDXB0L5oau6QSxQQKC6GObZrfNp 4pNZ74HsNpkMcmR10Ver7vximAf4cfxYI435zzEhjexnB217rAeqpFLuDV5sgD56zZHjor51F4AO+ j4B2v6vmS6s7JPjJxFcBb/q92ndZ7CMDj5WOeh7pTGn5lkv2OAKtfBh1qa/RcKJYaaWnK1zoIcWQl 4EtYaG5qQ==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kHjVl-00063t-T4; Mon, 14 Sep 2020 08:06:53 +0000 Received: from lhrrgout.huawei.com ([185.176.76.210] helo=huawei.com) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1kHjVU-0005sW-Lj for linux-riscv@lists.infradead.org; Mon, 14 Sep 2020 08:06:41 +0000 Received: from lhreml710-chm.china.huawei.com (unknown [172.18.7.107]) by Forcepoint Email with ESMTP id 82ED0EA4F23BCF2D226D; Mon, 14 Sep 2020 09:06:25 +0100 (IST) Received: from localhost (10.52.126.156) by lhreml710-chm.china.huawei.com (10.201.108.61) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1913.5; Mon, 14 Sep 2020 09:06:24 +0100 Date: Mon, 14 Sep 2020 09:04:48 +0100 From: Jonathan Cameron To: Atish Patra Subject: Re: [RFC/RFT PATCH v2 0/5] Unify NUMA implementation between ARM64 & RISC-V Message-ID: <20200914090448.00001f7f@Huawei.com> In-Reply-To: <20200912013441.9730-1-atish.patra@wdc.com> References: <20200912013441.9730-1-atish.patra@wdc.com> Organization: Huawei Technologies Research and Development (UK) Ltd. X-Mailer: Claws Mail 3.17.4 (GTK+ 2.24.32; i686-w64-mingw32) MIME-Version: 1.0 X-Originating-IP: [10.52.126.156] X-ClientProxiedBy: lhreml717-chm.china.huawei.com (10.201.108.68) To lhreml710-chm.china.huawei.com (10.201.108.61) X-CFilter-Loop: Reflected X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200914_040636_866538_D1E83DBC X-CRM114-Status: GOOD ( 25.49 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: David Hildenbrand , Catalin Marinas , Zong Li , linux-riscv@lists.infradead.org, Will Deacon , linux-arch@vger.kernel.org, Jia He , Anup Patel , "Rafael J. Wysocki" , Steven Price , Bjorn Helgaas , Greentime Hu , Albert Ou , Arnd Bergmann , Anshuman Khandual , Paul Walmsley , Greg Kroah-Hartman , linux-kernel@vger.kernel.org, Palmer Dabbelt , Mike Rapoport , Andrew Morton , Nicolas Saenz Julienne Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Fri, 11 Sep 2020 18:34:36 -0700 Atish Patra wrote: Hi Atish, I'm not seeing a change log from v1. Putting one in makes it easier for people who reviewed v1 to remember what to look for when looking at v2. Either here, or individual patches after the --- is fine. Thanks, Jonathan > This series attempts to move the ARM64 numa implementation to common > code so that RISC-V can leverage that as well instead of reimplementing > it again. > > RISC-V specific bits are based on initial work done by Greentime Hu [1] but > modified to reuse the common implementation to avoid duplication. > > [1] https://lkml.org/lkml/2020/1/10/233 > > This series has been tested on qemu with numa enabled for both RISC-V & ARM64. > It would be great if somebody can test it on numa capable ARM64 hardware platforms. > This patch series doesn't modify the maintainers list for the common code (arch_numa) > as I am not sure if somebody from ARM64 community or Greg should take up the > maintainership. Ganapatrao was the original author of the arm64 version. > I would be happy to update that in the next revision once it is decided. > > # numactl --hardware > available: 2 nodes (0-1) > node 0 cpus: 0 1 2 3 > node 0 size: 486 MB > node 0 free: 470 MB > node 1 cpus: 4 5 6 7 > node 1 size: 424 MB > node 1 free: 408 MB > node distances: > node 0 1 > 0: 10 20 > 1: 20 10 > # numactl -show > policy: default > preferred node: current > physcpubind: 0 1 2 3 4 5 6 7 > cpubind: 0 1 > nodebind: 0 1 > membind: 0 1 > > For RISC-V, the following qemu series is a pre-requisite(already available in upstream) > to test the patches in Qemu and 2 socket OmniXtend FPGA. > > https://patchwork.kernel.org/project/qemu-devel/list/?series=303313 > > The patches are also available at > > https://github.com/atishp04/linux/tree/5.10_numa_unified_v2 > > There may be some minor conflicts with Mike's cleanup series [2] depending on the > order in which these two series are being accepted. I can rebase on top his series > if required. > > [2] https://lkml.org/lkml/2020/8/18/754 > > Atish Patra (4): > numa: Move numa implementation to common code > arm64, numa: Change the numa init function name to be generic > riscv: Separate memory init from paging init > riscv: Add numa support for riscv64 platform > > Greentime Hu (1): > riscv: Add support pte_protnone and pmd_protnone if > CONFIG_NUMA_BALANCING > > arch/arm64/Kconfig | 1 + > arch/arm64/include/asm/numa.h | 45 +---------------- > arch/arm64/kernel/acpi_numa.c | 13 ----- > arch/arm64/mm/Makefile | 1 - > arch/arm64/mm/init.c | 4 +- > arch/riscv/Kconfig | 31 +++++++++++- > arch/riscv/include/asm/mmzone.h | 13 +++++ > arch/riscv/include/asm/numa.h | 8 +++ > arch/riscv/include/asm/pci.h | 14 ++++++ > arch/riscv/include/asm/pgtable.h | 21 ++++++++ > arch/riscv/kernel/setup.c | 11 ++++- > arch/riscv/kernel/smpboot.c | 12 ++++- > arch/riscv/mm/init.c | 10 +++- > drivers/base/Kconfig | 6 +++ > drivers/base/Makefile | 1 + > .../mm/numa.c => drivers/base/arch_numa.c | 29 +++++++++-- > include/asm-generic/numa.h | 49 +++++++++++++++++++ > 17 files changed, 200 insertions(+), 69 deletions(-) > create mode 100644 arch/riscv/include/asm/mmzone.h > create mode 100644 arch/riscv/include/asm/numa.h > rename arch/arm64/mm/numa.c => drivers/base/arch_numa.c (95%) > create mode 100644 include/asm-generic/numa.h > > -- > 2.24.0 > _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv