From: Rob Herring <robh@kernel.org>
To: Zhen Lei <thunder.leizhen@huawei.com>
Cc: Thomas Gleixner <tglx@linutronix.de>,
Jason Cooper <jason@lakedaemon.net>,
Marc Zyngier <maz@kernel.org>,
devicetree <devicetree@vger.kernel.org>,
linux-kernel <linux-kernel@vger.kernel.org>,
Kefeng Wang <wangkefeng.wang@huawei.com>
Subject: Re: [PATCH 1/2] dt-bindings: interrupt-controller: add Hisilicon SD5203 vector interrupt controller
Date: Mon, 14 Sep 2020 14:31:10 -0600 [thread overview]
Message-ID: <20200914203110.GA185427@bogus> (raw)
In-Reply-To: <20200903120504.2308-2-thunder.leizhen@huawei.com>
On Thu, Sep 03, 2020 at 08:05:03PM +0800, Zhen Lei wrote:
> Add DT bindings for the Hisilicon SD5203 vector interrupt controller.
>
> Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com>
> ---
> .../hisilicon,sd5203-vic.txt | 27 +++++++++++++++++++
Bindings should be in DT schema format now.
> 1 file changed, 27 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/interrupt-controller/hisilicon,sd5203-vic.txt
>
> diff --git a/Documentation/devicetree/bindings/interrupt-controller/hisilicon,sd5203-vic.txt b/Documentation/devicetree/bindings/interrupt-controller/hisilicon,sd5203-vic.txt
> new file mode 100644
> index 000000000000..a08292e868b0
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/interrupt-controller/hisilicon,sd5203-vic.txt
> @@ -0,0 +1,27 @@
> +Hisilicon SD5203 vector interrupt controller (VIC)
> +
> +Hisilicon SD5203 VIC based on Synopsys DesignWare APB interrupt controller, but
> +there's something special:
> +1. The maximum number of irqs supported is 32. The registers ENABLE, MASK and
> + FINALSTATUS are 32 bits.
> +2. There is only one VIC, it's used as primary interrupt controller.
> +
> +Required properties:
> +- compatible: shall be "hisilicon,sd5203-vic"
> +- reg: physical base address of the controller and length of memory mapped
> + region starting with ENABLE_LOW register
> +- interrupt-controller: identifies the node as an interrupt controller
> +- #interrupt-cells: number of cells to encode an interrupt-specifier, shall be 1
> +
> +The interrupt sources map to the corresponding bits in the interrupt
> +registers, i.e.
> +- 0 maps to bit 0 of low interrupts,
> +- 1 maps to bit 1 of low interrupts,
> +
> +Example:
> + vic: interrupt-controller@10130000 {
> + compatible = "hisilicon,sd5203-vic";
> + reg = <0x10130000 0x1000>;
> + interrupt-controller;
> + #interrupt-cells = <1>;
> + };
> --
> 2.26.0.106.g9fadedd
>
>
next prev parent reply other threads:[~2020-09-14 20:31 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-09-03 12:05 [PATCH 0/2] add support for Hisilicon SD5203 vector interrupt controller Zhen Lei
2020-09-03 12:05 ` [PATCH 1/2] dt-bindings: interrupt-controller: add " Zhen Lei
2020-09-14 20:31 ` Rob Herring [this message]
2020-09-15 6:12 ` Leizhen (ThunderTown)
2020-09-17 3:30 ` Leizhen (ThunderTown)
2020-09-18 18:55 ` Rob Herring
2020-09-19 2:02 ` Leizhen (ThunderTown)
2020-09-03 12:05 ` [PATCH 2/2] irqchip: " Zhen Lei
2020-09-03 16:46 ` [PATCH 0/2] add support for " Marc Zyngier
2020-09-04 4:57 ` Leizhen (ThunderTown)
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