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From: Sean Christopherson <sean.j.christopherson@intel.com>
To: Paolo Bonzini <pbonzini@redhat.com>
Cc: Sasha Levin <sashal@kernel.org>,
	stable@vger.kernel.org, Liran Alon <liran.alon@oracle.com>
Subject: Re: [PATCH] KVM: nVMX: Morph notification vector IRQ on nested VM-Enter to pending PI
Date: Wed, 23 Sep 2020 08:49:33 -0700	[thread overview]
Message-ID: <20200923154933.GA31972@linux.intel.com> (raw)
In-Reply-To: <454c167d-687a-d4cb-3170-b32886904739@redhat.com>

On Wed, Sep 23, 2020 at 04:44:01PM +0200, Paolo Bonzini wrote:
> Queued, thanks.
> 
> I cannot think of a "nicer" way to do this, we could perhaps move
> 
> +		vmx->nested.pi_pending = true;
> +		kvm_make_request(KVM_REQ_EVENT, vcpu);
> +		kvm_apic_clear_irr(vcpu, vmx->nested.posted_intr_nv);
> 
> to a separate function (possibly with the IRR clear made conditional, so
> that we can reuse the function for regular posted interrupt injection)
> but that is it.

Ya, I played around with similar approaches and didn't particular like any
of them :-/

For the record, I suspect there may be additional issues with a doubly nested
scenario, i.e. when running L3 and L2 is using the self-IPI method for
triggering posted interrupts.  I sort of tested once, and it appeared to be
broken, but it's entirely possible that there was an issue somewhere else in
my stack (L0, L1 and L2 all had non-trivial KVM changes), and I haven't yet
had time to dig in.  That, and I suspect I'm the only person that would care
about L3 functioning properly in this scenario :-)

  reply	other threads:[~2020-09-23 15:49 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-08-12 17:51 [PATCH] KVM: nVMX: Morph notification vector IRQ on nested VM-Enter to pending PI Sean Christopherson
2020-08-19 23:56 ` Sasha Levin
2020-08-26 13:54 ` Sasha Levin
2020-09-23 14:44   ` Paolo Bonzini
2020-09-23 15:49     ` Sean Christopherson [this message]
2020-10-06 17:36 ` Jim Mattson
2020-10-06 18:35   ` Sean Christopherson
2020-10-06 21:22     ` Oliver Upton

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