From: Thierry Reding <thierry.reding@gmail.com>
To: JC Kuo <jckuo@nvidia.com>
Cc: gregkh@linuxfoundation.org, robh@kernel.org,
jonathanh@nvidia.com, kishon@ti.com, linux-tegra@vger.kernel.org,
linux-usb@vger.kernel.org, linux-kernel@vger.kernel.org,
devicetree@vger.kernel.org, nkristam@nvidia.com
Subject: Re: [PATCH v3 05/15] phy: tegra: xusb: Rearrange UPHY init on Tegra210
Date: Mon, 28 Sep 2020 15:08:49 +0200 [thread overview]
Message-ID: <20200928130849.GF3065790@ulmo> (raw)
In-Reply-To: <20200909081041.3190157-6-jckuo@nvidia.com>
[-- Attachment #1: Type: text/plain, Size: 1540 bytes --]
On Wed, Sep 09, 2020 at 04:10:31PM +0800, JC Kuo wrote:
> This commit is a preparation for enabling XUSB SC7 support.
> It rearranges Tegra210 XUSB PADCTL UPHY initialization sequence,
> for the following reasons:
>
> 1. PLLE hardware power sequencer has to be enabled only after both
> PEX UPHY PLL and SATA UPHY PLL are initialized.
> tegra210_uphy_init() -> tegra210_pex_uphy_enable()
> -> tegra210_sata_uphy_enable()
> -> tegra210_plle_hw_sequence_start()
> -> tegra210_aux_mux_lp0_clamp_disable()
>
> 2. At cold boot and SC7 exit, the following bits must be cleared after
> PEX/SATA lanes are out of IDDQ (IDDQ_DISABLE=1).
> a. XUSB_PADCTL_ELPG_PROGRAM1_AUX_MUX_LP0_CLAMP_EN,
> b. XUSB_PADCTL_ELPG_PROGRAM1_AUX_MUX_LP0_CLAMP_EN_EARLY
> c. XUSB_PADCTL_ELPG_PROGRAM1_AUX_MUX_LP0_VCORE_DOWN
>
> tegra210_pex_uphy_enable() and tegra210_sata_uphy_enable() are in
> charge of bringing lanes out of IDDQ, and then AUX_MUX_LP0_* bits
> will be cleared by tegra210_aux_mux_lp0_clamp_disable().
>
> Signed-off-by: JC Kuo <jckuo@nvidia.com>
> ---
> v3:
> make separate changes
> use "unsigned int" instead "int" type for PHY index
> add blank line for better readability
>
> drivers/phy/tegra/xusb-tegra210.c | 203 +++++++++++++++---------------
> drivers/phy/tegra/xusb.h | 4 +-
> 2 files changed, 102 insertions(+), 105 deletions(-)
Acked-by: Thierry Reding <treding@nvidia.com>
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
next prev parent reply other threads:[~2020-09-28 13:09 UTC|newest]
Thread overview: 40+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-09-09 8:10 [PATCH v3 00/15] Tegra XHCI controller ELPG support JC Kuo
2020-09-09 8:10 ` [PATCH v3 01/15] clk: tegra: Add PLLE HW power sequencer control JC Kuo
2020-09-28 12:51 ` Thierry Reding
2020-09-09 8:10 ` [PATCH v3 02/15] clk: tegra: Don't enable PLLE HW sequencer at init JC Kuo
2020-09-28 12:52 ` Thierry Reding
2020-09-09 8:10 ` [PATCH v3 03/15] phy: tegra: xusb: Move usb3 port init for Tegra210 JC Kuo
2020-09-28 13:03 ` Thierry Reding
2020-09-09 8:10 ` [PATCH v3 04/15] phy: tegra: xusb: tegra210: Do not reset UPHY PLL JC Kuo
2020-09-28 13:06 ` Thierry Reding
2020-10-14 3:21 ` JC Kuo
2020-09-09 8:10 ` [PATCH v3 05/15] phy: tegra: xusb: Rearrange UPHY init on Tegra210 JC Kuo
2020-09-28 13:08 ` Thierry Reding [this message]
2020-09-09 8:10 ` [PATCH v3 06/15] phy: tegra: xusb: Add Tegra210 lane_iddq operation JC Kuo
2020-09-28 13:10 ` Thierry Reding
2020-09-09 8:10 ` [PATCH v3 07/15] phy: tegra: xusb: Add sleepwalk and suspend/resume JC Kuo
2020-09-28 13:11 ` Thierry Reding
2020-09-09 8:10 ` [PATCH v3 08/15] soc/tegra: pmc: Provide usb sleepwalk register map JC Kuo
2020-09-28 13:17 ` Thierry Reding
2020-10-14 4:08 ` JC Kuo
2020-09-09 8:10 ` [PATCH v3 09/15] arm64: tegra210: XUSB PADCTL add "nvidia,pmc" prop JC Kuo
2020-09-28 13:18 ` Thierry Reding
2020-10-14 4:15 ` JC Kuo
2020-09-09 8:10 ` [PATCH v3 10/15] phy: tegra: xusb: Add wake/sleepwalk for Tegra210 JC Kuo
2020-09-28 13:40 ` Thierry Reding
2020-10-14 8:37 ` JC Kuo
2020-09-09 8:10 ` [PATCH v3 11/15] phy: tegra: xusb: Tegra210 host mode VBUS control JC Kuo
2020-09-28 13:42 ` Thierry Reding
2020-09-09 8:10 ` [PATCH v3 12/15] phy: tegra: xusb: Add wake/sleepwalk for Tegra186 JC Kuo
2020-09-28 13:50 ` Thierry Reding
2020-10-15 8:08 ` JC Kuo
2020-09-09 8:10 ` [PATCH v3 13/15] arm64: tegra210/tegra186/tegra194: XUSB PADCTL irq JC Kuo
2020-09-09 8:10 ` [PATCH v3 14/15] usb: host: xhci-tegra: Unlink power domain devices JC Kuo
2020-09-28 13:53 ` Thierry Reding
2020-10-15 8:09 ` JC Kuo
2020-09-09 8:10 ` [PATCH v3 15/15] xhci: tegra: Enable ELPG for runtime/system PM JC Kuo
2020-09-10 12:06 ` kernel test robot
2020-09-28 14:06 ` Thierry Reding
2020-10-15 8:12 ` JC Kuo
2020-09-28 12:54 ` [PATCH v3 00/15] Tegra XHCI controller ELPG support Thierry Reding
2020-10-14 2:26 ` JC Kuo
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20200928130849.GF3065790@ulmo \
--to=thierry.reding@gmail.com \
--cc=devicetree@vger.kernel.org \
--cc=gregkh@linuxfoundation.org \
--cc=jckuo@nvidia.com \
--cc=jonathanh@nvidia.com \
--cc=kishon@ti.com \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-tegra@vger.kernel.org \
--cc=linux-usb@vger.kernel.org \
--cc=nkristam@nvidia.com \
--cc=robh@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.