From: Orson Zhai <orsonzhai@gmail.com>
To: Catalin Marinas <catalin.marinas@arm.com>
Cc: linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH 0/4] arm: Privileged no-access for LPAE
Date: Mon, 28 Sep 2020 21:09:07 +0800 [thread overview]
Message-ID: <20200928130907.GA5484@lenovo> (raw)
In-Reply-To: <20151211172140.GQ26759@e104818-lin.cambridge.arm.com>
Hi Catalin,
On Fri, Dec 11, 2015 at 05:21:40PM +0000, Catalin Marinas wrote:
> On Thu, Dec 10, 2015 at 11:40:44AM -0800, Kees Cook wrote:
> > [thread necromancy]
> >
> > This series looks good to me. I'd love to see it accepted. At the very
> > least the cleanups look like no-brainers. :)
> >
> > Please consider the series:
> >
> > Reviewed-by: Kees Cook <keescook@chromium.org>
> >
> > Thanks for working on it!
>
> Thanks for the review. After some more (internal) discussions around
> these patches, I need to get clarification on the architecture whether
> changing the TTBCR.A1 bit is enough to guarantee an ASID change (I do
Did you check it after then? Now I have a real requirement for implementing
LPAE and PAN at the same time. So I'd like to know if this patch could work.
I had some talk with Will about it at other place. He thought this patch is
not in correct state.
May I have your latest opinions?
Thanks.
-Orson
> this trick to change to the reserved ASID and avoid TLB invalidation as
> normally required by changes to translation control registers). If
> that's not allowed by the architecture, I would have to change the
> patches to switch to a reserved TTBR0 rather than disabling TTBR0 walks
> at the TTBCR level.
>
> --
> Catalin
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next prev parent reply other threads:[~2020-09-28 13:11 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-09-23 14:24 [PATCH 0/4] arm: Privileged no-access for LPAE Catalin Marinas
2015-09-23 14:24 ` [PATCH 1/4] arm: kvm: Move TTBCR_* definitions from kvm_arm.h into pgtable-3level-hwdef.h Catalin Marinas
2015-09-23 14:24 ` [PATCH 2/4] arm: Move asm statements accessing TTBCR into dedicated functions Catalin Marinas
2015-09-23 14:24 ` [PATCH 3/4] arm: Reduce the number of #ifdef CONFIG_CPU_SW_DOMAIN_PAN Catalin Marinas
2015-09-23 14:24 ` [PATCH 4/4] arm: Implement privileged no-access using TTBR0 page table walks disabling Catalin Marinas
2015-12-10 19:40 ` [kernel-hardening] Re: [PATCH 0/4] arm: Privileged no-access for LPAE Kees Cook
2015-12-10 19:40 ` Kees Cook
2015-12-11 17:21 ` [kernel-hardening] " Catalin Marinas
2015-12-11 17:21 ` Catalin Marinas
2020-09-28 13:09 ` Orson Zhai [this message]
2020-09-28 16:29 ` Catalin Marinas
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