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X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, yong.liang@mediatek.com, stanley.chu@mediatek.com, srv_heupstream@mediatek.com, seiya.wang@mediatek.com, linux-kernel@vger.kernel.org, fan.chen@mediatek.com, linux-mediatek@lists.infradead.org, yingjoe.chen@mediatek.com, s-anna@ti.com, linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org v6: fix the format error of mediatek-syscon-reset.yaml v5: 1. revert ti-syscon-reset.txt, and add a new mediatek reset binding. 2. split the patch [v4, 3/4] with the change to force write and the change to integrate assert and deassert together. 3. separate the dts patch from this patch sets v4: fix typos on v3 commit message. v3: 1. revert v2 changes. 2. add 'reset-duration-us' property to declare a minimum delay, which needs to be waited between assert and deassert. 3. add 'mediatek,infra-reset' to compatible. v2 changes: https://patchwork.kernel.org/patch/11697371/ 1. add 'assert-deassert-together' property to introduce a new reset handler, which allows device to do serialized assert and deassert operations in a single step by 'reset' method. 2. add 'update-force' property to introduce force-update method, which forces the write operation in case the read already happens to return the correct value. 3. add 'generic-reset' to compatible v1 changes: https://patchwork.kernel.org/patch/11690523/ https://patchwork.kernel.org/patch/11690527/ Crystal Guo (3): dt-binding: reset-controller: mediatek: add YAML schemas reset-controller: ti: introduce a new reset handler reset-controller: ti: force the write operation when assert or deassert .../bindings/reset/mediatek-syscon-reset.yaml | 51 +++++++++++++++++++ drivers/reset/reset-ti-syscon.c | 44 ++++++++++++++-- 2 files changed, 92 insertions(+), 3 deletions(-) create mode 100644 Documentation/devicetree/bindings/reset/mediatek-syscon-reset.yaml _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.5 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY,URIBL_BLOCKED,USER_AGENT_GIT autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 66424C4727C for ; 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Wed, 30 Sep 2020 10:22:02 +0800 Received: from localhost.localdomain (10.17.3.153) by mtkcas08.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 30 Sep 2020 10:22:01 +0800 From: Crystal Guo To: , , Subject: [v6,0/3] introduce TI reset controller for MT8192 SoC Date: Wed, 30 Sep 2020 10:21:56 +0800 Message-ID: <20200930022159.5559-1-crystal.guo@mediatek.com> X-Mailer: git-send-email 2.18.0 MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200929_223208_545549_DE886BF7 X-CRM114-Status: UNSURE ( 9.60 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, yong.liang@mediatek.com, stanley.chu@mediatek.com, srv_heupstream@mediatek.com, seiya.wang@mediatek.com, linux-kernel@vger.kernel.org, fan.chen@mediatek.com, linux-mediatek@lists.infradead.org, yingjoe.chen@mediatek.com, linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org v6: fix the format error of mediatek-syscon-reset.yaml v5: 1. revert ti-syscon-reset.txt, and add a new mediatek reset binding. 2. split the patch [v4, 3/4] with the change to force write and the change to integrate assert and deassert together. 3. separate the dts patch from this patch sets v4: fix typos on v3 commit message. v3: 1. revert v2 changes. 2. add 'reset-duration-us' property to declare a minimum delay, which needs to be waited between assert and deassert. 3. add 'mediatek,infra-reset' to compatible. v2 changes: https://patchwork.kernel.org/patch/11697371/ 1. add 'assert-deassert-together' property to introduce a new reset handler, which allows device to do serialized assert and deassert operations in a single step by 'reset' method. 2. add 'update-force' property to introduce force-update method, which forces the write operation in case the read already happens to return the correct value. 3. add 'generic-reset' to compatible v1 changes: https://patchwork.kernel.org/patch/11690523/ https://patchwork.kernel.org/patch/11690527/ Crystal Guo (3): dt-binding: reset-controller: mediatek: add YAML schemas reset-controller: ti: introduce a new reset handler reset-controller: ti: force the write operation when assert or deassert .../bindings/reset/mediatek-syscon-reset.yaml | 51 +++++++++++++++++++ drivers/reset/reset-ti-syscon.c | 44 ++++++++++++++-- 2 files changed, 92 insertions(+), 3 deletions(-) create mode 100644 Documentation/devicetree/bindings/reset/mediatek-syscon-reset.yaml _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, MIME_BASE64_TEXT,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY,USER_AGENT_GIT autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id AD36AC4727D for ; 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X-UUID: e2a1b0067cf5458cbda2c768b1c566b6-20200930 Received: from mtkcas08.mediatek.inc [(172.21.101.126)] by mailgw02.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.14 Build 0819 with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1755378119; Wed, 30 Sep 2020 10:22:02 +0800 Received: from mtkcas08.mediatek.inc (172.21.101.126) by mtkmbs07n2.mediatek.inc (172.21.101.141) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 30 Sep 2020 10:22:02 +0800 Received: from localhost.localdomain (10.17.3.153) by mtkcas08.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 30 Sep 2020 10:22:01 +0800 From: Crystal Guo To: , , CC: , , , , , , , , , , Subject: [v6,0/3] introduce TI reset controller for MT8192 SoC Date: Wed, 30 Sep 2020 10:21:56 +0800 Message-ID: <20200930022159.5559-1-crystal.guo@mediatek.com> X-Mailer: git-send-email 2.18.0 MIME-Version: 1.0 Content-Type: text/plain X-MTK: N Content-Transfer-Encoding: base64 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org djY6DQpmaXggdGhlIGZvcm1hdCBlcnJvciBvZiBtZWRpYXRlay1zeXNjb24tcmVzZXQueWFtbA0K DQp2NToNCjEuIHJldmVydCB0aS1zeXNjb24tcmVzZXQudHh0LCBhbmQgYWRkIGEgbmV3IG1lZGlh dGVrIHJlc2V0IGJpbmRpbmcuDQoyLiBzcGxpdCB0aGUgcGF0Y2ggW3Y0LCAzLzRdIHdpdGggdGhl IGNoYW5nZSB0byBmb3JjZSB3cml0ZSBhbmQgdGhlDQpjaGFuZ2UgdG8gaW50ZWdyYXRlIGFzc2Vy dCBhbmQgZGVhc3NlcnQgdG9nZXRoZXIuDQozLiBzZXBhcmF0ZSB0aGUgZHRzIHBhdGNoIGZyb20g dGhpcyBwYXRjaCBzZXRzDQoNCnY0Og0KZml4IHR5cG9zIG9uIHYzIGNvbW1pdCBtZXNzYWdlLg0K DQp2MzoNCjEuIHJldmVydCB2MiBjaGFuZ2VzLg0KMi4gYWRkICdyZXNldC1kdXJhdGlvbi11cycg cHJvcGVydHkgdG8gZGVjbGFyZSBhIG1pbmltdW0gZGVsYXksDQp3aGljaCBuZWVkcyB0byBiZSB3 YWl0ZWQgYmV0d2VlbiBhc3NlcnQgYW5kIGRlYXNzZXJ0Lg0KMy4gYWRkICdtZWRpYXRlayxpbmZy YS1yZXNldCcgdG8gY29tcGF0aWJsZS4NCg0KdjIgY2hhbmdlczoNCmh0dHBzOi8vcGF0Y2h3b3Jr Lmtlcm5lbC5vcmcvcGF0Y2gvMTE2OTczNzEvDQoxLiBhZGQgJ2Fzc2VydC1kZWFzc2VydC10b2dl dGhlcicgcHJvcGVydHkgdG8gaW50cm9kdWNlIGEgbmV3IHJlc2V0IGhhbmRsZXIsDQp3aGljaCBh bGxvd3MgZGV2aWNlIHRvIGRvIHNlcmlhbGl6ZWQgYXNzZXJ0IGFuZCBkZWFzc2VydCBvcGVyYXRp b25zIGluIGEgc2luZ2xlDQpzdGVwIGJ5ICdyZXNldCcgbWV0aG9kLg0KMi4gYWRkICd1cGRhdGUt Zm9yY2UnIHByb3BlcnR5IHRvIGludHJvZHVjZSBmb3JjZS11cGRhdGUgbWV0aG9kLCB3aGljaCBm b3JjZXMNCnRoZSB3cml0ZSBvcGVyYXRpb24gaW4gY2FzZSB0aGUgcmVhZCBhbHJlYWR5IGhhcHBl bnMgdG8gcmV0dXJuIHRoZSBjb3JyZWN0IHZhbHVlLg0KMy4gYWRkICdnZW5lcmljLXJlc2V0JyB0 byBjb21wYXRpYmxlDQoNCnYxIGNoYW5nZXM6DQpodHRwczovL3BhdGNod29yay5rZXJuZWwub3Jn L3BhdGNoLzExNjkwNTIzLw0KaHR0cHM6Ly9wYXRjaHdvcmsua2VybmVsLm9yZy9wYXRjaC8xMTY5 MDUyNy8NCg0KQ3J5c3RhbCBHdW8gKDMpOg0KICBkdC1iaW5kaW5nOiByZXNldC1jb250cm9sbGVy OiBtZWRpYXRlazogYWRkIFlBTUwgc2NoZW1hcw0KICByZXNldC1jb250cm9sbGVyOiB0aTogaW50 cm9kdWNlIGEgbmV3IHJlc2V0IGhhbmRsZXINCiAgcmVzZXQtY29udHJvbGxlcjogdGk6IGZvcmNl IHRoZSB3cml0ZSBvcGVyYXRpb24gd2hlbiBhc3NlcnQgb3INCiAgICBkZWFzc2VydA0KDQogLi4u L2JpbmRpbmdzL3Jlc2V0L21lZGlhdGVrLXN5c2Nvbi1yZXNldC55YW1sIHwgNTEgKysrKysrKysr KysrKysrKysrKw0KIGRyaXZlcnMvcmVzZXQvcmVzZXQtdGktc3lzY29uLmMgICAgICAgICAgICAg ICB8IDQ0ICsrKysrKysrKysrKysrLS0NCiAyIGZpbGVzIGNoYW5nZWQsIDkyIGluc2VydGlvbnMo KyksIDMgZGVsZXRpb25zKC0pDQogY3JlYXRlIG1vZGUgMTAwNjQ0IERvY3VtZW50YXRpb24vZGV2 aWNldHJlZS9iaW5kaW5ncy9yZXNldC9tZWRpYXRlay1zeXNjb24tcmVzZXQueWFtbA0KDQoNCg==