From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-11.2 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BD046C4727C for ; Thu, 1 Oct 2020 09:54:27 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 65367208B8 for ; Thu, 1 Oct 2020 09:54:27 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="g0x7GHBg" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 65367208B8 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References:Message-ID: Subject:To:From:Date:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=/7X3lnZy8rWjvnivmIn5relzH5GOmJbNgOOa59urIjo=; b=g0x7GHBgQIipK4ct4JUcTwaIw SM+dyp7OLnDYrPSIwq13odLUa4dQOlwB8fjLiTsYyCy535YFXsTag86e5412Y/a3FGf/nrnZfrIWb EDrhh+LHzHnmcOj8ZyBkov02A5kzA1LuK2mJs5nnnZ5t8lnEPP3uG9IEHGdw+2KB9r4cY5oKpFFhw 4+9XFsVlrYT7OulwiQOjkRt0VZAwwP+gd4Kuucvs1zhvEfP3rACIkxpyP7gC8l6nr5cEtgS93qNw4 9CGeCJYP4i1xfqgEjnx+9Buv2/uNeLu6p9f+PDeSKAbmUfl1E7yUPSvFGiylIdivyYX+r8ApYP7Al ReREOgHxg==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kNvGl-000857-2g; Thu, 01 Oct 2020 09:52:59 +0000 Received: from mail.kernel.org ([198.145.29.99]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1kNvGi-00084j-Qp for linux-arm-kernel@lists.infradead.org; Thu, 01 Oct 2020 09:52:57 +0000 Received: from gaia (unknown [31.124.44.166]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 6292120780; Thu, 1 Oct 2020 09:52:54 +0000 (UTC) Date: Thu, 1 Oct 2020 10:52:52 +0100 From: Catalin Marinas To: Will Deacon Subject: Re: [PATCH] arm64: dbm: Invalidate local TLB when setting TCR_EL1.HD Message-ID: <20201001095251.GB21544@gaia> References: <20201001093920.18260-1-will@kernel.org> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20201001093920.18260-1-will@kernel.org> User-Agent: Mutt/1.10.1 (2018-07-13) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201001_055256_930877_65D5334D X-CRM114-Status: GOOD ( 19.72 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu, Oct 01, 2020 at 10:39:20AM +0100, Will Deacon wrote: > TCR_EL1.HD is permitted to be cached in a TLB, so invalidate the local > TLB after setting the bit when detected support for the feature. Although > this isn't strictly necessary, since we can happily operate with the bit > effectively clear, the current code uses an ISB in a half-hearted attempt > to make the change effective, so let's just fix that up. > > Cc: Catalin Marinas > Signed-off-by: Will Deacon > --- > arch/arm64/kernel/cpufeature.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c > index 6424584be01e..29de76046977 100644 > --- a/arch/arm64/kernel/cpufeature.c > +++ b/arch/arm64/kernel/cpufeature.c > @@ -1442,7 +1442,7 @@ static inline void __cpu_enable_hw_dbm(void) > u64 tcr = read_sysreg(tcr_el1) | TCR_HD; > > write_sysreg(tcr, tcr_el1); > - isb(); > + local_flush_tlb_all(); Is the TLBI ordered with the TCR_EL1 write or we need the ISB as well? -- Catalin _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel