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Tue, 6 Oct 2020 19:55:53 +0000 Date: Tue, 6 Oct 2020 16:55:51 -0300 From: Jason Gunthorpe To: Weihang Li CC: , , , Subject: Re: [PATCH for-next 2/3] RDMA/hns: Add new interfaces to set/clear/read fields in QPC Message-ID: <20201006195551.GA161726@nvidia.com> References: <1601458452-55263-1-git-send-email-liweihang@huawei.com> <1601458452-55263-3-git-send-email-liweihang@huawei.com> Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <1601458452-55263-3-git-send-email-liweihang@huawei.com> X-ClientProxiedBy: MN2PR05CA0046.namprd05.prod.outlook.com (2603:10b6:208:236::15) To DM6PR12MB3834.namprd12.prod.outlook.com (2603:10b6:5:14a::12) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from mlx.ziepe.ca (156.34.48.30) by MN2PR05CA0046.namprd05.prod.outlook.com (2603:10b6:208:236::15) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3455.16 via Frontend Transport; Tue, 6 Oct 2020 19:55:52 +0000 Received: from jgg by mlx with local (Exim 4.94) (envelope-from ) id 1kPt3v-000g5S-6K; Tue, 06 Oct 2020 16:55:51 -0300 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1602014158; bh=AKRTxqLGJrEYJRI40HZjpf+CSEiVSPxYLvV5hm1ZTt8=; h=ARC-Seal:ARC-Message-Signature:ARC-Authentication-Results:Date: From:To:CC:Subject:Message-ID:References:Content-Type: Content-Disposition:In-Reply-To:X-ClientProxiedBy:MIME-Version: X-MS-Exchange-MessageSentRepresentingType; b=YSADWxr1jpUBQNqsxUizI3zYTyqZlpCIhkDBophO4CatlYvOK6t++zZ5XyB9Nx8o0 kOEXbTwEPZHXR0aF3rP27O9EFWpPpdBqOr4uI71KVMLeK5La9bL5eanjTWEN39IxKx zga2THOC4aUe4+qqKpQ23lZFNiwfKKq+lGqgyNlQ/ZCtSMS+ehNUjgbxke8uet8qOw pvN+C6hmmRRzqS7qm/HgrxUoD3t9fpaWc4CeSySygFNp7YnM7RLAwRFYSFkK/gmrB2 TUwqOXd7X/HkZyI7ZTIAC9nZW/r4r2Odd1WAfxSVHaEObgwt6B8Tax1NT69Eb4TFI6 H7rEjkuIV5DzQ== Precedence: bulk List-ID: X-Mailing-List: linux-rdma@vger.kernel.org On Wed, Sep 30, 2020 at 05:34:11PM +0800, Weihang Li wrote: > From: Lang Cheng > > For a field in extended QPC, there are four newly added interfaces: > - hr_reg_set(arr, field) can set all bits to 1, > - hr_reg_clear(arr, field) can clear all bits to 0, > - hr_reg_write(arr, field, val) can write a new value, > - hr_reg_read(arr, field) can read the value. > 'arr' is the array name of extended QPC, and 'field' is the global bit > offset of the whole array. > > Signed-off-by: Lang Cheng > Signed-off-by: Weihang Li > drivers/infiniband/hw/hns/hns_roce_common.h | 26 ++++++++++++++++++++++++++ > 1 file changed, 26 insertions(+) > > diff --git a/drivers/infiniband/hw/hns/hns_roce_common.h b/drivers/infiniband/hw/hns/hns_roce_common.h > index f5669ff..ab2386d 100644 > +++ b/drivers/infiniband/hw/hns/hns_roce_common.h > @@ -53,6 +53,32 @@ > #define roce_set_bit(origin, shift, val) \ > roce_set_field((origin), (1ul << (shift)), (shift), (val)) > > +#define hr_reg_set(arr, field) \ > + ((arr)[(field) / 32] |= \ > + cpu_to_le32((field##_W) + \ > + BUILD_BUG_ON_ZERO((field) / 32 >= ARRAY_SIZE(arr)))) > + > +#define hr_reg_clear(arr, field) \ > + ((arr)[(field) / 32] &= \ > + ~cpu_to_le32((field##_W) + \ > + BUILD_BUG_ON_ZERO((field) / 32 >= ARRAY_SIZE(arr)))) > + > +#define hr_reg_write(arr, field, val) \ > + do { \ > + BUILD_BUG_ON((field) / 32 >= ARRAY_SIZE(arr)); \ > + (arr)[(field) / 32] &= ~cpu_to_le32(field##_W); \ > + (arr)[(field) / 32] |= cpu_to_le32( \ > + ((u32)(val) << ((field) % 32)) & (field##_W)); \ > + } while (0) > + > +#define hr_reg_read(arr, field) \ > + (((le32_to_cpu((arr)[(field) / 32]) & (field##_W)) >> (field) % 32) + \ > + BUILD_BUG_ON_ZERO((field) / 32 >= ARRAY_SIZE(arr))) Why add these functions that are not used? Jason