From: Krzysztof Kozlowski <krzk@kernel.org>
To: Nicolin Chen <nicoleotsuka@gmail.com>
Cc: thierry.reding@gmail.com, robh+dt@kernel.org,
jonathanh@nvidia.com, linux-tegra@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH 3/5] memory: tegra: Sort tegra210_swgroups by reg address
Date: Thu, 8 Oct 2020 12:32:58 +0200 [thread overview]
Message-ID: <20201008103258.GA16358@kozik-lap> (raw)
In-Reply-To: <20201008003746.25659-4-nicoleotsuka@gmail.com>
On Wed, Oct 07, 2020 at 05:37:44PM -0700, Nicolin Chen wrote:
> This is a cleanup change to prepare for new swgroups.
What type of cleanup? Any functional change?
>
> Signed-off-by: Nicolin Chen <nicoleotsuka@gmail.com>
> ---
> drivers/memory/tegra/tegra210.c | 20 ++++++++++----------
> 1 file changed, 10 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/memory/tegra/tegra210.c b/drivers/memory/tegra/tegra210.c
> index e8a7d266802c..b400802c9f14 100644
> --- a/drivers/memory/tegra/tegra210.c
> +++ b/drivers/memory/tegra/tegra210.c
> @@ -1020,32 +1020,32 @@ static const struct tegra_mc_client tegra210_mc_clients[] = {
> };
>
> static const struct tegra_smmu_swgroup tegra210_swgroups[] = {
> - { .name = "dc", .swgroup = TEGRA_SWGROUP_DC, .reg = 0x240 },
> - { .name = "dcb", .swgroup = TEGRA_SWGROUP_DCB, .reg = 0x244 },
> { .name = "afi", .swgroup = TEGRA_SWGROUP_AFI, .reg = 0x238 },
> { .name = "avpc", .swgroup = TEGRA_SWGROUP_AVPC, .reg = 0x23c },
> - { .name = "hda", .swgroup = TEGRA_SWGROUP_HDA, .reg = 0x254 },
> + { .name = "dc", .swgroup = TEGRA_SWGROUP_DC, .reg = 0x240 },
> + { .name = "dcb", .swgroup = TEGRA_SWGROUP_DCB, .reg = 0x244 },
> { .name = "hc", .swgroup = TEGRA_SWGROUP_HC, .reg = 0x250 },
> + { .name = "hda", .swgroup = TEGRA_SWGROUP_HDA, .reg = 0x254 },
> + { .name = "isp2", .swgroup = TEGRA_SWGROUP_ISP2, .reg = 0x258 },
> { .name = "nvenc", .swgroup = TEGRA_SWGROUP_NVENC, .reg = 0x264 },
> { .name = "ppcs", .swgroup = TEGRA_SWGROUP_PPCS, .reg = 0x270 },
> { .name = "sata", .swgroup = TEGRA_SWGROUP_SATA, .reg = 0x274 },
> - { .name = "isp2", .swgroup = TEGRA_SWGROUP_ISP2, .reg = 0x258 },
> + { .name = "vi", .swgroup = TEGRA_SWGROUP_VI, .reg = 0x280 },
> + { .name = "vic", .swgroup = TEGRA_SWGROUP_VIC, .reg = 0x284 },
> { .name = "xusb_host", .swgroup = TEGRA_SWGROUP_XUSB_HOST, .reg = 0x288 },
> { .name = "xusb_dev", .swgroup = TEGRA_SWGROUP_XUSB_DEV, .reg = 0x28c },
> - { .name = "isp2b", .swgroup = TEGRA_SWGROUP_ISP2B, .reg = 0xaa4 },
> - { .name = "tsec", .swgroup = TEGRA_SWGROUP_TSEC, .reg = 0x294 },
> { .name = "a9avp", .swgroup = TEGRA_SWGROUP_A9AVP, .reg = 0x290 },
I must say I cannot find the order. By name - not. By swgroup name -
not. By register - not.
What is the order then?
Best regards,
Krzysztof
> - { .name = "gpu", .swgroup = TEGRA_SWGROUP_GPU, .reg = 0xaac },
> + { .name = "tsec", .swgroup = TEGRA_SWGROUP_TSEC, .reg = 0x294 },
> { .name = "sdmmc1a", .swgroup = TEGRA_SWGROUP_SDMMC1A, .reg = 0xa94 },
> { .name = "sdmmc2a", .swgroup = TEGRA_SWGROUP_SDMMC2A, .reg = 0xa98 },
> { .name = "sdmmc3a", .swgroup = TEGRA_SWGROUP_SDMMC3A, .reg = 0xa9c },
> { .name = "sdmmc4a", .swgroup = TEGRA_SWGROUP_SDMMC4A, .reg = 0xaa0 },
> - { .name = "vic", .swgroup = TEGRA_SWGROUP_VIC, .reg = 0x284 },
> - { .name = "vi", .swgroup = TEGRA_SWGROUP_VI, .reg = 0x280 },
> + { .name = "isp2b", .swgroup = TEGRA_SWGROUP_ISP2B, .reg = 0xaa4 },
> + { .name = "gpu", .swgroup = TEGRA_SWGROUP_GPU, .reg = 0xaac },
> { .name = "nvdec", .swgroup = TEGRA_SWGROUP_NVDEC, .reg = 0xab4 },
> { .name = "ape", .swgroup = TEGRA_SWGROUP_APE, .reg = 0xab8 },
> - { .name = "nvjpg", .swgroup = TEGRA_SWGROUP_NVJPG, .reg = 0xac0 },
> { .name = "se", .swgroup = TEGRA_SWGROUP_SE, .reg = 0xabc },
> + { .name = "nvjpg", .swgroup = TEGRA_SWGROUP_NVJPG, .reg = 0xac0 },
> { .name = "axiap", .swgroup = TEGRA_SWGROUP_AXIAP, .reg = 0xacc },
> { .name = "etr", .swgroup = TEGRA_SWGROUP_ETR, .reg = 0xad0 },
> { .name = "tsecb", .swgroup = TEGRA_SWGROUP_TSECB, .reg = 0xad4 },
> --
> 2.17.1
>
next prev parent reply other threads:[~2020-10-08 10:33 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-10-08 0:37 [PATCH 0/5] memory: tegra: Fix client list and add swgroups Nicolin Chen
2020-10-08 0:37 ` [PATCH 1/5] memory: tegra: Correct la.reg address of seswr Nicolin Chen
2020-10-09 12:11 ` Thierry Reding
2020-10-26 20:14 ` Krzysztof Kozlowski
2020-10-08 0:37 ` [PATCH 2/5] memory: tegra: Correct tegra210_mc_clients def values Nicolin Chen
2020-10-09 12:14 ` Thierry Reding
2020-10-26 20:15 ` Krzysztof Kozlowski
2020-10-08 0:37 ` [PATCH 3/5] memory: tegra: Sort tegra210_swgroups by reg address Nicolin Chen
2020-10-08 10:32 ` Krzysztof Kozlowski [this message]
2020-10-08 20:26 ` Nicolin Chen
2020-10-12 16:43 ` Krzysztof Kozlowski
2020-10-12 18:57 ` Nicolin Chen
2020-10-09 12:15 ` Thierry Reding
2020-10-26 20:17 ` Krzysztof Kozlowski
2020-10-08 0:37 ` [PATCH 4/5] dt-bindings: memory: tegra: Add missing swgroups Nicolin Chen
2020-10-09 12:21 ` Thierry Reding
2020-10-09 15:52 ` Nicolin Chen
2020-10-26 20:17 ` Krzysztof Kozlowski
2020-10-27 12:55 ` Thierry Reding
2020-10-27 23:31 ` Nicolin Chen
2020-10-27 19:54 ` Krzysztof Kozlowski
2020-10-08 0:37 ` [PATCH 5/5] memory: tegra: Complete tegra210_swgroups Nicolin Chen
2020-10-27 13:01 ` Thierry Reding
2020-10-27 23:37 ` Nicolin Chen
2020-11-20 16:27 ` Thierry Reding
2020-11-22 11:07 ` Krzysztof Kozlowski
2020-10-08 10:29 ` [PATCH 0/5] memory: tegra: Fix client list and add swgroups Krzysztof Kozlowski
2020-10-08 20:27 ` Nicolin Chen
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