From: Alexey Baturo <baturo.alexey@gmail.com>
Cc: baturo.alexey@gmail.com, richard.henderson@linaro.org,
space.monkey.delivers@gmail.com, kupokupokupopo@gmail.com,
palmer@dabbelt.com, Alistair.Francis@wdc.com,
sagark@eecs.berkeley.edu, kbastian@mail.uni-paderborn.de,
qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Subject: [PATCH 0/5] RISC-V Pointer Masking implementation
Date: Wed, 14 Oct 2020 20:03:23 +0300 [thread overview]
Message-ID: <20201014170323.27348-1-space.monkey.delivers@gmail.com> (raw)
Hi folks,
These patches implement Pointer Masking proposal which is developed by J-ext group.
This proposal is not yet ratified, but I hope QEMU implementation is done.
The proposal itself could be found here: https://github.com/riscv/riscv-j-extension
This functionality is submitted as experimental, as Richard Henderson suggested, thus there're some obvious issues:
- Introducing J extension is not the 100% correct way as I see it, but no Zname has been assigned and on J WG meeting we agreed to go with J ext for now
- CSR numbers for PM are not yet ratified, so they're subject to change
- No CSR have been implemented for recent hypervisor spec update. I didn't have enough time to get familiar with it, so I'll add it later
- No compliance tests for PM exist in RISC-V compliance infra, however in order to check it I did some simple asm tests(https://github.com/gattaca-lab/riscv_pm) and we have LLVM HWASAN enabled for RISC-V that relies on this PM implementation(https://github.com/gattaca-lab/riscv_hwasan)
This is my first QEMU patch submission, so please tell me if I'm doing something wrong.
Thanks
Alexey Baturo (4):
[RISCV_PM] Add J-extension into RISC-V
[RISCV_PM] Support CSRs required for RISC-V PM extension except for
ones in hypervisor mode
[RISCV_PM] Print new PM CSRs in QEMU logs
[RISCV_PM] Support pointer masking for RISC-V for i/c/f/d/a types of
instructions
Anatoly Parshintsev (1):
[RISCV_PM] Add address masking functions required for RISC-V Pointer
Masking extension
target/riscv/cpu.c | 14 ++
target/riscv/cpu.h | 13 +
target/riscv/cpu_bits.h | 66 ++++++
target/riscv/csr.c | 302 ++++++++++++++++++++++++
target/riscv/insn_trans/trans_rva.c.inc | 9 +
target/riscv/insn_trans/trans_rvd.c.inc | 6 +
target/riscv/insn_trans/trans_rvf.c.inc | 6 +
target/riscv/insn_trans/trans_rvi.c.inc | 6 +
target/riscv/translate.c | 77 ++++++
9 files changed, 499 insertions(+)
--
2.20.1
WARNING: multiple messages have this Message-ID (diff)
From: Alexey Baturo <baturo.alexey@gmail.com>
Cc: baturo.alexey@gmail.com, qemu-riscv@nongnu.org,
sagark@eecs.berkeley.edu, kbastian@mail.uni-paderborn.de,
richard.henderson@linaro.org, qemu-devel@nongnu.org,
space.monkey.delivers@gmail.com, Alistair.Francis@wdc.com,
kupokupokupopo@gmail.com, palmer@dabbelt.com
Subject: [PATCH 0/5] RISC-V Pointer Masking implementation
Date: Wed, 14 Oct 2020 20:03:23 +0300 [thread overview]
Message-ID: <20201014170323.27348-1-space.monkey.delivers@gmail.com> (raw)
Hi folks,
These patches implement Pointer Masking proposal which is developed by J-ext group.
This proposal is not yet ratified, but I hope QEMU implementation is done.
The proposal itself could be found here: https://github.com/riscv/riscv-j-extension
This functionality is submitted as experimental, as Richard Henderson suggested, thus there're some obvious issues:
- Introducing J extension is not the 100% correct way as I see it, but no Zname has been assigned and on J WG meeting we agreed to go with J ext for now
- CSR numbers for PM are not yet ratified, so they're subject to change
- No CSR have been implemented for recent hypervisor spec update. I didn't have enough time to get familiar with it, so I'll add it later
- No compliance tests for PM exist in RISC-V compliance infra, however in order to check it I did some simple asm tests(https://github.com/gattaca-lab/riscv_pm) and we have LLVM HWASAN enabled for RISC-V that relies on this PM implementation(https://github.com/gattaca-lab/riscv_hwasan)
This is my first QEMU patch submission, so please tell me if I'm doing something wrong.
Thanks
Alexey Baturo (4):
[RISCV_PM] Add J-extension into RISC-V
[RISCV_PM] Support CSRs required for RISC-V PM extension except for
ones in hypervisor mode
[RISCV_PM] Print new PM CSRs in QEMU logs
[RISCV_PM] Support pointer masking for RISC-V for i/c/f/d/a types of
instructions
Anatoly Parshintsev (1):
[RISCV_PM] Add address masking functions required for RISC-V Pointer
Masking extension
target/riscv/cpu.c | 14 ++
target/riscv/cpu.h | 13 +
target/riscv/cpu_bits.h | 66 ++++++
target/riscv/csr.c | 302 ++++++++++++++++++++++++
target/riscv/insn_trans/trans_rva.c.inc | 9 +
target/riscv/insn_trans/trans_rvd.c.inc | 6 +
target/riscv/insn_trans/trans_rvf.c.inc | 6 +
target/riscv/insn_trans/trans_rvi.c.inc | 6 +
target/riscv/translate.c | 77 ++++++
9 files changed, 499 insertions(+)
--
2.20.1
next reply other threads:[~2020-10-14 17:03 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-10-14 17:03 Alexey Baturo [this message]
2020-10-14 17:03 ` [PATCH 0/5] RISC-V Pointer Masking implementation Alexey Baturo
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