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From: Huang Rui <ray.huang@amd.com>
To: "Marek Olšák" <maraeo@gmail.com>,
	"Bas Nieuwenhuizen" <bas@basnieuwenhuizen.nl>
Cc: "Deucher, Alexander" <alexander.deucher@amd.com>,
	Roman.Li@amd.com,
	amd-gfx mailing list <amd-gfx@lists.freedesktop.org>
Subject: Re: [PATCH] drm/amd/display: Initialize num_pkrs on VANGOGH.
Date: Wed, 21 Oct 2020 10:48:37 +0800	[thread overview]
Message-ID: <20201021024837.GA896161@hr-amd> (raw)
In-Reply-To: <CAAxE2A5HdVj41F7BhnXzZzEpGLDowPat0tWxVrAA0trvZ6p8JQ@mail.gmail.com>

On Tue, Oct 20, 2020 at 07:47:42PM -0400, Marek Olšák wrote:
> FYI, this fixes tiling on VanGogh.
> 
> Reviewed-by: Marek Olšák <marek.olsak@amd.com>
> 
> Marek
> 
> On Tue, Oct 20, 2020 at 6:31 PM Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
> wrote:
> 
> > As far a I can tell uses a variant of DCN3xx which uses num_pkrs.
> >
> > If we do not initialize the variable we will set the register field
> > to ilog2(0) = -1, though the mask will reduce that to 7. Pretty sure
> > 7 is not the value we want here.
> >
> > Signed-off-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
> > ---
> >
> > Found while rebasing my modifiers series. Not tested on HW.

Yes! Thank you so much, Bas!

I just verified the tiling issue got resovled with your patch! :-)

Applied.

Reviewed-and-Tested-by: Huang Rui <ray.huang@amd.com>

> >
> >  drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 ++-
> >  1 file changed, 2 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> > b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> > index 6855aad7f312..2713caac4f2a 100644
> > --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> > +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> > @@ -4074,7 +4074,8 @@ fill_plane_buffer_attributes(struct amdgpu_device
> > *adev,
> >  #ifdef CONFIG_DRM_AMD_DC_DCN3_0
> >                 if (adev->asic_type == CHIP_SIENNA_CICHLID ||
> >                     adev->asic_type == CHIP_NAVY_FLOUNDER ||
> > -                   adev->asic_type == CHIP_DIMGREY_CAVEFISH)
> > +                   adev->asic_type == CHIP_DIMGREY_CAVEFISH ||
> > +                   adev->asic_type == CHIP_VANGOGH)
> >                         tiling_info->gfx9.num_pkrs =
> > adev->gfx.config.gb_addr_config_fields.num_pkrs;
> >  #endif
> >                 ret = fill_plane_dcc_attributes(adev, afb, format,
> > rotation,
> > --
> > 2.28.0
> >
> > _______________________________________________
> > amd-gfx mailing list
> > amd-gfx@lists.freedesktop.org
> > https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&amp;data=04%7C01%7Cray.huang%40amd.com%7C9afdb4e0a2e949655c9b08d87552a1bf%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637388345070265382%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&amp;sdata=SbojOTLaOXt85OSbYjyRPozLAsqBwXpvoYVBu7c0Ido%3D&amp;reserved=0
> >

> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&amp;data=04%7C01%7Cray.huang%40amd.com%7C9afdb4e0a2e949655c9b08d87552a1bf%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637388345070305360%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&amp;sdata=uPui9S6bxwp%2B4J4uav4FekR1zOZ9VeHYcdrOSA9ZFKg%3D&amp;reserved=0

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  reply	other threads:[~2020-10-21  2:48 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-10-20 22:31 [PATCH] drm/amd/display: Initialize num_pkrs on VANGOGH Bas Nieuwenhuizen
2020-10-20 23:47 ` Marek Olšák
2020-10-21  2:48   ` Huang Rui [this message]
2020-10-21 16:09 ` [PATCH] drm/amd/display: Interpret log_2(0) as 0 Harry Wentland
2020-10-21 16:39   ` Bas Nieuwenhuizen
2020-10-21 20:10     ` Marek Olšák

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