From: Vidya Sagar <vidyas@nvidia.com>
To: <jingoohan1@gmail.com>, <gustavo.pimentel@synopsys.com>,
<lorenzo.pieralisi@arm.com>, <bhelgaas@google.com>,
<amurray@thegoodpenguin.co.uk>, <robh@kernel.org>,
<treding@nvidia.com>, <jonathanh@nvidia.com>
Cc: <linux-pci@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
<kthota@nvidia.com>, <mmaddireddy@nvidia.com>,
<vidyas@nvidia.com>, <sagar.tv@gmail.com>
Subject: [PATCH 2/3] PCI: dwc: Add support to program ATU for >4GB memory aperture sizes
Date: Sat, 24 Oct 2020 01:26:54 +0530 [thread overview]
Message-ID: <20201023195655.11242-3-vidyas@nvidia.com> (raw)
In-Reply-To: <20201023195655.11242-1-vidyas@nvidia.com>
Add support to program the ATU to enable translations for >4GB sizes of
the prefetchable memory apertures.
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
---
drivers/pci/controller/dwc/pcie-designware.c | 12 +++++++-----
drivers/pci/controller/dwc/pcie-designware.h | 3 ++-
2 files changed, 9 insertions(+), 6 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
index c2dea8fc97c8..b5e438b70cd5 100644
--- a/drivers/pci/controller/dwc/pcie-designware.c
+++ b/drivers/pci/controller/dwc/pcie-designware.c
@@ -228,7 +228,7 @@ static void dw_pcie_writel_ob_unroll(struct dw_pcie *pci, u32 index, u32 reg,
static void dw_pcie_prog_outbound_atu_unroll(struct dw_pcie *pci, u8 func_no,
int index, int type,
u64 cpu_addr, u64 pci_addr,
- u32 size)
+ u64 size)
{
u32 retries, val;
u64 limit_addr = cpu_addr + size - 1;
@@ -245,8 +245,10 @@ static void dw_pcie_prog_outbound_atu_unroll(struct dw_pcie *pci, u8 func_no,
lower_32_bits(pci_addr));
dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_UPPER_TARGET,
upper_32_bits(pci_addr));
- dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL1,
- type | PCIE_ATU_FUNC_NUM(func_no));
+ val = type | PCIE_ATU_FUNC_NUM(func_no);
+ val = upper_32_bits(size - 1) ?
+ val | PCIE_ATU_INCREASE_REGION_SIZE : val;
+ dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL1, val);
dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL2,
PCIE_ATU_ENABLE);
@@ -267,7 +269,7 @@ static void dw_pcie_prog_outbound_atu_unroll(struct dw_pcie *pci, u8 func_no,
static void __dw_pcie_prog_outbound_atu(struct dw_pcie *pci, u8 func_no,
int index, int type, u64 cpu_addr,
- u64 pci_addr, u32 size)
+ u64 pci_addr, u64 size)
{
u32 retries, val;
@@ -311,7 +313,7 @@ static void __dw_pcie_prog_outbound_atu(struct dw_pcie *pci, u8 func_no,
}
void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, int type,
- u64 cpu_addr, u64 pci_addr, u32 size)
+ u64 cpu_addr, u64 pci_addr, u64 size)
{
__dw_pcie_prog_outbound_atu(pci, 0, index, type,
cpu_addr, pci_addr, size);
diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
index 9d2f511f13fa..e7f441441db2 100644
--- a/drivers/pci/controller/dwc/pcie-designware.h
+++ b/drivers/pci/controller/dwc/pcie-designware.h
@@ -84,6 +84,7 @@
#define PCIE_ATU_REGION_INDEX1 0x1
#define PCIE_ATU_REGION_INDEX0 0x0
#define PCIE_ATU_CR1 0x904
+#define PCIE_ATU_INCREASE_REGION_SIZE BIT(13)
#define PCIE_ATU_TYPE_MEM 0x0
#define PCIE_ATU_TYPE_IO 0x2
#define PCIE_ATU_TYPE_CFG0 0x4
@@ -295,7 +296,7 @@ void dw_pcie_upconfig_setup(struct dw_pcie *pci);
int dw_pcie_wait_for_link(struct dw_pcie *pci);
void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index,
int type, u64 cpu_addr, u64 pci_addr,
- u32 size);
+ u64 size);
void dw_pcie_prog_ep_outbound_atu(struct dw_pcie *pci, u8 func_no, int index,
int type, u64 cpu_addr, u64 pci_addr,
u32 size);
--
2.17.1
next prev parent reply other threads:[~2020-10-23 19:57 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-10-23 19:56 [PATCH 0/3] Add support to handle prefetchable memory Vidya Sagar
2020-10-23 19:56 ` [PATCH 1/3] PCI: of: Warn if non-prefetchable memory aperture size is > 32-bit Vidya Sagar
2020-10-26 17:51 ` Rob Herring
2020-10-23 19:56 ` Vidya Sagar [this message]
2020-10-26 17:51 ` [PATCH 2/3] PCI: dwc: Add support to program ATU for >4GB memory aperture sizes Rob Herring
2020-10-23 19:56 ` [PATCH 3/3] PCI: dwc: Add support to handle prefetchable memory mapping Vidya Sagar
2020-10-26 15:40 ` Rob Herring
2020-10-24 4:03 ` [PATCH 0/3] Add support to handle prefetchable memory Jingoo Han
2020-10-26 12:32 ` Thierry Reding
2020-11-04 7:46 ` Vidya Sagar
2020-11-17 4:38 ` Vidya Sagar
2020-11-17 12:10 ` [PATCH 0/3] Add support to handle prefetchable memoryg Lorenzo Pieralisi
2020-11-17 17:34 ` Vidya Sagar
2020-11-18 10:29 ` [PATCH 0/3] Add support to handle prefetchable memory Lorenzo Pieralisi
2020-11-04 9:50 ` Jon Hunter
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20201023195655.11242-3-vidyas@nvidia.com \
--to=vidyas@nvidia.com \
--cc=amurray@thegoodpenguin.co.uk \
--cc=bhelgaas@google.com \
--cc=gustavo.pimentel@synopsys.com \
--cc=jingoohan1@gmail.com \
--cc=jonathanh@nvidia.com \
--cc=kthota@nvidia.com \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-pci@vger.kernel.org \
--cc=lorenzo.pieralisi@arm.com \
--cc=mmaddireddy@nvidia.com \
--cc=robh@kernel.org \
--cc=sagar.tv@gmail.com \
--cc=treding@nvidia.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.