Re: [Intel-gfx] [PATCH] drm/i915: Disable atomics in L3 for gen9

["Ville Syrjälä" <ville.syrjala@linux.intel.com>]

On Mon, Nov 09, 2020 at 08:15:05PM +0000, Chris Wilson wrote:
> Quoting Jason Ekstrand (2020-11-09 19:52:26)
> > We need to land this patch.  The number of bugs we have piling up in
> > Mesa gitlab related to this is getting a lot larger than I'd like.
> > I've gone back and forth with various HW and SW people internally for
> > countless e-mail threads and there is no other good workaround.  Yes,
> > the perf hit to atomics sucks but, fortunately, most games don't use
> > them heavily enough for it to make a significant impact.  We should
> > just eat the perf hit and fix the hangs.
> 
> Drat, I thought you had found an alternative fix in the
> bad GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC w/a.
> 
> So be it.

I don't suppose this could be just lack of programming the magic
MOCS entry for L3 evictions?

--- a/drivers/gpu/drm/i915/gt/intel_mocs.c
+++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
@@ -132,6 +132,9 @@ static const struct drm_i915_mocs_entry skl_mocs_table[] = {
        MOCS_ENTRY(I915_MOCS_CACHED,
                   LE_3_WB | LE_TC_2_LLC_ELLC | LE_LRUM(3),
                   L3_3_WB)
+       MOCS_ENTRY(63,
+                  LE_3_WB | LE_TC_1_LLC | LE_LRUM(3),
+                  L3_1_UC)
 };
 
 /* NOTE: the LE_TGT_CACHE is not used on Broxton */

The code seems to claim we can't even program that on gen9, but there's
nothing in the current spec to back that up AFAICS.

-- 
Ville Syrjälä
Intel
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