From: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
To: Mika Westerberg <mika.westerberg@linux.intel.com>
Cc: linux-gpio@vger.kernel.org,
Linus Walleij <linus.walleij@linaro.org>,
Divagar Mohandass <divagar.mohandass@intel.com>
Subject: Re: [PATCH v1] pinctrl: jasperlake: Unhide SPI group of pins
Date: Thu, 12 Nov 2020 15:56:06 +0200 [thread overview]
Message-ID: <20201112135606.GD4077@smile.fi.intel.com> (raw)
In-Reply-To: <20201111073533.GM2495@lahna.fi.intel.com>
On Wed, Nov 11, 2020 at 09:35:33AM +0200, Mika Westerberg wrote:
> On Tue, Nov 10, 2020 at 09:59:23PM +0200, Andy Shevchenko wrote:
> > If the group of pins is hidden in the pin list it affects
> > the register offset calculation despite fixed GPIO base.
> > Hence, the offsets of all pins after the hidden group
> > are broken. Instead we have to unhide the group and use a flag
> > to exclude it from GPIO number space.
> >
> > Fixes: e278dcb7048b ("pinctrl: intel: Add Intel Jasper Lake pin controller support")
> > Reported-by: Divagar Mohandass <divagar.mohandass@intel.com>
> > Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
>
> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Pushed to my review and testing queue, thanks!
--
With Best Regards,
Andy Shevchenko
prev parent reply other threads:[~2020-11-12 13:55 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-11-10 19:59 [PATCH v1] pinctrl: jasperlake: Unhide SPI group of pins Andy Shevchenko
2020-11-11 7:35 ` Mika Westerberg
2020-11-12 13:56 ` Andy Shevchenko [this message]
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