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Thu, 12 Nov 2020 18:35:33 +0000 Date: Thu, 12 Nov 2020 14:35:32 -0400 From: Jason Gunthorpe To: Weihang Li CC: , , , Subject: Re: [PATCH for-next 7/8] RDMA/hns: Add UD support for HIP09 Message-ID: <20201112183532.GA964096@nvidia.com> References: <1604057975-23388-1-git-send-email-liweihang@huawei.com> <1604057975-23388-8-git-send-email-liweihang@huawei.com> Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <1604057975-23388-8-git-send-email-liweihang@huawei.com> X-ClientProxiedBy: BL1PR13CA0151.namprd13.prod.outlook.com (2603:10b6:208:2bd::6) To DM6PR12MB3834.namprd12.prod.outlook.com (2603:10b6:5:14a::12) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from mlx.ziepe.ca (156.34.48.30) by BL1PR13CA0151.namprd13.prod.outlook.com (2603:10b6:208:2bd::6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3564.21 via Frontend Transport; Thu, 12 Nov 2020 18:35:33 +0000 Received: from jgg by mlx with local (Exim 4.94) (envelope-from ) id 1kdHRU-0042pl-6T; Thu, 12 Nov 2020 14:35:32 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1605206140; bh=xUzwi9x81Gr6/1ig96S3ugoH15M/BWV4ZoXdAM9gO+U=; h=ARC-Seal:ARC-Message-Signature:ARC-Authentication-Results:Date: From:To:CC:Subject:Message-ID:References:Content-Type: Content-Disposition:In-Reply-To:X-ClientProxiedBy:MIME-Version: X-MS-Exchange-MessageSentRepresentingType; b=UYL+cUw7UCWbdTRnWv01ves2BKpHlXZ0OH3AdMR1bBy/nc1IVORp5XHyveGUx1b4F wgGJ96LWZDzxflyCTs6nMj1DXiN/MbKcMnXrZQIdSE6klPRNuPuwOe7SuKTbd911l0 LqxOqUzUTPJGyopS+RuWSXBE4POOau/ivYMI1U8QCz5GYMm7e5sxpeP2Z9MIbFADy+ WZWRvb6gDxX57L0jI6M8zrPNp6jhzOSszVPHHXF5gsFtLb2Q2N4XGrDH58oY3EN9rQ EZoJ+fQ/AV7ZQ1MQ9IYdCTd77VtwSL4pDm3+w9wZ6oaDX+Cdt/WQ8r+THxBnDgimHj Ma8c4bZQLsDFA== Precedence: bulk List-ID: X-Mailing-List: linux-rdma@vger.kernel.org On Fri, Oct 30, 2020 at 07:39:34PM +0800, Weihang Li wrote: > HIP09 supports service type of Unreliable Datagram, add necessary process > to enable this feature. > > Signed-off-by: Weihang Li > drivers/infiniband/hw/hns/hns_roce_device.h | 2 ++ > drivers/infiniband/hw/hns/hns_roce_hw_v2.c | 8 +++++--- > drivers/infiniband/hw/hns/hns_roce_qp.c | 3 ++- > 3 files changed, 9 insertions(+), 4 deletions(-) > > diff --git a/drivers/infiniband/hw/hns/hns_roce_device.h b/drivers/infiniband/hw/hns/hns_roce_device.h > index 9a032d0..23f8fe7 100644 > +++ b/drivers/infiniband/hw/hns/hns_roce_device.h > @@ -222,7 +222,9 @@ enum { > HNS_ROCE_CAP_FLAG_FRMR = BIT(8), > HNS_ROCE_CAP_FLAG_QP_FLOW_CTRL = BIT(9), > HNS_ROCE_CAP_FLAG_ATOMIC = BIT(10), > + HNS_ROCE_CAP_FLAG_UD = BIT(11), Why add this flag if nothing reads it? > HNS_ROCE_CAP_FLAG_SDI_MODE = BIT(14), > + > }; Extra space If I recall properly earlier chips did not have a GID table so could not support UD because they could not secure the AH, or something like that. So, I would expect to see that only the new devices support UD, but I can't quite see that in this patch?? Jason