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From: Bjorn Andersson <bjorn.andersson@linaro.org>
To: Thara Gopinath <thara.gopinath@linaro.org>
Cc: agross@kernel.org, herbert@gondor.apana.org.au,
	davem@davemloft.net, robh+dt@kernel.org, sboyd@kernel.org,
	mturquette@baylibre.com, linux-arm-msm@vger.kernel.org,
	linux-crypto@vger.kernel.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org
Subject: Re: [PATCH 2/6] clk:qcom:rpmh: Add CE clock on sdm845.
Date: Tue, 17 Nov 2020 21:59:48 -0600	[thread overview]
Message-ID: <20201118035948.GB8532@builder.lan> (raw)
In-Reply-To: <20201117134714.3456446-3-thara.gopinath@linaro.org>

On Tue 17 Nov 07:47 CST 2020, Thara Gopinath wrote:

> Qualcomm CE clock resource that is managed by BCM is required
> by crypto driver to access the core clock.
> 

' ' after ':' in $subject

With that
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>

Regards,
bjorn

> Signed-off-by: Thara Gopinath <thara.gopinath@linaro.org>
> ---
>  drivers/clk/qcom/clk-rpmh.c | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/drivers/clk/qcom/clk-rpmh.c b/drivers/clk/qcom/clk-rpmh.c
> index e2c669b08aff..7e2a4a9b9bf6 100644
> --- a/drivers/clk/qcom/clk-rpmh.c
> +++ b/drivers/clk/qcom/clk-rpmh.c
> @@ -349,6 +349,7 @@ DEFINE_CLK_RPMH_VRM(sdm845, rf_clk2, rf_clk2_ao, "rfclka2", 1);
>  DEFINE_CLK_RPMH_VRM(sdm845, rf_clk3, rf_clk3_ao, "rfclka3", 1);
>  DEFINE_CLK_RPMH_VRM(sm8150, rf_clk3, rf_clk3_ao, "rfclka3", 1);
>  DEFINE_CLK_RPMH_BCM(sdm845, ipa, "IP0");
> +DEFINE_CLK_RPMH_BCM(sdm845, ce, "CE0");
>  
>  static struct clk_hw *sdm845_rpmh_clocks[] = {
>  	[RPMH_CXO_CLK]		= &sdm845_bi_tcxo.hw,
> @@ -364,6 +365,7 @@ static struct clk_hw *sdm845_rpmh_clocks[] = {
>  	[RPMH_RF_CLK3]		= &sdm845_rf_clk3.hw,
>  	[RPMH_RF_CLK3_A]	= &sdm845_rf_clk3_ao.hw,
>  	[RPMH_IPA_CLK]		= &sdm845_ipa.hw,
> +	[RPMH_CE_CLK]		= &sdm845_ce.hw,
>  };
>  
>  static const struct clk_rpmh_desc clk_rpmh_sdm845 = {
> -- 
> 2.25.1
> 

  reply	other threads:[~2020-11-18  3:59 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-11-17 13:47 [PATCH 0/6] Enable Qualcomm Crypto Engine on sdm845 Thara Gopinath
2020-11-17 13:47 ` [PATCH 1/6] dt-binding:clock: Add entry for crypto engine RPMH clock resource Thara Gopinath
2020-11-18  3:57   ` Bjorn Andersson
2020-11-17 13:47 ` [PATCH 2/6] clk:qcom:rpmh: Add CE clock on sdm845 Thara Gopinath
2020-11-18  3:59   ` Bjorn Andersson [this message]
2020-11-17 13:47 ` [PATCH 3/6] drivers:crypto:qce: Enable support for crypto engine " Thara Gopinath
2020-11-18  4:02   ` Bjorn Andersson
2020-11-17 13:47 ` [PATCH 4/6] drivers:crypto:qce: Fix SHA result buffer corruption issues Thara Gopinath
2020-11-18  4:04   ` Bjorn Andersson
2020-11-17 13:47 ` [PATCH 5/6] dts:qcom:sdm845: Add dt entries to support crypto engine Thara Gopinath
2020-11-18  4:10   ` Bjorn Andersson
2020-11-18 19:58     ` Thara Gopinath
2020-11-17 13:47 ` [PATCH 6/6] devicetree:bindings:crypto: Extend qcom-qce binding to add support for crypto engine version 5.4 Thara Gopinath
2020-11-18  4:08   ` Bjorn Andersson
2020-11-17 16:57 ` [PATCH 0/6] Enable Qualcomm Crypto Engine on sdm845 Eric Biggers
2020-11-17 18:07   ` Thara Gopinath

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