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header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 9D5A389E63; Sat, 21 Nov 2020 22:20:46 +0000 (UTC) Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by gabe.freedesktop.org (Postfix) with ESMTPS id D8BF689E63 for ; Sat, 21 Nov 2020 22:20:45 +0000 (UTC) IronPort-SDR: C1YsKBBL+5wEvM3/Ne1mZdMtxXzRJr6FGeDYwR3rW7jeld5kBnZLlwYW0792WaIffIakWG+asB Eje/imXW1i9Q== X-IronPort-AV: E=McAfee;i="6000,8403,9812"; a="169046705" X-IronPort-AV: E=Sophos;i="5.78,360,1599548400"; d="gz'50?scan'50,208,50";a="169046705" X-Amp-Result: UNKNOWN X-Amp-Original-Verdict: FILE UNKNOWN X-Amp-File-Uploaded: False Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Nov 2020 14:20:44 -0800 IronPort-SDR: xXOqQ/0cWAYLrlUUTJ6yuHGqbCbrYR7CNuEdGGqXxRE6c5eGkPBf2hNsotB1lBoFR5ql8jU0OL hCT7g4Dlp+ZQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.78,360,1599548400"; d="gz'50?scan'50,208,50";a="545917056" Received: from lkp-server01.sh.intel.com (HELO 00bc34107a07) ([10.239.97.150]) by orsmga005.jf.intel.com with ESMTP; 21 Nov 2020 14:20:42 -0800 Received: from kbuild by 00bc34107a07 with local (Exim 4.92) (envelope-from ) id 1kgbFJ-0000RV-8n; Sat, 21 Nov 2020 22:20:41 +0000 Date: Sun, 22 Nov 2020 06:19:54 +0800 From: kernel test robot To: Flora Cui Subject: [radeon-alex:amd-20.45 1379/2417] drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hubp.h:164:2: error: expected specifier-qualifier-list before 'DCN21_HUBP_REG_COMMON_VARIABLE_LIST' Message-ID: <202011220627.iskIRRja-lkp@intel.com> MIME-Version: 1.0 Content-Type: multipart/mixed; boundary="PNTmBPCT7hxwcZjr" Content-Disposition: inline User-Agent: Mutt/1.10.1 (2018-07-13) X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Yang Xiong , kbuild-all@lists.01.org, dri-devel@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" --PNTmBPCT7hxwcZjr Content-Type: text/plain; charset=us-ascii Content-Disposition: inline tree: git://people.freedesktop.org/~agd5f/linux.git amd-20.45 head: 1807abbb3a7f17fc931a15d7fd4365ea148c6bb1 commit: 470f4be73099cc46478d2c708411fecde8197ca3 [1379/2417] drm/amdkcl: update DRM_AMD_DC_DCN3_0 to depends on legacy display config config: i386-randconfig-a003-20201120 (attached as .config) compiler: gcc-9 (Debian 9.3.0-15) 9.3.0 reproduce (this is a W=1 build): git remote add radeon-alex git://people.freedesktop.org/~agd5f/linux.git git fetch --no-tags radeon-alex amd-20.45 git checkout 470f4be73099cc46478d2c708411fecde8197ca3 # save the attached .config to linux build tree make W=1 ARCH=i386 If you fix the issue, kindly add following tag as appropriate Reported-by: kernel test robot All error/warnings (new ones prefixed by >>): In file included from drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:42: >> drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hubp.h:164:2: error: expected specifier-qualifier-list before 'DCN21_HUBP_REG_COMMON_VARIABLE_LIST' 164 | DCN21_HUBP_REG_COMMON_VARIABLE_LIST;\ | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hubp.h:164:2: note: in definition of macro 'DCN30_HUBP_REG_COMMON_VARIABLE_LIST' 164 | DCN21_HUBP_REG_COMMON_VARIABLE_LIST;\ | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ >> drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hubp.h:207:2: error: expected specifier-qualifier-list before 'DCN21_HUBP_REG_FIELD_VARIABLE_LIST' 207 | DCN21_HUBP_REG_FIELD_VARIABLE_LIST(type);\ | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hubp.h:207:2: note: in definition of macro 'DCN30_HUBP_REG_FIELD_VARIABLE_LIST' 207 | DCN21_HUBP_REG_FIELD_VARIABLE_LIST(type);\ | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ >> drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hubp.h:207:2: error: expected specifier-qualifier-list before 'DCN21_HUBP_REG_FIELD_VARIABLE_LIST' 207 | DCN21_HUBP_REG_FIELD_VARIABLE_LIST(type);\ | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hubp.h:207:2: note: in definition of macro 'DCN30_HUBP_REG_FIELD_VARIABLE_LIST' 207 | DCN21_HUBP_REG_FIELD_VARIABLE_LIST(type);\ | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ In file included from drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:68: drivers/gpu/drm/amd/include/navi10_ip_offset.h:269:52: warning: initialized field overwritten [-Woverride-init] 269 | #define DCN_BASE__INST0_SEG2 0x000034C0 | ^~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:494:25: note: in expansion of macro 'DCN_BASE__INST0_SEG2' 494 | #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg | ^~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:496:19: note: in expansion of macro 'BASE_INNER' 496 | #define BASE(seg) BASE_INNER(seg) | ^~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:503:14: note: in expansion of macro 'BASE' 503 | .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ | ^~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_link_encoder.h:202:2: note: in expansion of macro 'SRI' 202 | SRI(TMDS_CTL_BITS, DIG, id), \ | ^~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_link_encoder.h:235:2: note: in expansion of macro 'DPCS_DCN2_CMN_REG_LIST' 235 | DPCS_DCN2_CMN_REG_LIST(id), \ | ^~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:678:2: note: in expansion of macro 'DPCS_DCN2_REG_LIST' 678 | DPCS_DCN2_REG_LIST(id), \ | ^~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:683:2: note: in expansion of macro 'link_regs' 683 | link_regs(0, A), | ^~~~~~~~~ drivers/gpu/drm/amd/include/navi10_ip_offset.h:269:52: note: (near initialization for 'link_enc_regs[0].TMDS_CTL_BITS') 269 | #define DCN_BASE__INST0_SEG2 0x000034C0 | ^~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:494:25: note: in expansion of macro 'DCN_BASE__INST0_SEG2' 494 | #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg | ^~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:496:19: note: in expansion of macro 'BASE_INNER' 496 | #define BASE(seg) BASE_INNER(seg) | ^~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:503:14: note: in expansion of macro 'BASE' 503 | .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ | ^~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_link_encoder.h:202:2: note: in expansion of macro 'SRI' 202 | SRI(TMDS_CTL_BITS, DIG, id), \ | ^~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_link_encoder.h:235:2: note: in expansion of macro 'DPCS_DCN2_CMN_REG_LIST' 235 | DPCS_DCN2_CMN_REG_LIST(id), \ | ^~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:678:2: note: in expansion of macro 'DPCS_DCN2_REG_LIST' 678 | DPCS_DCN2_REG_LIST(id), \ | ^~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:683:2: note: in expansion of macro 'link_regs' 683 | link_regs(0, A), | ^~~~~~~~~ drivers/gpu/drm/amd/include/navi10_ip_offset.h:269:52: warning: initialized field overwritten [-Woverride-init] 269 | #define DCN_BASE__INST0_SEG2 0x000034C0 | ^~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:494:25: note: in expansion of macro 'DCN_BASE__INST0_SEG2' 494 | #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg | ^~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:496:19: note: in expansion of macro 'BASE_INNER' 496 | #define BASE(seg) BASE_INNER(seg) | ^~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:503:14: note: in expansion of macro 'BASE' 503 | .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ | ^~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:679:2: note: in expansion of macro 'SRI' 679 | SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \ | ^~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:683:2: note: in expansion of macro 'link_regs' 683 | link_regs(0, A), | ^~~~~~~~~ drivers/gpu/drm/amd/include/navi10_ip_offset.h:269:52: note: (near initialization for 'link_enc_regs[0].DP_DPHY_INTERNAL_CTRL') 269 | #define DCN_BASE__INST0_SEG2 0x000034C0 | ^~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:494:25: note: in expansion of macro 'DCN_BASE__INST0_SEG2' 494 | #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg | ^~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:496:19: note: in expansion of macro 'BASE_INNER' 496 | #define BASE(seg) BASE_INNER(seg) | ^~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:503:14: note: in expansion of macro 'BASE' 503 | .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ | ^~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:679:2: note: in expansion of macro 'SRI' 679 | SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \ | ^~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:683:2: note: in expansion of macro 'link_regs' 683 | link_regs(0, A), | ^~~~~~~~~ drivers/gpu/drm/amd/include/navi10_ip_offset.h:269:52: warning: initialized field overwritten [-Woverride-init] 269 | #define DCN_BASE__INST0_SEG2 0x000034C0 | ^~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:494:25: note: in expansion of macro 'DCN_BASE__INST0_SEG2' 494 | #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg | ^~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:496:19: note: in expansion of macro 'BASE_INNER' 496 | #define BASE(seg) BASE_INNER(seg) | ^~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:503:14: note: in expansion of macro 'BASE' -- | ^~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_optc.h:48:2: note: in expansion of macro 'TG_COMMON_MASK_SH_LIST_DCN' 48 | TG_COMMON_MASK_SH_LIST_DCN(mask_sh),\ | ^~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:873:2: note: in expansion of macro 'TG_COMMON_MASK_SH_LIST_DCN2_0' 873 | TG_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT) | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_sh_mask.h:31037:111: note: (near initialization for 'tg_shift.OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP') 31037 | #define OTG0_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP__SHIFT 0x12 | ^~~~ drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_sh_mask.h:31037:111: note: in definition of macro 'OTG0_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP__SHIFT' 31037 | #define OTG0_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP__SHIFT 0x12 | ^~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/../dcn10/dcn10_optc.h:224:2: note: in expansion of macro 'SF' 224 | SF(OTG0_OTG_STEREO_CONTROL, OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP, mask_sh),\ | ^~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_optc.h:48:2: note: in expansion of macro 'TG_COMMON_MASK_SH_LIST_DCN' 48 | TG_COMMON_MASK_SH_LIST_DCN(mask_sh),\ | ^~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:873:2: note: in expansion of macro 'TG_COMMON_MASK_SH_LIST_DCN2_0' 873 | TG_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT) | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_sh_mask.h:31110:111: warning: initialized field overwritten [-Woverride-init] 31110 | #define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_MODE__SHIFT 0x18 | ^~~~ drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_sh_mask.h:31110:111: note: in definition of macro 'OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_MODE__SHIFT' 31110 | #define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_MODE__SHIFT 0x18 | ^~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_optc.h:54:2: note: in expansion of macro 'SF' 54 | SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_RANGE_TIMING_DBUF_UPDATE_MODE, mask_sh),\ | ^~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:873:2: note: in expansion of macro 'TG_COMMON_MASK_SH_LIST_DCN2_0' 873 | TG_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT) | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_sh_mask.h:31110:111: note: (near initialization for 'tg_shift.OTG_RANGE_TIMING_DBUF_UPDATE_MODE') 31110 | #define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_MODE__SHIFT 0x18 | ^~~~ drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_sh_mask.h:31110:111: note: in definition of macro 'OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_MODE__SHIFT' 31110 | #define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_MODE__SHIFT 0x18 | ^~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_optc.h:54:2: note: in expansion of macro 'SF' 54 | SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_RANGE_TIMING_DBUF_UPDATE_MODE, mask_sh),\ | ^~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:873:2: note: in expansion of macro 'TG_COMMON_MASK_SH_LIST_DCN2_0' 873 | TG_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT) | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_sh_mask.h:31044:111: warning: initialized field overwritten [-Woverride-init] 31044 | #define OTG0_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP_MASK 0x00040000L | ^~~~~~~~~~~ drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_sh_mask.h:31044:111: note: in definition of macro 'OTG0_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP_MASK' 31044 | #define OTG0_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP_MASK 0x00040000L | ^~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/../dcn10/dcn10_optc.h:224:2: note: in expansion of macro 'SF' 224 | SF(OTG0_OTG_STEREO_CONTROL, OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP, mask_sh),\ | ^~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_optc.h:48:2: note: in expansion of macro 'TG_COMMON_MASK_SH_LIST_DCN' 48 | TG_COMMON_MASK_SH_LIST_DCN(mask_sh),\ | ^~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:877:2: note: in expansion of macro 'TG_COMMON_MASK_SH_LIST_DCN2_0' 877 | TG_COMMON_MASK_SH_LIST_DCN2_0(_MASK) | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_sh_mask.h:31044:111: note: (near initialization for 'tg_mask.OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP') 31044 | #define OTG0_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP_MASK 0x00040000L | ^~~~~~~~~~~ drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_sh_mask.h:31044:111: note: in definition of macro 'OTG0_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP_MASK' 31044 | #define OTG0_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP_MASK 0x00040000L | ^~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/../dcn10/dcn10_optc.h:224:2: note: in expansion of macro 'SF' 224 | SF(OTG0_OTG_STEREO_CONTROL, OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP, mask_sh),\ | ^~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_optc.h:48:2: note: in expansion of macro 'TG_COMMON_MASK_SH_LIST_DCN' 48 | TG_COMMON_MASK_SH_LIST_DCN(mask_sh),\ | ^~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:877:2: note: in expansion of macro 'TG_COMMON_MASK_SH_LIST_DCN2_0' 877 | TG_COMMON_MASK_SH_LIST_DCN2_0(_MASK) | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_sh_mask.h:31122:111: warning: initialized field overwritten [-Woverride-init] 31122 | #define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_MODE_MASK 0x03000000L | ^~~~~~~~~~~ drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_sh_mask.h:31122:111: note: in definition of macro 'OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_MODE_MASK' 31122 | #define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_MODE_MASK 0x03000000L | ^~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_optc.h:54:2: note: in expansion of macro 'SF' 54 | SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_RANGE_TIMING_DBUF_UPDATE_MODE, mask_sh),\ | ^~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:877:2: note: in expansion of macro 'TG_COMMON_MASK_SH_LIST_DCN2_0' 877 | TG_COMMON_MASK_SH_LIST_DCN2_0(_MASK) | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_sh_mask.h:31122:111: note: (near initialization for 'tg_mask.OTG_RANGE_TIMING_DBUF_UPDATE_MODE') 31122 | #define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_MODE_MASK 0x03000000L | ^~~~~~~~~~~ drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_sh_mask.h:31122:111: note: in definition of macro 'OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_MODE_MASK' 31122 | #define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_MODE_MASK 0x03000000L | ^~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_optc.h:54:2: note: in expansion of macro 'SF' 54 | SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_RANGE_TIMING_DBUF_UPDATE_MODE, mask_sh),\ | ^~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:877:2: note: in expansion of macro 'TG_COMMON_MASK_SH_LIST_DCN2_0' 877 | TG_COMMON_MASK_SH_LIST_DCN2_0(_MASK) | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~ >> drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h:35:6: error: 'const struct dcn_hubp2_registers' has no member named 'DCHUBP_CNTL' 35 | SRI(DCHUBP_CNTL, HUBP, id),\ | ^~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:503:3: note: in definition of macro 'SRI' 503 | .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ | ^~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hubp.h:35:2: note: in expansion of macro 'HUBP_REG_LIST_DCN' 35 | HUBP_REG_LIST_DCN(id),\ | ^~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hubp.h:65:2: note: in expansion of macro 'HUBP_REG_LIST_DCN2_COMMON' 65 | HUBP_REG_LIST_DCN2_COMMON(id),\ | ^~~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:882:2: note: in expansion of macro 'HUBP_REG_LIST_DCN20' 882 | HUBP_REG_LIST_DCN20(id)\ | ^~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:886:3: note: in expansion of macro 'hubp_regs' 886 | hubp_regs(0), | ^~~~~~~~~ In file included from drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:68: >> drivers/gpu/drm/amd/include/navi10_ip_offset.h:269:52: warning: excess elements in struct initializer 269 | #define DCN_BASE__INST0_SEG2 0x000034C0 | ^~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:494:25: note: in expansion of macro 'DCN_BASE__INST0_SEG2' 494 | #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg | ^~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:496:19: note: in expansion of macro 'BASE_INNER' 496 | #define BASE(seg) BASE_INNER(seg) | ^~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:503:14: note: in expansion of macro 'BASE' 503 | .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ | ^~~~ drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h:35:2: note: in expansion of macro 'SRI' 35 | SRI(DCHUBP_CNTL, HUBP, id),\ | ^~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hubp.h:35:2: note: in expansion of macro 'HUBP_REG_LIST_DCN' 35 | HUBP_REG_LIST_DCN(id),\ | ^~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hubp.h:65:2: note: in expansion of macro 'HUBP_REG_LIST_DCN2_COMMON' 65 | HUBP_REG_LIST_DCN2_COMMON(id),\ | ^~~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:882:2: note: in expansion of macro 'HUBP_REG_LIST_DCN20' 882 | HUBP_REG_LIST_DCN20(id)\ | ^~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:886:3: note: in expansion of macro 'hubp_regs' 886 | hubp_regs(0), | ^~~~~~~~~ drivers/gpu/drm/amd/include/navi10_ip_offset.h:269:52: note: (near initialization for 'hubp_regs[0]') 269 | #define DCN_BASE__INST0_SEG2 0x000034C0 | ^~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:494:25: note: in expansion of macro 'DCN_BASE__INST0_SEG2' 494 | #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg | ^~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:496:19: note: in expansion of macro 'BASE_INNER' 496 | #define BASE(seg) BASE_INNER(seg) | ^~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:503:14: note: in expansion of macro 'BASE' 503 | .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ | ^~~~ drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h:35:2: note: in expansion of macro 'SRI' 35 | SRI(DCHUBP_CNTL, HUBP, id),\ | ^~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hubp.h:35:2: note: in expansion of macro 'HUBP_REG_LIST_DCN' 35 | HUBP_REG_LIST_DCN(id),\ | ^~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hubp.h:65:2: note: in expansion of macro 'HUBP_REG_LIST_DCN2_COMMON' 65 | HUBP_REG_LIST_DCN2_COMMON(id),\ | ^~~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:882:2: note: in expansion of macro 'HUBP_REG_LIST_DCN20' 882 | HUBP_REG_LIST_DCN20(id)\ | ^~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:886:3: note: in expansion of macro 'hubp_regs' 886 | hubp_regs(0), | ^~~~~~~~~ >> drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h:36:6: error: 'const struct dcn_hubp2_registers' has no member named 'HUBPREQ_DEBUG_DB' 36 | SRI(HUBPREQ_DEBUG_DB, HUBP, id),\ | ^~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:503:3: note: in definition of macro 'SRI' 503 | .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ | ^~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hubp.h:35:2: note: in expansion of macro 'HUBP_REG_LIST_DCN' 35 | HUBP_REG_LIST_DCN(id),\ | ^~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hubp.h:65:2: note: in expansion of macro 'HUBP_REG_LIST_DCN2_COMMON' 65 | HUBP_REG_LIST_DCN2_COMMON(id),\ | ^~~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:882:2: note: in expansion of macro 'HUBP_REG_LIST_DCN20' 882 | HUBP_REG_LIST_DCN20(id)\ | ^~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:886:3: note: in expansion of macro 'hubp_regs' 886 | hubp_regs(0), | ^~~~~~~~~ In file included from drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:68: >> drivers/gpu/drm/amd/include/navi10_ip_offset.h:269:52: warning: excess elements in struct initializer 269 | #define DCN_BASE__INST0_SEG2 0x000034C0 | ^~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:494:25: note: in expansion of macro 'DCN_BASE__INST0_SEG2' 494 | #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg | ^~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:496:19: note: in expansion of macro 'BASE_INNER' 496 | #define BASE(seg) BASE_INNER(seg) | ^~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:503:14: note: in expansion of macro 'BASE' 503 | .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ | ^~~~ drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h:36:2: note: in expansion of macro 'SRI' 36 | SRI(HUBPREQ_DEBUG_DB, HUBP, id),\ | ^~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hubp.h:35:2: note: in expansion of macro 'HUBP_REG_LIST_DCN' 35 | HUBP_REG_LIST_DCN(id),\ | ^~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hubp.h:65:2: note: in expansion of macro 'HUBP_REG_LIST_DCN2_COMMON' 65 | HUBP_REG_LIST_DCN2_COMMON(id),\ | ^~~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:882:2: note: in expansion of macro 'HUBP_REG_LIST_DCN20' 882 | HUBP_REG_LIST_DCN20(id)\ | ^~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:886:3: note: in expansion of macro 'hubp_regs' 886 | hubp_regs(0), | ^~~~~~~~~ drivers/gpu/drm/amd/include/navi10_ip_offset.h:269:52: note: (near initialization for 'hubp_regs[0]') 269 | #define DCN_BASE__INST0_SEG2 0x000034C0 | ^~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:494:25: note: in expansion of macro 'DCN_BASE__INST0_SEG2' 494 | #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg | ^~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:496:19: note: in expansion of macro 'BASE_INNER' 496 | #define BASE(seg) BASE_INNER(seg) | ^~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:503:14: note: in expansion of macro 'BASE' 503 | .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ | ^~~~ drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h:36:2: note: in expansion of macro 'SRI' 36 | SRI(HUBPREQ_DEBUG_DB, HUBP, id),\ | ^~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hubp.h:35:2: note: in expansion of macro 'HUBP_REG_LIST_DCN' 35 | HUBP_REG_LIST_DCN(id),\ | ^~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hubp.h:65:2: note: in expansion of macro 'HUBP_REG_LIST_DCN2_COMMON' 65 | HUBP_REG_LIST_DCN2_COMMON(id),\ | ^~~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:882:2: note: in expansion of macro 'HUBP_REG_LIST_DCN20' 882 | HUBP_REG_LIST_DCN20(id)\ | ^~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:886:3: note: in expansion of macro 'hubp_regs' 886 | hubp_regs(0), | ^~~~~~~~~ >> drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h:37:6: error: 'const struct dcn_hubp2_registers' has no member named 'HUBPREQ_DEBUG' 37 | SRI(HUBPREQ_DEBUG, HUBP, id),\ | ^~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:503:3: note: in definition of macro 'SRI' 503 | .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ | ^~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hubp.h:35:2: note: in expansion of macro 'HUBP_REG_LIST_DCN' 35 | HUBP_REG_LIST_DCN(id),\ | ^~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hubp.h:65:2: note: in expansion of macro 'HUBP_REG_LIST_DCN2_COMMON' 65 | HUBP_REG_LIST_DCN2_COMMON(id),\ | ^~~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:882:2: note: in expansion of macro 'HUBP_REG_LIST_DCN20' 882 | HUBP_REG_LIST_DCN20(id)\ | ^~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:886:3: note: in expansion of macro 'hubp_regs' 886 | hubp_regs(0), | ^~~~~~~~~ In file included from drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:68: >> drivers/gpu/drm/amd/include/navi10_ip_offset.h:269:52: warning: excess elements in struct initializer 269 | #define DCN_BASE__INST0_SEG2 0x000034C0 | ^~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:494:25: note: in expansion of macro 'DCN_BASE__INST0_SEG2' 494 | #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg | ^~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:496:19: note: in expansion of macro 'BASE_INNER' 496 | #define BASE(seg) BASE_INNER(seg) | ^~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:503:14: note: in expansion of macro 'BASE' 503 | .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ | ^~~~ drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h:37:2: note: in expansion of macro 'SRI' 37 | SRI(HUBPREQ_DEBUG, HUBP, id),\ | ^~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hubp.h:35:2: note: in expansion of macro 'HUBP_REG_LIST_DCN' 35 | HUBP_REG_LIST_DCN(id),\ | ^~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hubp.h:65:2: note: in expansion of macro 'HUBP_REG_LIST_DCN2_COMMON' 65 | HUBP_REG_LIST_DCN2_COMMON(id),\ | ^~~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:882:2: note: in expansion of macro 'HUBP_REG_LIST_DCN20' 882 | HUBP_REG_LIST_DCN20(id)\ | ^~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:886:3: note: in expansion of macro 'hubp_regs' 886 | hubp_regs(0), | ^~~~~~~~~ drivers/gpu/drm/amd/include/navi10_ip_offset.h:269:52: note: (near initialization for 'hubp_regs[0]') 269 | #define DCN_BASE__INST0_SEG2 0x000034C0 | ^~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:494:25: note: in expansion of macro 'DCN_BASE__INST0_SEG2' 494 | #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg | ^~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:496:19: note: in expansion of macro 'BASE_INNER' 496 | #define BASE(seg) BASE_INNER(seg) | ^~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:503:14: note: in expansion of macro 'BASE' 503 | .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ | ^~~~ drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h:37:2: note: in expansion of macro 'SRI' 37 | SRI(HUBPREQ_DEBUG, HUBP, id),\ | ^~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hubp.h:35:2: note: in expansion of macro 'HUBP_REG_LIST_DCN' 35 | HUBP_REG_LIST_DCN(id),\ | ^~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hubp.h:65:2: note: in expansion of macro 'HUBP_REG_LIST_DCN2_COMMON' 65 | HUBP_REG_LIST_DCN2_COMMON(id),\ | ^~~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:882:2: note: in expansion of macro 'HUBP_REG_LIST_DCN20' 882 | HUBP_REG_LIST_DCN20(id)\ | ^~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:886:3: note: in expansion of macro 'hubp_regs' 886 | hubp_regs(0), | ^~~~~~~~~ >> drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h:38:6: error: 'const struct dcn_hubp2_registers' has no member named 'DCSURF_ADDR_CONFIG' 38 | SRI(DCSURF_ADDR_CONFIG, HUBP, id),\ | ^~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:503:3: note: in definition of macro 'SRI' 503 | .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ | ^~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hubp.h:35:2: note: in expansion of macro 'HUBP_REG_LIST_DCN' 35 | HUBP_REG_LIST_DCN(id),\ | ^~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hubp.h:65:2: note: in expansion of macro 'HUBP_REG_LIST_DCN2_COMMON' 65 | HUBP_REG_LIST_DCN2_COMMON(id),\ | ^~~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:882:2: note: in expansion of macro 'HUBP_REG_LIST_DCN20' 882 | HUBP_REG_LIST_DCN20(id)\ | ^~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:886:3: note: in expansion of macro 'hubp_regs' 886 | hubp_regs(0), | ^~~~~~~~~ In file included from drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:68: >> drivers/gpu/drm/amd/include/navi10_ip_offset.h:269:52: warning: excess elements in struct initializer 269 | #define DCN_BASE__INST0_SEG2 0x000034C0 | ^~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:494:25: note: in expansion of macro 'DCN_BASE__INST0_SEG2' 494 | #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg | ^~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:496:19: note: in expansion of macro 'BASE_INNER' 496 | #define BASE(seg) BASE_INNER(seg) | ^~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:503:14: note: in expansion of macro 'BASE' 503 | .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ | ^~~~ drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h:38:2: note: in expansion of macro 'SRI' 38 | SRI(DCSURF_ADDR_CONFIG, HUBP, id),\ | ^~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hubp.h:35:2: note: in expansion of macro 'HUBP_REG_LIST_DCN' 35 | HUBP_REG_LIST_DCN(id),\ | ^~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hubp.h:65:2: note: in expansion of macro 'HUBP_REG_LIST_DCN2_COMMON' 65 | HUBP_REG_LIST_DCN2_COMMON(id),\ | ^~~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:882:2: note: in expansion of macro 'HUBP_REG_LIST_DCN20' 882 | HUBP_REG_LIST_DCN20(id)\ | ^~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:886:3: note: in expansion of macro 'hubp_regs' 886 | hubp_regs(0), | ^~~~~~~~~ drivers/gpu/drm/amd/include/navi10_ip_offset.h:269:52: note: (near initialization for 'hubp_regs[0]') 269 | #define DCN_BASE__INST0_SEG2 0x000034C0 | ^~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:494:25: note: in expansion of macro 'DCN_BASE__INST0_SEG2' 494 | #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg | ^~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:496:19: note: in expansion of macro 'BASE_INNER' 496 | #define BASE(seg) BASE_INNER(seg) | ^~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:503:14: note: in expansion of macro 'BASE' 503 | .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ | ^~~~ drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h:38:2: note: in expansion of macro 'SRI' 38 | SRI(DCSURF_ADDR_CONFIG, HUBP, id),\ | ^~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hubp.h:35:2: note: in expansion of macro 'HUBP_REG_LIST_DCN' 35 | HUBP_REG_LIST_DCN(id),\ | ^~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hubp.h:65:2: note: in expansion of macro 'HUBP_REG_LIST_DCN2_COMMON' 65 | HUBP_REG_LIST_DCN2_COMMON(id),\ | ^~~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:882:2: note: in expansion of macro 'HUBP_REG_LIST_DCN20' 882 | HUBP_REG_LIST_DCN20(id)\ | ^~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:886:3: note: in expansion of macro 'hubp_regs' 886 | hubp_regs(0), | ^~~~~~~~~ >> drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h:39:6: error: 'const struct dcn_hubp2_registers' has no member named 'DCSURF_TILING_CONFIG' 39 | SRI(DCSURF_TILING_CONFIG, HUBP, id),\ | ^~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:503:3: note: in definition of macro 'SRI' 503 | .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ | ^~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hubp.h:35:2: note: in expansion of macro 'HUBP_REG_LIST_DCN' 35 | HUBP_REG_LIST_DCN(id),\ | ^~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hubp.h:65:2: note: in expansion of macro 'HUBP_REG_LIST_DCN2_COMMON' 65 | HUBP_REG_LIST_DCN2_COMMON(id),\ | ^~~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:882:2: note: in expansion of macro 'HUBP_REG_LIST_DCN20' 882 | HUBP_REG_LIST_DCN20(id)\ | ^~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:886:3: note: in expansion of macro 'hubp_regs' 886 | hubp_regs(0), | ^~~~~~~~~ In file included from drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:68: >> drivers/gpu/drm/amd/include/navi10_ip_offset.h:269:52: warning: excess elements in struct initializer 269 | #define DCN_BASE__INST0_SEG2 0x000034C0 | ^~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:494:25: note: in expansion of macro 'DCN_BASE__INST0_SEG2' 494 | #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg | ^~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:496:19: note: in expansion of macro 'BASE_INNER' 496 | #define BASE(seg) BASE_INNER(seg) | ^~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:503:14: note: in expansion of macro 'BASE' 503 | .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ | ^~~~ drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h:39:2: note: in expansion of macro 'SRI' 39 | SRI(DCSURF_TILING_CONFIG, HUBP, id),\ | ^~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hubp.h:35:2: note: in expansion of macro 'HUBP_REG_LIST_DCN' 35 | HUBP_REG_LIST_DCN(id),\ | ^~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hubp.h:65:2: note: in expansion of macro 'HUBP_REG_LIST_DCN2_COMMON' 65 | HUBP_REG_LIST_DCN2_COMMON(id),\ | ^~~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:882:2: note: in expansion of macro 'HUBP_REG_LIST_DCN20' 882 | HUBP_REG_LIST_DCN20(id)\ | ^~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:886:3: note: in expansion of macro 'hubp_regs' 886 | hubp_regs(0), | ^~~~~~~~~ drivers/gpu/drm/amd/include/navi10_ip_offset.h:269:52: note: (near initialization for 'hubp_regs[0]') 269 | #define DCN_BASE__INST0_SEG2 0x000034C0 | ^~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:494:25: note: in expansion of macro 'DCN_BASE__INST0_SEG2' 494 | #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg | ^~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:496:19: note: in expansion of macro 'BASE_INNER' 496 | #define BASE(seg) BASE_INNER(seg) | ^~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:503:14: note: in expansion of macro 'BASE' 503 | .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ | ^~~~ drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h:39:2: note: in expansion of macro 'SRI' 39 | SRI(DCSURF_TILING_CONFIG, HUBP, id),\ | ^~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hubp.h:35:2: note: in expansion of macro 'HUBP_REG_LIST_DCN' 35 | HUBP_REG_LIST_DCN(id),\ | ^~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hubp.h:65:2: note: in expansion of macro 'HUBP_REG_LIST_DCN2_COMMON' 65 | HUBP_REG_LIST_DCN2_COMMON(id),\ | ^~~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:882:2: note: in expansion of macro 'HUBP_REG_LIST_DCN20' 882 | HUBP_REG_LIST_DCN20(id)\ | ^~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:886:3: note: in expansion of macro 'hubp_regs' 886 | hubp_regs(0), | ^~~~~~~~~ >> drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h:40:6: error: 'const struct dcn_hubp2_registers' has no member named 'DCSURF_SURFACE_PITCH' 40 | SRI(DCSURF_SURFACE_PITCH, HUBPREQ, id),\ | ^~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:503:3: note: in definition of macro 'SRI' 503 | .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ | ^~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hubp.h:35:2: note: in expansion of macro 'HUBP_REG_LIST_DCN' 35 | HUBP_REG_LIST_DCN(id),\ | ^~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hubp.h:65:2: note: in expansion of macro 'HUBP_REG_LIST_DCN2_COMMON' 65 | HUBP_REG_LIST_DCN2_COMMON(id),\ | ^~~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:882:2: note: in expansion of macro 'HUBP_REG_LIST_DCN20' 882 | HUBP_REG_LIST_DCN20(id)\ | ^~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:886:3: note: in expansion of macro 'hubp_regs' 886 | hubp_regs(0), | ^~~~~~~~~ In file included from drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:68: >> drivers/gpu/drm/amd/include/navi10_ip_offset.h:269:52: warning: excess elements in struct initializer 269 | #define DCN_BASE__INST0_SEG2 0x000034C0 | ^~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:494:25: note: in expansion of macro 'DCN_BASE__INST0_SEG2' 494 | #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg | ^~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:496:19: note: in expansion of macro 'BASE_INNER' 496 | #define BASE(seg) BASE_INNER(seg) | ^~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:503:14: note: in expansion of macro 'BASE' 503 | .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ | ^~~~ drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h:40:2: note: in expansion of macro 'SRI' 40 | SRI(DCSURF_SURFACE_PITCH, HUBPREQ, id),\ | ^~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hubp.h:35:2: note: in expansion of macro 'HUBP_REG_LIST_DCN' 35 | HUBP_REG_LIST_DCN(id),\ | ^~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hubp.h:65:2: note: in expansion of macro 'HUBP_REG_LIST_DCN2_COMMON' 65 | HUBP_REG_LIST_DCN2_COMMON(id),\ | ^~~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:882:2: note: in expansion of macro 'HUBP_REG_LIST_DCN20' 882 | HUBP_REG_LIST_DCN20(id)\ | ^~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:886:3: note: in expansion of macro 'hubp_regs' 886 | hubp_regs(0), | ^~~~~~~~~ drivers/gpu/drm/amd/include/navi10_ip_offset.h:269:52: note: (near initialization for 'hubp_regs[0]') 269 | #define DCN_BASE__INST0_SEG2 0x000034C0 | ^~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:494:25: note: in expansion of macro 'DCN_BASE__INST0_SEG2' 494 | #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg | ^~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:496:19: note: in expansion of macro 'BASE_INNER' 496 | #define BASE(seg) BASE_INNER(seg) | ^~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:503:14: note: in expansion of macro 'BASE' 503 | .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ | ^~~~ drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h:40:2: note: in expansion of macro 'SRI' 40 | SRI(DCSURF_SURFACE_PITCH, HUBPREQ, id),\ | ^~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hubp.h:35:2: note: in expansion of macro 'HUBP_REG_LIST_DCN' 35 | HUBP_REG_LIST_DCN(id),\ | ^~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hubp.h:65:2: note: in expansion of macro 'HUBP_REG_LIST_DCN2_COMMON' 65 | HUBP_REG_LIST_DCN2_COMMON(id),\ | ^~~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:882:2: note: in expansion of macro 'HUBP_REG_LIST_DCN20' 882 | HUBP_REG_LIST_DCN20(id)\ | ^~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:886:3: note: in expansion of macro 'hubp_regs' 886 | hubp_regs(0), | ^~~~~~~~~ >> drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h:41:6: error: 'const struct dcn_hubp2_registers' has no member named 'DCSURF_SURFACE_PITCH_C' 41 | SRI(DCSURF_SURFACE_PITCH_C, HUBPREQ, id),\ | ^~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:503:3: note: in definition of macro 'SRI' 503 | .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ | ^~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hubp.h:35:2: note: in expansion of macro 'HUBP_REG_LIST_DCN' 35 | HUBP_REG_LIST_DCN(id),\ | ^~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hubp.h:65:2: note: in expansion of macro 'HUBP_REG_LIST_DCN2_COMMON' 65 | HUBP_REG_LIST_DCN2_COMMON(id),\ | ^~~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:882:2: note: in expansion of macro 'HUBP_REG_LIST_DCN20' 882 | HUBP_REG_LIST_DCN20(id)\ | ^~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:886:3: note: in expansion of macro 'hubp_regs' 886 | hubp_regs(0), | ^~~~~~~~~ In file included from drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:68: >> drivers/gpu/drm/amd/include/navi10_ip_offset.h:269:52: warning: excess elements in struct initializer 269 | #define DCN_BASE__INST0_SEG2 0x000034C0 | ^~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:494:25: note: in expansion of macro 'DCN_BASE__INST0_SEG2' 494 | #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg | ^~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:496:19: note: in expansion of macro 'BASE_INNER' 496 | #define BASE(seg) BASE_INNER(seg) | ^~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:503:14: note: in expansion of macro 'BASE' 503 | .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ | ^~~~ drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h:41:2: note: in expansion of macro 'SRI' 41 | SRI(DCSURF_SURFACE_PITCH_C, HUBPREQ, id),\ | ^~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hubp.h:35:2: note: in expansion of macro 'HUBP_REG_LIST_DCN' 35 | HUBP_REG_LIST_DCN(id),\ | ^~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hubp.h:65:2: note: in expansion of macro 'HUBP_REG_LIST_DCN2_COMMON' 65 | HUBP_REG_LIST_DCN2_COMMON(id),\ | ^~~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:882:2: note: in expansion of macro 'HUBP_REG_LIST_DCN20' 882 | HUBP_REG_LIST_DCN20(id)\ | ^~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:886:3: note: in expansion of macro 'hubp_regs' 886 | hubp_regs(0), | ^~~~~~~~~ drivers/gpu/drm/amd/include/navi10_ip_offset.h:269:52: note: (near initialization for 'hubp_regs[0]') 269 | #define DCN_BASE__INST0_SEG2 0x000034C0 | ^~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:494:25: note: in expansion of macro 'DCN_BASE__INST0_SEG2' 494 | #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg | ^~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:496:19: note: in expansion of macro 'BASE_INNER' 496 | #define BASE(seg) BASE_INNER(seg) | ^~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:503:14: note: in expansion of macro 'BASE' 503 | .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ | ^~~~ drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h:41:2: note: in expansion of macro 'SRI' 41 | SRI(DCSURF_SURFACE_PITCH_C, HUBPREQ, id),\ | ^~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hubp.h:35:2: note: in expansion of macro 'HUBP_REG_LIST_DCN' 35 | HUBP_REG_LIST_DCN(id),\ | ^~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hubp.h:65:2: note: in expansion of macro 'HUBP_REG_LIST_DCN2_COMMON' 65 | HUBP_REG_LIST_DCN2_COMMON(id),\ | ^~~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:882:2: note: in expansion of macro 'HUBP_REG_LIST_DCN20' 882 | HUBP_REG_LIST_DCN20(id)\ | ^~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:886:3: note: in expansion of macro 'hubp_regs' 886 | hubp_regs(0), | ^~~~~~~~~ >> drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h:42:6: error: 'const struct dcn_hubp2_registers' has no member named 'DCSURF_SURFACE_CONFIG' 42 | SRI(DCSURF_SURFACE_CONFIG, HUBP, id),\ | ^~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:503:3: note: in definition of macro 'SRI' 503 | .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ | ^~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hubp.h:35:2: note: in expansion of macro 'HUBP_REG_LIST_DCN' 35 | HUBP_REG_LIST_DCN(id),\ | ^~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hubp.h:65:2: note: in expansion of macro 'HUBP_REG_LIST_DCN2_COMMON' 65 | HUBP_REG_LIST_DCN2_COMMON(id),\ | ^~~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:882:2: note: in expansion of macro 'HUBP_REG_LIST_DCN20' 882 | HUBP_REG_LIST_DCN20(id)\ | ^~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:886:3: note: in expansion of macro 'hubp_regs' 886 | hubp_regs(0), | ^~~~~~~~~ In file included from drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:68: >> drivers/gpu/drm/amd/include/navi10_ip_offset.h:269:52: warning: excess elements in struct initializer 269 | #define DCN_BASE__INST0_SEG2 0x000034C0 | ^~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:494:25: note: in expansion of macro 'DCN_BASE__INST0_SEG2' 494 | #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg | ^~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:496:19: note: in expansion of macro 'BASE_INNER' 496 | #define BASE(seg) BASE_INNER(seg) | ^~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:503:14: note: in expansion of macro 'BASE' 503 | .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ | ^~~~ drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h:42:2: note: in expansion of macro 'SRI' 42 | SRI(DCSURF_SURFACE_CONFIG, HUBP, id),\ | ^~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hubp.h:35:2: note: in expansion of macro 'HUBP_REG_LIST_DCN' 35 | HUBP_REG_LIST_DCN(id),\ | ^~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hubp.h:65:2: note: in expansion of macro 'HUBP_REG_LIST_DCN2_COMMON' 65 | HUBP_REG_LIST_DCN2_COMMON(id),\ | ^~~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:882:2: note: in expansion of macro 'HUBP_REG_LIST_DCN20' 882 | HUBP_REG_LIST_DCN20(id)\ | ^~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:886:3: note: in expansion of macro 'hubp_regs' 886 | hubp_regs(0), | ^~~~~~~~~ drivers/gpu/drm/amd/include/navi10_ip_offset.h:269:52: note: (near initialization for 'hubp_regs[0]') 269 | #define DCN_BASE__INST0_SEG2 0x000034C0 | ^~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:494:25: note: in expansion of macro 'DCN_BASE__INST0_SEG2' 494 | #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg | ^~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:496:19: note: in expansion of macro 'BASE_INNER' 496 | #define BASE(seg) BASE_INNER(seg) | ^~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:503:14: note: in expansion of macro 'BASE' 503 | .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ | ^~~~ drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h:42:2: note: in expansion of macro 'SRI' 42 | SRI(DCSURF_SURFACE_CONFIG, HUBP, id),\ | ^~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hubp.h:35:2: note: in expansion of macro 'HUBP_REG_LIST_DCN' 35 | HUBP_REG_LIST_DCN(id),\ | ^~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hubp.h:65:2: note: in expansion of macro 'HUBP_REG_LIST_DCN2_COMMON' 65 | HUBP_REG_LIST_DCN2_COMMON(id),\ | ^~~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:882:2: note: in expansion of macro 'HUBP_REG_LIST_DCN20' 882 | HUBP_REG_LIST_DCN20(id)\ | ^~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:886:3: note: in expansion of macro 'hubp_regs' 886 | hubp_regs(0), | ^~~~~~~~~ >> drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h:43:6: error: 'const struct dcn_hubp2_registers' has no member named 'DCSURF_FLIP_CONTROL' 43 | SRI(DCSURF_FLIP_CONTROL, HUBPREQ, id),\ | ^~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:503:3: note: in definition of macro 'SRI' 503 | .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ | ^~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hubp.h:35:2: note: in expansion of macro 'HUBP_REG_LIST_DCN' 35 | HUBP_REG_LIST_DCN(id),\ | ^~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hubp.h:65:2: note: in expansion of macro 'HUBP_REG_LIST_DCN2_COMMON' 65 | HUBP_REG_LIST_DCN2_COMMON(id),\ | ^~~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:882:2: note: in expansion of macro 'HUBP_REG_LIST_DCN20' 882 | HUBP_REG_LIST_DCN20(id)\ | ^~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:886:3: note: in expansion of macro 'hubp_regs' 886 | hubp_regs(0), | ^~~~~~~~~ In file included from drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:68: drivers/gpu/drm/amd/include/navi10_ip_offset.h:269:52: warning: excess elements in struct initializer 269 | #define DCN_BASE__INST0_SEG2 0x000034C0 | ^~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:494:25: note: in expansion of macro 'DCN_BASE__INST0_SEG2' 494 | #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg | ^~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:496:19: note: in expansion of macro 'BASE_INNER' 496 | #define BASE(seg) BASE_INNER(seg) | ^~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:503:14: note: in expansion of macro 'BASE' 503 | .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ | ^~~~ drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h:43:2: note: in expansion of macro 'SRI' 43 | SRI(DCSURF_FLIP_CONTROL, HUBPREQ, id),\ | ^~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hubp.h:35:2: note: in expansion of macro 'HUBP_REG_LIST_DCN' 35 | HUBP_REG_LIST_DCN(id),\ | ^~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hubp.h:65:2: note: in expansion of macro 'HUBP_REG_LIST_DCN2_COMMON' 65 | HUBP_REG_LIST_DCN2_COMMON(id),\ | ^~~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:882:2: note: in expansion of macro 'HUBP_REG_LIST_DCN20' 882 | HUBP_REG_LIST_DCN20(id)\ | ^~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:886:3: note: in expansion of macro 'hubp_regs' 886 | hubp_regs(0), | ^~~~~~~~~ drivers/gpu/drm/amd/include/navi10_ip_offset.h:269:52: note: (near initialization for 'hubp_regs[0]') 269 | #define DCN_BASE__INST0_SEG2 0x000034C0 | ^~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:494:25: note: in expansion of macro 'DCN_BASE__INST0_SEG2' 494 | #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg | ^~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:496:19: note: in expansion of macro 'BASE_INNER' 496 | #define BASE(seg) BASE_INNER(seg) | ^~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:503:14: note: in expansion of macro 'BASE' 503 | .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ | ^~~~ drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h:43:2: note: in expansion of macro 'SRI' 43 | SRI(DCSURF_FLIP_CONTROL, HUBPREQ, id),\ | ^~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hubp.h:35:2: note: in expansion of macro 'HUBP_REG_LIST_DCN' 35 | HUBP_REG_LIST_DCN(id),\ | ^~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hubp.h:65:2: note: in expansion of macro 'HUBP_REG_LIST_DCN2_COMMON' 65 | HUBP_REG_LIST_DCN2_COMMON(id),\ | ^~~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:882:2: note: in expansion of macro 'HUBP_REG_LIST_DCN20' 882 | HUBP_REG_LIST_DCN20(id)\ | ^~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:886:3: note: in expansion of macro 'hubp_regs' 886 | hubp_regs(0), | ^~~~~~~~~ drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h:44:6: error: 'const struct dcn_hubp2_registers' has no member named 'DCSURF_PRI_VIEWPORT_DIMENSION' 44 | SRI(DCSURF_PRI_VIEWPORT_DIMENSION, HUBP, id), \ | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:503:3: note: in definition of macro 'SRI' 503 | .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ | ^~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hubp.h:35:2: note: in expansion of macro 'HUBP_REG_LIST_DCN' 35 | HUBP_REG_LIST_DCN(id),\ | ^~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hubp.h:65:2: note: in expansion of macro 'HUBP_REG_LIST_DCN2_COMMON' 65 | HUBP_REG_LIST_DCN2_COMMON(id),\ | ^~~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:882:2: note: in expansion of macro 'HUBP_REG_LIST_DCN20' 882 | HUBP_REG_LIST_DCN20(id)\ | ^~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:886:3: note: in expansion of macro 'hubp_regs' 886 | hubp_regs(0), | ^~~~~~~~~ In file included from drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:68: drivers/gpu/drm/amd/include/navi10_ip_offset.h:269:52: warning: excess elements in struct initializer 269 | #define DCN_BASE__INST0_SEG2 0x000034C0 | ^~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:494:25: note: in expansion of macro 'DCN_BASE__INST0_SEG2' 494 | #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg | ^~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:496:19: note: in expansion of macro 'BASE_INNER' 496 | #define BASE(seg) BASE_INNER(seg) | ^~~~~~~~~~ .. vim +/DCN21_HUBP_REG_COMMON_VARIABLE_LIST +164 drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hubp.h bbeb64d0eb78f4 Harry Wentland 2019-05-07 30 bbeb64d0eb78f4 Harry Wentland 2019-05-07 31 #define TO_DCN20_HUBP(hubp)\ bbeb64d0eb78f4 Harry Wentland 2019-05-07 32 container_of(hubp, struct dcn20_hubp, base) bbeb64d0eb78f4 Harry Wentland 2019-05-07 33 0213541d4b6b24 Yongqiang Sun 2019-03-28 34 #define HUBP_REG_LIST_DCN2_COMMON(id)\ bbeb64d0eb78f4 Harry Wentland 2019-05-07 35 HUBP_REG_LIST_DCN(id),\ bbeb64d0eb78f4 Harry Wentland 2019-05-07 36 HUBP_REG_LIST_DCN_VM(id),\ bbeb64d0eb78f4 Harry Wentland 2019-05-07 @37 SRI(PREFETCH_SETTINGS, HUBPREQ, id),\ bbeb64d0eb78f4 Harry Wentland 2019-05-07 @38 SRI(PREFETCH_SETTINGS_C, HUBPREQ, id),\ bbeb64d0eb78f4 Harry Wentland 2019-05-07 @39 SRI(DCN_VM_SYSTEM_APERTURE_LOW_ADDR, HUBPREQ, id),\ bbeb64d0eb78f4 Harry Wentland 2019-05-07 @40 SRI(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR, HUBPREQ, id),\ bbeb64d0eb78f4 Harry Wentland 2019-05-07 @41 SRI(CURSOR_SETTINGS, HUBPREQ, id), \ bbeb64d0eb78f4 Harry Wentland 2019-05-07 @42 SRI(CURSOR_SURFACE_ADDRESS_HIGH, CURSOR0_, id), \ bbeb64d0eb78f4 Harry Wentland 2019-05-07 @43 SRI(CURSOR_SURFACE_ADDRESS, CURSOR0_, id), \ bbeb64d0eb78f4 Harry Wentland 2019-05-07 @44 SRI(CURSOR_SIZE, CURSOR0_, id), \ bbeb64d0eb78f4 Harry Wentland 2019-05-07 @45 SRI(CURSOR_CONTROL, CURSOR0_, id), \ bbeb64d0eb78f4 Harry Wentland 2019-05-07 @46 SRI(CURSOR_POSITION, CURSOR0_, id), \ bbeb64d0eb78f4 Harry Wentland 2019-05-07 @47 SRI(CURSOR_HOT_SPOT, CURSOR0_, id), \ bbeb64d0eb78f4 Harry Wentland 2019-05-07 @48 SRI(CURSOR_DST_OFFSET, CURSOR0_, id), \ bbeb64d0eb78f4 Harry Wentland 2019-05-07 @49 SRI(DMDATA_ADDRESS_HIGH, CURSOR0_, id), \ bbeb64d0eb78f4 Harry Wentland 2019-05-07 @50 SRI(DMDATA_ADDRESS_LOW, CURSOR0_, id), \ bbeb64d0eb78f4 Harry Wentland 2019-05-07 @51 SRI(DMDATA_CNTL, CURSOR0_, id), \ bbeb64d0eb78f4 Harry Wentland 2019-05-07 @52 SRI(DMDATA_SW_CNTL, CURSOR0_, id), \ bbeb64d0eb78f4 Harry Wentland 2019-05-07 @53 SRI(DMDATA_QOS_CNTL, CURSOR0_, id), \ bbeb64d0eb78f4 Harry Wentland 2019-05-07 @54 SRI(DMDATA_SW_DATA, CURSOR0_, id), \ bbeb64d0eb78f4 Harry Wentland 2019-05-07 @55 SRI(DMDATA_STATUS, CURSOR0_, id),\ bbeb64d0eb78f4 Harry Wentland 2019-05-07 @56 SRI(FLIP_PARAMETERS_0, HUBPREQ, id),\ bbeb64d0eb78f4 Harry Wentland 2019-05-07 @57 SRI(FLIP_PARAMETERS_1, HUBPREQ, id),\ bbeb64d0eb78f4 Harry Wentland 2019-05-07 @58 SRI(FLIP_PARAMETERS_2, HUBPREQ, id),\ 4850ce697f9892 Charlene Liu 2019-05-07 @59 SRI(DCN_CUR1_TTU_CNTL0, HUBPREQ, id),\ bbeb64d0eb78f4 Harry Wentland 2019-05-07 @60 SRI(DCN_CUR1_TTU_CNTL1, HUBPREQ, id),\ bbeb64d0eb78f4 Harry Wentland 2019-05-07 @61 SRI(DCSURF_FLIP_CONTROL2, HUBPREQ, id), \ 0213541d4b6b24 Yongqiang Sun 2019-03-28 @62 SRI(VMID_SETTINGS_0, HUBPREQ, id) 0213541d4b6b24 Yongqiang Sun 2019-03-28 63 0213541d4b6b24 Yongqiang Sun 2019-03-28 64 #define HUBP_REG_LIST_DCN20(id)\ 0213541d4b6b24 Yongqiang Sun 2019-03-28 65 HUBP_REG_LIST_DCN2_COMMON(id),\ bbeb64d0eb78f4 Harry Wentland 2019-05-07 @66 SR(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB),\ bbeb64d0eb78f4 Harry Wentland 2019-05-07 @67 SR(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB) bbeb64d0eb78f4 Harry Wentland 2019-05-07 68 c70b4016306a10 Charlene Liu 2019-06-05 69 #define HUBP_MASK_SH_LIST_DCN2_SHARE_COMMON(mask_sh)\ c70b4016306a10 Charlene Liu 2019-06-05 70 HUBP_MASK_SH_LIST_DCN_SHARE_COMMON(mask_sh),\ bbeb64d0eb78f4 Harry Wentland 2019-05-07 71 HUBP_MASK_SH_LIST_DCN_VM(mask_sh),\ bbeb64d0eb78f4 Harry Wentland 2019-05-07 @72 HUBP_SF(HUBP0_DCSURF_SURFACE_CONFIG, ROTATION_ANGLE, mask_sh),\ bbeb64d0eb78f4 Harry Wentland 2019-05-07 @73 HUBP_SF(HUBP0_DCSURF_SURFACE_CONFIG, H_MIRROR_EN, mask_sh),\ bbeb64d0eb78f4 Harry Wentland 2019-05-07 @74 HUBP_SF(HUBPREQ0_PREFETCH_SETTINGS, DST_Y_PREFETCH, mask_sh),\ bbeb64d0eb78f4 Harry Wentland 2019-05-07 @75 HUBP_SF(HUBPREQ0_PREFETCH_SETTINGS, VRATIO_PREFETCH, mask_sh),\ bbeb64d0eb78f4 Harry Wentland 2019-05-07 @76 HUBP_SF(HUBPREQ0_PREFETCH_SETTINGS_C, VRATIO_PREFETCH_C, mask_sh),\ bbeb64d0eb78f4 Harry Wentland 2019-05-07 @77 HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR, MC_VM_SYSTEM_APERTURE_LOW_ADDR, mask_sh),\ bbeb64d0eb78f4 Harry Wentland 2019-05-07 @78 HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR, MC_VM_SYSTEM_APERTURE_HIGH_ADDR, mask_sh),\ bbeb64d0eb78f4 Harry Wentland 2019-05-07 @79 HUBP_SF(HUBPREQ0_CURSOR_SETTINGS, CURSOR0_DST_Y_OFFSET, mask_sh), \ bbeb64d0eb78f4 Harry Wentland 2019-05-07 @80 HUBP_SF(HUBPREQ0_CURSOR_SETTINGS, CURSOR0_CHUNK_HDL_ADJUST, mask_sh), \ bbeb64d0eb78f4 Harry Wentland 2019-05-07 @81 HUBP_SF(CURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH, CURSOR_SURFACE_ADDRESS_HIGH, mask_sh), \ bbeb64d0eb78f4 Harry Wentland 2019-05-07 @82 HUBP_SF(CURSOR0_0_CURSOR_SURFACE_ADDRESS, CURSOR_SURFACE_ADDRESS, mask_sh), \ bbeb64d0eb78f4 Harry Wentland 2019-05-07 @83 HUBP_SF(CURSOR0_0_CURSOR_SIZE, CURSOR_WIDTH, mask_sh), \ bbeb64d0eb78f4 Harry Wentland 2019-05-07 @84 HUBP_SF(CURSOR0_0_CURSOR_SIZE, CURSOR_HEIGHT, mask_sh), \ bbeb64d0eb78f4 Harry Wentland 2019-05-07 @85 HUBP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_MODE, mask_sh), \ bbeb64d0eb78f4 Harry Wentland 2019-05-07 @86 HUBP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_2X_MAGNIFY, mask_sh), \ bbeb64d0eb78f4 Harry Wentland 2019-05-07 @87 HUBP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_PITCH, mask_sh), \ bbeb64d0eb78f4 Harry Wentland 2019-05-07 @88 HUBP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_LINES_PER_CHUNK, mask_sh), \ bbeb64d0eb78f4 Harry Wentland 2019-05-07 @89 HUBP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_ENABLE, mask_sh), \ bbeb64d0eb78f4 Harry Wentland 2019-05-07 @90 HUBP_SF(CURSOR0_0_CURSOR_POSITION, CURSOR_X_POSITION, mask_sh), \ bbeb64d0eb78f4 Harry Wentland 2019-05-07 @91 HUBP_SF(CURSOR0_0_CURSOR_POSITION, CURSOR_Y_POSITION, mask_sh), \ bbeb64d0eb78f4 Harry Wentland 2019-05-07 @92 HUBP_SF(CURSOR0_0_CURSOR_HOT_SPOT, CURSOR_HOT_SPOT_X, mask_sh), \ bbeb64d0eb78f4 Harry Wentland 2019-05-07 @93 HUBP_SF(CURSOR0_0_CURSOR_HOT_SPOT, CURSOR_HOT_SPOT_Y, mask_sh), \ bbeb64d0eb78f4 Harry Wentland 2019-05-07 @94 HUBP_SF(CURSOR0_0_CURSOR_DST_OFFSET, CURSOR_DST_X_OFFSET, mask_sh), \ bbeb64d0eb78f4 Harry Wentland 2019-05-07 @95 HUBP_SF(CURSOR0_0_DMDATA_ADDRESS_HIGH, DMDATA_ADDRESS_HIGH, mask_sh), \ bbeb64d0eb78f4 Harry Wentland 2019-05-07 @96 HUBP_SF(CURSOR0_0_DMDATA_CNTL, DMDATA_MODE, mask_sh), \ bbeb64d0eb78f4 Harry Wentland 2019-05-07 @97 HUBP_SF(CURSOR0_0_DMDATA_CNTL, DMDATA_UPDATED, mask_sh), \ bbeb64d0eb78f4 Harry Wentland 2019-05-07 @98 HUBP_SF(CURSOR0_0_DMDATA_CNTL, DMDATA_REPEAT, mask_sh), \ bbeb64d0eb78f4 Harry Wentland 2019-05-07 @99 HUBP_SF(CURSOR0_0_DMDATA_CNTL, DMDATA_SIZE, mask_sh), \ bbeb64d0eb78f4 Harry Wentland 2019-05-07 @100 HUBP_SF(CURSOR0_0_DMDATA_SW_CNTL, DMDATA_SW_UPDATED, mask_sh), \ bbeb64d0eb78f4 Harry Wentland 2019-05-07 @101 HUBP_SF(CURSOR0_0_DMDATA_SW_CNTL, DMDATA_SW_REPEAT, mask_sh), \ bbeb64d0eb78f4 Harry Wentland 2019-05-07 @102 HUBP_SF(CURSOR0_0_DMDATA_SW_CNTL, DMDATA_SW_SIZE, mask_sh), \ bbeb64d0eb78f4 Harry Wentland 2019-05-07 @103 HUBP_SF(CURSOR0_0_DMDATA_QOS_CNTL, DMDATA_QOS_MODE, mask_sh), \ bbeb64d0eb78f4 Harry Wentland 2019-05-07 @104 HUBP_SF(CURSOR0_0_DMDATA_QOS_CNTL, DMDATA_QOS_LEVEL, mask_sh), \ bbeb64d0eb78f4 Harry Wentland 2019-05-07 @105 HUBP_SF(CURSOR0_0_DMDATA_QOS_CNTL, DMDATA_DL_DELTA, mask_sh), \ bbeb64d0eb78f4 Harry Wentland 2019-05-07 @106 HUBP_SF(CURSOR0_0_DMDATA_STATUS, DMDATA_DONE, mask_sh),\ bbeb64d0eb78f4 Harry Wentland 2019-05-07 @107 HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_0, DST_Y_PER_VM_FLIP, mask_sh),\ bbeb64d0eb78f4 Harry Wentland 2019-05-07 @108 HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_0, DST_Y_PER_ROW_FLIP, mask_sh),\ bbeb64d0eb78f4 Harry Wentland 2019-05-07 @109 HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_1, REFCYC_PER_PTE_GROUP_FLIP_L, mask_sh),\ bbeb64d0eb78f4 Harry Wentland 2019-05-07 @110 HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_2, REFCYC_PER_META_CHUNK_FLIP_L, mask_sh),\ bbeb64d0eb78f4 Harry Wentland 2019-05-07 @111 HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_VREADY_AT_OR_AFTER_VSYNC, mask_sh),\ bbeb64d0eb78f4 Harry Wentland 2019-05-07 @112 HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_DISABLE_STOP_DATA_DURING_VM, mask_sh),\ bbeb64d0eb78f4 Harry Wentland 2019-05-07 @113 HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, HUBPREQ_MASTER_UPDATE_LOCK_STATUS, mask_sh),\ bbeb64d0eb78f4 Harry Wentland 2019-05-07 @114 HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL2, SURFACE_GSL_ENABLE, mask_sh),\ bbeb64d0eb78f4 Harry Wentland 2019-05-07 @115 HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL2, SURFACE_TRIPLE_BUFFER_ENABLE, mask_sh),\ 0213541d4b6b24 Yongqiang Sun 2019-03-28 @116 HUBP_SF(HUBPREQ0_VMID_SETTINGS_0, VMID, mask_sh) 0213541d4b6b24 Yongqiang Sun 2019-03-28 117 c70b4016306a10 Charlene Liu 2019-06-05 118 /*DCN2.x and DCN1.x*/ c70b4016306a10 Charlene Liu 2019-06-05 119 #define HUBP_MASK_SH_LIST_DCN2_COMMON(mask_sh)\ c70b4016306a10 Charlene Liu 2019-06-05 120 HUBP_MASK_SH_LIST_DCN2_SHARE_COMMON(mask_sh),\ c70b4016306a10 Charlene Liu 2019-06-05 @121 HUBP_SF(HUBP0_DCSURF_TILING_CONFIG, RB_ALIGNED, mask_sh),\ c70b4016306a10 Charlene Liu 2019-06-05 @122 HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, MPTE_GROUP_SIZE, mask_sh),\ c70b4016306a10 Charlene Liu 2019-06-05 @123 HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, MPTE_GROUP_SIZE_C, mask_sh) c70b4016306a10 Charlene Liu 2019-06-05 124 c70b4016306a10 Charlene Liu 2019-06-05 125 /*DCN2.0 specific*/ 0213541d4b6b24 Yongqiang Sun 2019-03-28 126 #define HUBP_MASK_SH_LIST_DCN20(mask_sh)\ 0213541d4b6b24 Yongqiang Sun 2019-03-28 127 HUBP_MASK_SH_LIST_DCN2_COMMON(mask_sh),\ bbeb64d0eb78f4 Harry Wentland 2019-05-07 @128 HUBP_SF(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, DCN_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM, mask_sh),\ bbeb64d0eb78f4 Harry Wentland 2019-05-07 @129 HUBP_SF(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, mask_sh),\ bbeb64d0eb78f4 Harry Wentland 2019-05-07 @130 HUBP_SF(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, mask_sh) bbeb64d0eb78f4 Harry Wentland 2019-05-07 131 c70b4016306a10 Charlene Liu 2019-06-05 132 /*DCN2.x */ bbeb64d0eb78f4 Harry Wentland 2019-05-07 133 #define DCN2_HUBP_REG_COMMON_VARIABLE_LIST \ bbeb64d0eb78f4 Harry Wentland 2019-05-07 134 HUBP_COMMON_REG_VARIABLE_LIST; \ bbeb64d0eb78f4 Harry Wentland 2019-05-07 135 uint32_t DMDATA_ADDRESS_HIGH; \ bbeb64d0eb78f4 Harry Wentland 2019-05-07 136 uint32_t DMDATA_ADDRESS_LOW; \ bbeb64d0eb78f4 Harry Wentland 2019-05-07 137 uint32_t DMDATA_CNTL; \ bbeb64d0eb78f4 Harry Wentland 2019-05-07 138 uint32_t DMDATA_SW_CNTL; \ bbeb64d0eb78f4 Harry Wentland 2019-05-07 139 uint32_t DMDATA_QOS_CNTL; \ bbeb64d0eb78f4 Harry Wentland 2019-05-07 140 uint32_t DMDATA_SW_DATA; \ bbeb64d0eb78f4 Harry Wentland 2019-05-07 141 uint32_t DMDATA_STATUS;\ bbeb64d0eb78f4 Harry Wentland 2019-05-07 142 uint32_t DCSURF_FLIP_CONTROL2;\ bbeb64d0eb78f4 Harry Wentland 2019-05-07 143 uint32_t FLIP_PARAMETERS_0;\ bbeb64d0eb78f4 Harry Wentland 2019-05-07 144 uint32_t FLIP_PARAMETERS_1;\ bbeb64d0eb78f4 Harry Wentland 2019-05-07 145 uint32_t FLIP_PARAMETERS_2;\ 4850ce697f9892 Charlene Liu 2019-05-07 146 uint32_t DCN_CUR1_TTU_CNTL0;\ bbeb64d0eb78f4 Harry Wentland 2019-05-07 147 uint32_t DCN_CUR1_TTU_CNTL1;\ c70b4016306a10 Charlene Liu 2019-06-05 148 uint32_t VMID_SETTINGS_0 c70b4016306a10 Charlene Liu 2019-06-05 149 bbeb64d0eb78f4 Harry Wentland 2019-05-07 150 6162ba9234c124 Yifan Zhang 2019-11-28 151 #if defined(CONFIG_DRM_AMD_DC_DCN2_1) 35b82ba8f2fa9b Bhawanpreet Lakha 2019-08-28 152 #define DCN21_HUBP_REG_COMMON_VARIABLE_LIST \ 35b82ba8f2fa9b Bhawanpreet Lakha 2019-08-28 153 DCN2_HUBP_REG_COMMON_VARIABLE_LIST; \ 35b82ba8f2fa9b Bhawanpreet Lakha 2019-08-28 154 uint32_t FLIP_PARAMETERS_3;\ 35b82ba8f2fa9b Bhawanpreet Lakha 2019-08-28 155 uint32_t FLIP_PARAMETERS_4;\ 35b82ba8f2fa9b Bhawanpreet Lakha 2019-08-28 156 uint32_t FLIP_PARAMETERS_5;\ 35b82ba8f2fa9b Bhawanpreet Lakha 2019-08-28 157 uint32_t FLIP_PARAMETERS_6;\ 35b82ba8f2fa9b Bhawanpreet Lakha 2019-08-28 158 uint32_t VBLANK_PARAMETERS_5;\ 35b82ba8f2fa9b Bhawanpreet Lakha 2019-08-28 159 uint32_t VBLANK_PARAMETERS_6 6162ba9234c124 Yifan Zhang 2019-11-28 160 #endif 35b82ba8f2fa9b Bhawanpreet Lakha 2019-08-28 161 d2898ece6bedb5 Bhawanpreet Lakha 2020-05-21 162 #if defined(CONFIG_DRM_AMD_DC_DCN3_0) d2898ece6bedb5 Bhawanpreet Lakha 2020-05-21 163 #define DCN30_HUBP_REG_COMMON_VARIABLE_LIST \ d2898ece6bedb5 Bhawanpreet Lakha 2020-05-21 @164 DCN21_HUBP_REG_COMMON_VARIABLE_LIST;\ d2898ece6bedb5 Bhawanpreet Lakha 2020-05-21 165 uint32_t DCN_DMDATA_VM_CNTL d2898ece6bedb5 Bhawanpreet Lakha 2020-05-21 166 #endif d2898ece6bedb5 Bhawanpreet Lakha 2020-05-21 167 bbeb64d0eb78f4 Harry Wentland 2019-05-07 168 #define DCN2_HUBP_REG_FIELD_VARIABLE_LIST(type) \ c70b4016306a10 Charlene Liu 2019-06-05 169 DCN_HUBP_REG_FIELD_BASE_LIST(type); \ bbeb64d0eb78f4 Harry Wentland 2019-05-07 170 type DMDATA_ADDRESS_HIGH;\ bbeb64d0eb78f4 Harry Wentland 2019-05-07 171 type DMDATA_MODE;\ bbeb64d0eb78f4 Harry Wentland 2019-05-07 172 type DMDATA_UPDATED;\ bbeb64d0eb78f4 Harry Wentland 2019-05-07 173 type DMDATA_REPEAT;\ bbeb64d0eb78f4 Harry Wentland 2019-05-07 174 type DMDATA_SIZE;\ bbeb64d0eb78f4 Harry Wentland 2019-05-07 175 type DMDATA_SW_UPDATED;\ bbeb64d0eb78f4 Harry Wentland 2019-05-07 176 type DMDATA_SW_REPEAT;\ bbeb64d0eb78f4 Harry Wentland 2019-05-07 177 type DMDATA_SW_SIZE;\ bbeb64d0eb78f4 Harry Wentland 2019-05-07 178 type DMDATA_QOS_MODE;\ bbeb64d0eb78f4 Harry Wentland 2019-05-07 179 type DMDATA_QOS_LEVEL;\ bbeb64d0eb78f4 Harry Wentland 2019-05-07 180 type DMDATA_DL_DELTA;\ bbeb64d0eb78f4 Harry Wentland 2019-05-07 181 type DMDATA_DONE;\ bbeb64d0eb78f4 Harry Wentland 2019-05-07 182 type DST_Y_PER_VM_FLIP;\ bbeb64d0eb78f4 Harry Wentland 2019-05-07 183 type DST_Y_PER_ROW_FLIP;\ bbeb64d0eb78f4 Harry Wentland 2019-05-07 184 type REFCYC_PER_PTE_GROUP_FLIP_L;\ bbeb64d0eb78f4 Harry Wentland 2019-05-07 185 type REFCYC_PER_META_CHUNK_FLIP_L;\ bbeb64d0eb78f4 Harry Wentland 2019-05-07 186 type HUBP_VREADY_AT_OR_AFTER_VSYNC;\ bbeb64d0eb78f4 Harry Wentland 2019-05-07 187 type HUBP_DISABLE_STOP_DATA_DURING_VM;\ bbeb64d0eb78f4 Harry Wentland 2019-05-07 188 type HUBPREQ_MASTER_UPDATE_LOCK_STATUS;\ bbeb64d0eb78f4 Harry Wentland 2019-05-07 189 type SURFACE_GSL_ENABLE;\ bbeb64d0eb78f4 Harry Wentland 2019-05-07 190 type SURFACE_TRIPLE_BUFFER_ENABLE;\ 64f223b0dd1200 Yongqiang Sun 2019-04-02 191 type VMID 64f223b0dd1200 Yongqiang Sun 2019-04-02 192 6162ba9234c124 Yifan Zhang 2019-11-28 193 #ifdef CONFIG_DRM_AMD_DC_DCN2_1 35b82ba8f2fa9b Bhawanpreet Lakha 2019-08-28 194 #define DCN21_HUBP_REG_FIELD_VARIABLE_LIST(type) \ 35b82ba8f2fa9b Bhawanpreet Lakha 2019-08-28 195 DCN2_HUBP_REG_FIELD_VARIABLE_LIST(type);\ 35b82ba8f2fa9b Bhawanpreet Lakha 2019-08-28 196 type REFCYC_PER_VM_GROUP_FLIP;\ 35b82ba8f2fa9b Bhawanpreet Lakha 2019-08-28 197 type REFCYC_PER_VM_REQ_FLIP;\ 35b82ba8f2fa9b Bhawanpreet Lakha 2019-08-28 198 type REFCYC_PER_VM_GROUP_VBLANK;\ 35b82ba8f2fa9b Bhawanpreet Lakha 2019-08-28 199 type REFCYC_PER_VM_REQ_VBLANK;\ 35b82ba8f2fa9b Bhawanpreet Lakha 2019-08-28 200 type REFCYC_PER_PTE_GROUP_FLIP_C; \ 35b82ba8f2fa9b Bhawanpreet Lakha 2019-08-28 201 type REFCYC_PER_META_CHUNK_FLIP_C; \ 35b82ba8f2fa9b Bhawanpreet Lakha 2019-08-28 202 type VM_GROUP_SIZE 6162ba9234c124 Yifan Zhang 2019-11-28 203 #endif 35b82ba8f2fa9b Bhawanpreet Lakha 2019-08-28 204 d2898ece6bedb5 Bhawanpreet Lakha 2020-05-21 205 #if defined(CONFIG_DRM_AMD_DC_DCN3_0) d2898ece6bedb5 Bhawanpreet Lakha 2020-05-21 206 #define DCN30_HUBP_REG_FIELD_VARIABLE_LIST(type) \ d2898ece6bedb5 Bhawanpreet Lakha 2020-05-21 @207 DCN21_HUBP_REG_FIELD_VARIABLE_LIST(type);\ d2898ece6bedb5 Bhawanpreet Lakha 2020-05-21 208 type PRIMARY_SURFACE_DCC_IND_BLK;\ d2898ece6bedb5 Bhawanpreet Lakha 2020-05-21 209 type SECONDARY_SURFACE_DCC_IND_BLK;\ d2898ece6bedb5 Bhawanpreet Lakha 2020-05-21 210 type PRIMARY_SURFACE_DCC_IND_BLK_C;\ d2898ece6bedb5 Bhawanpreet Lakha 2020-05-21 211 type SECONDARY_SURFACE_DCC_IND_BLK_C;\ d2898ece6bedb5 Bhawanpreet Lakha 2020-05-21 212 type ALPHA_PLANE_EN;\ d2898ece6bedb5 Bhawanpreet Lakha 2020-05-21 213 type REFCYC_PER_VM_DMDATA;\ d2898ece6bedb5 Bhawanpreet Lakha 2020-05-21 214 type DMDATA_VM_FAULT_STATUS;\ d2898ece6bedb5 Bhawanpreet Lakha 2020-05-21 215 type DMDATA_VM_FAULT_STATUS_CLEAR; \ d2898ece6bedb5 Bhawanpreet Lakha 2020-05-21 216 type DMDATA_VM_UNDERFLOW_STATUS;\ d2898ece6bedb5 Bhawanpreet Lakha 2020-05-21 217 type DMDATA_VM_LATE_STATUS;\ d2898ece6bedb5 Bhawanpreet Lakha 2020-05-21 218 type DMDATA_VM_UNDERFLOW_STATUS_CLEAR; \ d2898ece6bedb5 Bhawanpreet Lakha 2020-05-21 219 type DMDATA_VM_DONE; \ d2898ece6bedb5 Bhawanpreet Lakha 2020-05-21 220 type CROSSBAR_SRC_Y_G; \ d2898ece6bedb5 Bhawanpreet Lakha 2020-05-21 221 type CROSSBAR_SRC_ALPHA; \ d2898ece6bedb5 Bhawanpreet Lakha 2020-05-21 222 type PACK_3TO2_ELEMENT_DISABLE; \ d2898ece6bedb5 Bhawanpreet Lakha 2020-05-21 223 type ROW_TTU_MODE; \ d2898ece6bedb5 Bhawanpreet Lakha 2020-05-21 224 type NUM_PKRS d2898ece6bedb5 Bhawanpreet Lakha 2020-05-21 225 #endif bbeb64d0eb78f4 Harry Wentland 2019-05-07 226 :::::: The code at line 164 was first introduced by commit :::::: d2898ece6bedb5a51e5822369af38c7fda182838 drm/amd/display: Add DCN3 HUBP :::::: TO: Bhawanpreet Lakha :::::: CC: Yang Xiong --- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org --PNTmBPCT7hxwcZjr Content-Type: application/gzip Content-Disposition: attachment; filename=".config.gz" Content-Transfer-Encoding: base64 H4sICDCEuF8AAy5jb25maWcAlDzLcty2svt8xZSzSRZxJEtWnHtLC5AEOcgQBA2AoxltUIo8 TlSxJV89TuK/v90AHwAIjnNSqUSDbjRe/UaD33/3/Yq8PD98vnm+u7359Onr6o/D/eHx5vnw YfXx7tPhf1eFWDVCr2jB9GtAru/uX/75+e7s3cXq7euL1yerzeHx/vBplT/cf7z74wV63j3c f/f9d/Dv99D4+QsQefyf1R+3tz/9uvqhOPx+d3O/+vX12euTn07f/uj+AtxcNCWrTJ4bpkyV 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2MrMsWyRfPMabsojlIgA9gAx9/JZIQD2s5O4u5Ld19g/xG0ExXD+GxkREcSy1Inam4BPceuN jjkOMaJnFUUwJ1Y55tdNtXUhxwDw4d0nTvahjducePIox/vB0N4KDrI5iSvRqbLqyexxkK85 ehjCLmzcc7y3XT22RzUmFoofOUvMJ05R9CmkMO7o6zEE5Bgu4mDAWuQgfUkKQfMtVPm5Bg7T so5hbKiLKvaS5CAIrGYvjv8B6kEQ5uoAAgA= --PNTmBPCT7hxwcZjr Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel --PNTmBPCT7hxwcZjr-- From mboxrd@z Thu Jan 1 00:00:00 1970 Content-Type: multipart/mixed; boundary="===============3421469896192445084==" MIME-Version: 1.0 From: kernel test robot To: kbuild-all@lists.01.org Subject: [radeon-alex:amd-20.45 1379/2417] drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hubp.h:164:2: error: expected specifier-qualifier-list before 'DCN21_HUBP_REG_COMMON_VARIABLE_LIST' Date: Sun, 22 Nov 2020 06:19:54 +0800 Message-ID: <202011220627.iskIRRja-lkp@intel.com> List-Id: --===============3421469896192445084== Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable tree: git://people.freedesktop.org/~agd5f/linux.git amd-20.45 head: 1807abbb3a7f17fc931a15d7fd4365ea148c6bb1 commit: 470f4be73099cc46478d2c708411fecde8197ca3 [1379/2417] drm/amdkcl: up= date DRM_AMD_DC_DCN3_0 to depends on legacy display config config: i386-randconfig-a003-20201120 (attached as .config) compiler: gcc-9 (Debian 9.3.0-15) 9.3.0 reproduce (this is a W=3D1 build): git remote add radeon-alex git://people.freedesktop.org/~agd5f/linu= x.git git fetch --no-tags radeon-alex amd-20.45 git checkout 470f4be73099cc46478d2c708411fecde8197ca3 # save the attached .config to linux build tree make W=3D1 ARCH=3Di386 = If you fix the issue, kindly add following tag as appropriate Reported-by: kernel test robot All error/warnings (new ones prefixed by >>): In file included from drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn= 20_resource.c:42: >> drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hubp.h:164:2: error= : expected specifier-qualifier-list before 'DCN21_HUBP_REG_COMMON_VARIABLE_= LIST' 164 | DCN21_HUBP_REG_COMMON_VARIABLE_LIST;\ | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hubp.h:164:2: note:= in definition of macro 'DCN30_HUBP_REG_COMMON_VARIABLE_LIST' 164 | DCN21_HUBP_REG_COMMON_VARIABLE_LIST;\ | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ >> drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hubp.h:207:2: error= : expected specifier-qualifier-list before 'DCN21_HUBP_REG_FIELD_VARIABLE_L= IST' 207 | DCN21_HUBP_REG_FIELD_VARIABLE_LIST(type);\ | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hubp.h:207:2: note:= in definition of macro 'DCN30_HUBP_REG_FIELD_VARIABLE_LIST' 207 | DCN21_HUBP_REG_FIELD_VARIABLE_LIST(type);\ | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ >> drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hubp.h:207:2: error= : expected specifier-qualifier-list before 'DCN21_HUBP_REG_FIELD_VARIABLE_L= IST' 207 | DCN21_HUBP_REG_FIELD_VARIABLE_LIST(type);\ | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hubp.h:207:2: note:= in definition of macro 'DCN30_HUBP_REG_FIELD_VARIABLE_LIST' 207 | DCN21_HUBP_REG_FIELD_VARIABLE_LIST(type);\ | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ In file included from drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn= 20_resource.c:68: drivers/gpu/drm/amd/include/navi10_ip_offset.h:269:52: warning: initiali= zed field overwritten [-Woverride-init] 269 | #define DCN_BASE__INST0_SEG2 0x000034C0 | ^~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:494:25: = note: in expansion of macro 'DCN_BASE__INST0_SEG2' 494 | #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg | ^~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:496:19: = note: in expansion of macro 'BASE_INNER' 496 | #define BASE(seg) BASE_INNER(seg) | ^~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:503:14: = note: in expansion of macro 'BASE' 503 | .reg_name =3D BASE(mm ## block ## id ## _ ## reg_name ## _BASE_= IDX) + \ | ^~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_link_encoder.h:202:= 2: note: in expansion of macro 'SRI' 202 | SRI(TMDS_CTL_BITS, DIG, id), \ | ^~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_link_encoder.h:235:= 2: note: in expansion of macro 'DPCS_DCN2_CMN_REG_LIST' 235 | DPCS_DCN2_CMN_REG_LIST(id), \ | ^~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:678:2: n= ote: in expansion of macro 'DPCS_DCN2_REG_LIST' 678 | DPCS_DCN2_REG_LIST(id), \ | ^~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:683:2: n= ote: in expansion of macro 'link_regs' 683 | link_regs(0, A), | ^~~~~~~~~ drivers/gpu/drm/amd/include/navi10_ip_offset.h:269:52: note: (near initi= alization for 'link_enc_regs[0].TMDS_CTL_BITS') 269 | #define DCN_BASE__INST0_SEG2 0x000034C0 | ^~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:494:25: = note: in expansion of macro 'DCN_BASE__INST0_SEG2' 494 | #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg | ^~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:496:19: = note: in expansion of macro 'BASE_INNER' 496 | #define BASE(seg) BASE_INNER(seg) | ^~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:503:14: = note: in expansion of macro 'BASE' 503 | .reg_name =3D BASE(mm ## block ## id ## _ ## reg_name ## _BASE_= IDX) + \ | ^~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_link_encoder.h:202:= 2: note: in expansion of macro 'SRI' 202 | SRI(TMDS_CTL_BITS, DIG, id), \ | ^~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_link_encoder.h:235:= 2: note: in expansion of macro 'DPCS_DCN2_CMN_REG_LIST' 235 | DPCS_DCN2_CMN_REG_LIST(id), \ | ^~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:678:2: n= ote: in expansion of macro 'DPCS_DCN2_REG_LIST' 678 | DPCS_DCN2_REG_LIST(id), \ | ^~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:683:2: n= ote: in expansion of macro 'link_regs' 683 | link_regs(0, A), | ^~~~~~~~~ drivers/gpu/drm/amd/include/navi10_ip_offset.h:269:52: warning: initiali= zed field overwritten [-Woverride-init] 269 | #define DCN_BASE__INST0_SEG2 0x000034C0 | ^~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:494:25: = note: in expansion of macro 'DCN_BASE__INST0_SEG2' 494 | #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg | ^~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:496:19: = note: in expansion of macro 'BASE_INNER' 496 | #define BASE(seg) BASE_INNER(seg) | ^~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:503:14: = note: in expansion of macro 'BASE' 503 | .reg_name =3D BASE(mm ## block ## id ## _ ## reg_name ## _BASE_= IDX) + \ | ^~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:679:2: n= ote: in expansion of macro 'SRI' 679 | SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \ | ^~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:683:2: n= ote: in expansion of macro 'link_regs' 683 | link_regs(0, A), | ^~~~~~~~~ drivers/gpu/drm/amd/include/navi10_ip_offset.h:269:52: note: (near initi= alization for 'link_enc_regs[0].DP_DPHY_INTERNAL_CTRL') 269 | #define DCN_BASE__INST0_SEG2 0x000034C0 | ^~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:494:25: = note: in expansion of macro 'DCN_BASE__INST0_SEG2' 494 | #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg | ^~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:496:19: = note: in expansion of macro 'BASE_INNER' 496 | #define BASE(seg) BASE_INNER(seg) | ^~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:503:14: = note: in expansion of macro 'BASE' 503 | .reg_name =3D BASE(mm ## block ## id ## _ ## reg_name ## _BASE_= IDX) + \ | ^~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:679:2: n= ote: in expansion of macro 'SRI' 679 | SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \ | ^~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:683:2: n= ote: in expansion of macro 'link_regs' 683 | link_regs(0, A), | ^~~~~~~~~ drivers/gpu/drm/amd/include/navi10_ip_offset.h:269:52: warning: initiali= zed field overwritten [-Woverride-init] 269 | #define DCN_BASE__INST0_SEG2 0x000034C0 | ^~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:494:25: = note: in expansion of macro 'DCN_BASE__INST0_SEG2' 494 | #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg | ^~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:496:19: = note: in expansion of macro 'BASE_INNER' 496 | #define BASE(seg) BASE_INNER(seg) | ^~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:503:14: = note: in expansion of macro 'BASE' -- | ^~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_optc.h:48:2: note: = in expansion of macro 'TG_COMMON_MASK_SH_LIST_DCN' 48 | TG_COMMON_MASK_SH_LIST_DCN(mask_sh),\ | ^~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:873:2: n= ote: in expansion of macro 'TG_COMMON_MASK_SH_LIST_DCN2_0' 873 | TG_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT) | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_sh_mask.h:31037:111: = note: (near initialization for 'tg_shift.OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_= DP') 31037 | #define OTG0_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_F= OR_DP__SHIFT 0x12 | = ^~~~ drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_sh_mask.h:31037:111: = note: in definition of macro 'OTG0_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSY= NC_OUTPUT_FOR_DP__SHIFT' 31037 | #define OTG0_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_F= OR_DP__SHIFT 0x12 | = ^~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/../dcn10/dcn10_optc.h:224= :2: note: in expansion of macro 'SF' 224 | SF(OTG0_OTG_STEREO_CONTROL, OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_D= P, mask_sh),\ | ^~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_optc.h:48:2: note: = in expansion of macro 'TG_COMMON_MASK_SH_LIST_DCN' 48 | TG_COMMON_MASK_SH_LIST_DCN(mask_sh),\ | ^~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:873:2: n= ote: in expansion of macro 'TG_COMMON_MASK_SH_LIST_DCN2_0' 873 | TG_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT) | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_sh_mask.h:31110:111: = warning: initialized field overwritten [-Woverride-init] 31110 | #define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UP= DATE_MODE__SHIFT 0x18 | = ^~~~ drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_sh_mask.h:31110:111: = note: in definition of macro 'OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIM= ING_DBUF_UPDATE_MODE__SHIFT' 31110 | #define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UP= DATE_MODE__SHIFT 0x18 | = ^~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_optc.h:54:2: note: = in expansion of macro 'SF' 54 | SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_RANGE_TIMING_DBUF_UPDATE= _MODE, mask_sh),\ | ^~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:873:2: n= ote: in expansion of macro 'TG_COMMON_MASK_SH_LIST_DCN2_0' 873 | TG_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT) | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_sh_mask.h:31110:111: = note: (near initialization for 'tg_shift.OTG_RANGE_TIMING_DBUF_UPDATE_MODE') 31110 | #define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UP= DATE_MODE__SHIFT 0x18 | = ^~~~ drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_sh_mask.h:31110:111: = note: in definition of macro 'OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIM= ING_DBUF_UPDATE_MODE__SHIFT' 31110 | #define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UP= DATE_MODE__SHIFT 0x18 | = ^~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_optc.h:54:2: note: = in expansion of macro 'SF' 54 | SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_RANGE_TIMING_DBUF_UPDATE= _MODE, mask_sh),\ | ^~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:873:2: n= ote: in expansion of macro 'TG_COMMON_MASK_SH_LIST_DCN2_0' 873 | TG_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT) | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_sh_mask.h:31044:111: = warning: initialized field overwritten [-Woverride-init] 31044 | #define OTG0_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_F= OR_DP_MASK 0x00040000L | = ^~~~~~~~~~~ drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_sh_mask.h:31044:111: = note: in definition of macro 'OTG0_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSY= NC_OUTPUT_FOR_DP_MASK' 31044 | #define OTG0_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_F= OR_DP_MASK 0x00040000L | = ^~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/../dcn10/dcn10_optc.h:224= :2: note: in expansion of macro 'SF' 224 | SF(OTG0_OTG_STEREO_CONTROL, OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_D= P, mask_sh),\ | ^~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_optc.h:48:2: note: = in expansion of macro 'TG_COMMON_MASK_SH_LIST_DCN' 48 | TG_COMMON_MASK_SH_LIST_DCN(mask_sh),\ | ^~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:877:2: n= ote: in expansion of macro 'TG_COMMON_MASK_SH_LIST_DCN2_0' 877 | TG_COMMON_MASK_SH_LIST_DCN2_0(_MASK) | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_sh_mask.h:31044:111: = note: (near initialization for 'tg_mask.OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_D= P') 31044 | #define OTG0_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_F= OR_DP_MASK 0x00040000L | = ^~~~~~~~~~~ drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_sh_mask.h:31044:111: = note: in definition of macro 'OTG0_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSY= NC_OUTPUT_FOR_DP_MASK' 31044 | #define OTG0_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_F= OR_DP_MASK 0x00040000L | = ^~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/../dcn10/dcn10_optc.h:224= :2: note: in expansion of macro 'SF' 224 | SF(OTG0_OTG_STEREO_CONTROL, OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_D= P, mask_sh),\ | ^~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_optc.h:48:2: note: = in expansion of macro 'TG_COMMON_MASK_SH_LIST_DCN' 48 | TG_COMMON_MASK_SH_LIST_DCN(mask_sh),\ | ^~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:877:2: n= ote: in expansion of macro 'TG_COMMON_MASK_SH_LIST_DCN2_0' 877 | TG_COMMON_MASK_SH_LIST_DCN2_0(_MASK) | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_sh_mask.h:31122:111: = warning: initialized field overwritten [-Woverride-init] 31122 | #define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UP= DATE_MODE_MASK 0x03000000L | = ^~~~~~~~~~~ drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_sh_mask.h:31122:111: = note: in definition of macro 'OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIM= ING_DBUF_UPDATE_MODE_MASK' 31122 | #define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UP= DATE_MODE_MASK 0x03000000L | = ^~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_optc.h:54:2: note: = in expansion of macro 'SF' 54 | SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_RANGE_TIMING_DBUF_UPDATE= _MODE, mask_sh),\ | ^~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:877:2: n= ote: in expansion of macro 'TG_COMMON_MASK_SH_LIST_DCN2_0' 877 | TG_COMMON_MASK_SH_LIST_DCN2_0(_MASK) | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_sh_mask.h:31122:111: = note: (near initialization for 'tg_mask.OTG_RANGE_TIMING_DBUF_UPDATE_MODE') 31122 | #define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UP= DATE_MODE_MASK 0x03000000L | = ^~~~~~~~~~~ drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_sh_mask.h:31122:111: = note: in definition of macro 'OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIM= ING_DBUF_UPDATE_MODE_MASK' 31122 | #define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UP= DATE_MODE_MASK 0x03000000L | = ^~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_optc.h:54:2: note: = in expansion of macro 'SF' 54 | SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_RANGE_TIMING_DBUF_UPDATE= _MODE, mask_sh),\ | ^~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:877:2: n= ote: in expansion of macro 'TG_COMMON_MASK_SH_LIST_DCN2_0' 877 | TG_COMMON_MASK_SH_LIST_DCN2_0(_MASK) | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~ >> drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h:35:6: error: 'const st= ruct dcn_hubp2_registers' has no member named 'DCHUBP_CNTL' 35 | SRI(DCHUBP_CNTL, HUBP, id),\ | ^~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:503:3: n= ote: in definition of macro 'SRI' 503 | .reg_name =3D BASE(mm ## block ## id ## _ ## reg_name ## _BASE_= IDX) + \ | ^~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hubp.h:35:2: note: = in expansion of macro 'HUBP_REG_LIST_DCN' 35 | HUBP_REG_LIST_DCN(id),\ | ^~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hubp.h:65:2: note: = in expansion of macro 'HUBP_REG_LIST_DCN2_COMMON' 65 | HUBP_REG_LIST_DCN2_COMMON(id),\ | ^~~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:882:2: n= ote: in expansion of macro 'HUBP_REG_LIST_DCN20' 882 | HUBP_REG_LIST_DCN20(id)\ | ^~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:886:3: n= ote: in expansion of macro 'hubp_regs' 886 | hubp_regs(0), | ^~~~~~~~~ In file included from drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn= 20_resource.c:68: >> drivers/gpu/drm/amd/include/navi10_ip_offset.h:269:52: warning: excess e= lements in struct initializer 269 | #define DCN_BASE__INST0_SEG2 0x000034C0 | ^~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:494:25: = note: in expansion of macro 'DCN_BASE__INST0_SEG2' 494 | #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg | ^~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:496:19: = note: in expansion of macro 'BASE_INNER' 496 | #define BASE(seg) BASE_INNER(seg) | ^~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:503:14: = note: in expansion of macro 'BASE' 503 | .reg_name =3D BASE(mm ## block ## id ## _ ## reg_name ## _BASE_= IDX) + \ | ^~~~ drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h:35:2: note: in expansi= on of macro 'SRI' 35 | SRI(DCHUBP_CNTL, HUBP, id),\ | ^~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hubp.h:35:2: note: = in expansion of macro 'HUBP_REG_LIST_DCN' 35 | HUBP_REG_LIST_DCN(id),\ | ^~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hubp.h:65:2: note: = in expansion of macro 'HUBP_REG_LIST_DCN2_COMMON' 65 | HUBP_REG_LIST_DCN2_COMMON(id),\ | ^~~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:882:2: n= ote: in expansion of macro 'HUBP_REG_LIST_DCN20' 882 | HUBP_REG_LIST_DCN20(id)\ | ^~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:886:3: n= ote: in expansion of macro 'hubp_regs' 886 | hubp_regs(0), | ^~~~~~~~~ drivers/gpu/drm/amd/include/navi10_ip_offset.h:269:52: note: (near initi= alization for 'hubp_regs[0]') 269 | #define DCN_BASE__INST0_SEG2 0x000034C0 | ^~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:494:25: = note: in expansion of macro 'DCN_BASE__INST0_SEG2' 494 | #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg | ^~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:496:19: = note: in expansion of macro 'BASE_INNER' 496 | #define BASE(seg) BASE_INNER(seg) | ^~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:503:14: = note: in expansion of macro 'BASE' 503 | .reg_name =3D BASE(mm ## block ## id ## _ ## reg_name ## _BASE_= IDX) + \ | ^~~~ drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h:35:2: note: in expansi= on of macro 'SRI' 35 | SRI(DCHUBP_CNTL, HUBP, id),\ | ^~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hubp.h:35:2: note: = in expansion of macro 'HUBP_REG_LIST_DCN' 35 | HUBP_REG_LIST_DCN(id),\ | ^~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hubp.h:65:2: note: = in expansion of macro 'HUBP_REG_LIST_DCN2_COMMON' 65 | HUBP_REG_LIST_DCN2_COMMON(id),\ | ^~~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:882:2: n= ote: in expansion of macro 'HUBP_REG_LIST_DCN20' 882 | HUBP_REG_LIST_DCN20(id)\ | ^~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:886:3: n= ote: in expansion of macro 'hubp_regs' 886 | hubp_regs(0), | ^~~~~~~~~ >> drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h:36:6: error: 'const st= ruct dcn_hubp2_registers' has no member named 'HUBPREQ_DEBUG_DB' 36 | SRI(HUBPREQ_DEBUG_DB, HUBP, id),\ | ^~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:503:3: n= ote: in definition of macro 'SRI' 503 | .reg_name =3D BASE(mm ## block ## id ## _ ## reg_name ## _BASE_= IDX) + \ | ^~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hubp.h:35:2: note: = in expansion of macro 'HUBP_REG_LIST_DCN' 35 | HUBP_REG_LIST_DCN(id),\ | ^~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hubp.h:65:2: note: = in expansion of macro 'HUBP_REG_LIST_DCN2_COMMON' 65 | HUBP_REG_LIST_DCN2_COMMON(id),\ | ^~~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:882:2: n= ote: in expansion of macro 'HUBP_REG_LIST_DCN20' 882 | HUBP_REG_LIST_DCN20(id)\ | ^~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:886:3: n= ote: in expansion of macro 'hubp_regs' 886 | hubp_regs(0), | ^~~~~~~~~ In file included from drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn= 20_resource.c:68: >> drivers/gpu/drm/amd/include/navi10_ip_offset.h:269:52: warning: excess e= lements in struct initializer 269 | #define DCN_BASE__INST0_SEG2 0x000034C0 | ^~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:494:25: = note: in expansion of macro 'DCN_BASE__INST0_SEG2' 494 | #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg | ^~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:496:19: = note: in expansion of macro 'BASE_INNER' 496 | #define BASE(seg) BASE_INNER(seg) | ^~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:503:14: = note: in expansion of macro 'BASE' 503 | .reg_name =3D BASE(mm ## block ## id ## _ ## reg_name ## _BASE_= IDX) + \ | ^~~~ drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h:36:2: note: in expansi= on of macro 'SRI' 36 | SRI(HUBPREQ_DEBUG_DB, HUBP, id),\ | ^~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hubp.h:35:2: note: = in expansion of macro 'HUBP_REG_LIST_DCN' 35 | HUBP_REG_LIST_DCN(id),\ | ^~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hubp.h:65:2: note: = in expansion of macro 'HUBP_REG_LIST_DCN2_COMMON' 65 | HUBP_REG_LIST_DCN2_COMMON(id),\ | ^~~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:882:2: n= ote: in expansion of macro 'HUBP_REG_LIST_DCN20' 882 | HUBP_REG_LIST_DCN20(id)\ | ^~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:886:3: n= ote: in expansion of macro 'hubp_regs' 886 | hubp_regs(0), | ^~~~~~~~~ drivers/gpu/drm/amd/include/navi10_ip_offset.h:269:52: note: (near initi= alization for 'hubp_regs[0]') 269 | #define DCN_BASE__INST0_SEG2 0x000034C0 | ^~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:494:25: = note: in expansion of macro 'DCN_BASE__INST0_SEG2' 494 | #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg | ^~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:496:19: = note: in expansion of macro 'BASE_INNER' 496 | #define BASE(seg) BASE_INNER(seg) | ^~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:503:14: = note: in expansion of macro 'BASE' 503 | .reg_name =3D BASE(mm ## block ## id ## _ ## reg_name ## _BASE_= IDX) + \ | ^~~~ drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h:36:2: note: in expansi= on of macro 'SRI' 36 | SRI(HUBPREQ_DEBUG_DB, HUBP, id),\ | ^~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hubp.h:35:2: note: = in expansion of macro 'HUBP_REG_LIST_DCN' 35 | HUBP_REG_LIST_DCN(id),\ | ^~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hubp.h:65:2: note: = in expansion of macro 'HUBP_REG_LIST_DCN2_COMMON' 65 | HUBP_REG_LIST_DCN2_COMMON(id),\ | ^~~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:882:2: n= ote: in expansion of macro 'HUBP_REG_LIST_DCN20' 882 | HUBP_REG_LIST_DCN20(id)\ | ^~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:886:3: n= ote: in expansion of macro 'hubp_regs' 886 | hubp_regs(0), | ^~~~~~~~~ >> drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h:37:6: error: 'const st= ruct dcn_hubp2_registers' has no member named 'HUBPREQ_DEBUG' 37 | SRI(HUBPREQ_DEBUG, HUBP, id),\ | ^~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:503:3: n= ote: in definition of macro 'SRI' 503 | .reg_name =3D BASE(mm ## block ## id ## _ ## reg_name ## _BASE_= IDX) + \ | ^~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hubp.h:35:2: note: = in expansion of macro 'HUBP_REG_LIST_DCN' 35 | HUBP_REG_LIST_DCN(id),\ | ^~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hubp.h:65:2: note: = in expansion of macro 'HUBP_REG_LIST_DCN2_COMMON' 65 | HUBP_REG_LIST_DCN2_COMMON(id),\ | ^~~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:882:2: n= ote: in expansion of macro 'HUBP_REG_LIST_DCN20' 882 | HUBP_REG_LIST_DCN20(id)\ | ^~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:886:3: n= ote: in expansion of macro 'hubp_regs' 886 | hubp_regs(0), | ^~~~~~~~~ In file included from drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn= 20_resource.c:68: >> drivers/gpu/drm/amd/include/navi10_ip_offset.h:269:52: warning: excess e= lements in struct initializer 269 | #define DCN_BASE__INST0_SEG2 0x000034C0 | ^~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:494:25: = note: in expansion of macro 'DCN_BASE__INST0_SEG2' 494 | #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg | ^~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:496:19: = note: in expansion of macro 'BASE_INNER' 496 | #define BASE(seg) BASE_INNER(seg) | ^~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:503:14: = note: in expansion of macro 'BASE' 503 | .reg_name =3D BASE(mm ## block ## id ## _ ## reg_name ## _BASE_= IDX) + \ | ^~~~ drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h:37:2: note: in expansi= on of macro 'SRI' 37 | SRI(HUBPREQ_DEBUG, HUBP, id),\ | ^~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hubp.h:35:2: note: = in expansion of macro 'HUBP_REG_LIST_DCN' 35 | HUBP_REG_LIST_DCN(id),\ | ^~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hubp.h:65:2: note: = in expansion of macro 'HUBP_REG_LIST_DCN2_COMMON' 65 | HUBP_REG_LIST_DCN2_COMMON(id),\ | ^~~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:882:2: n= ote: in expansion of macro 'HUBP_REG_LIST_DCN20' 882 | HUBP_REG_LIST_DCN20(id)\ | ^~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:886:3: n= ote: in expansion of macro 'hubp_regs' 886 | hubp_regs(0), | ^~~~~~~~~ drivers/gpu/drm/amd/include/navi10_ip_offset.h:269:52: note: (near initi= alization for 'hubp_regs[0]') 269 | #define DCN_BASE__INST0_SEG2 0x000034C0 | ^~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:494:25: = note: in expansion of macro 'DCN_BASE__INST0_SEG2' 494 | #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg | ^~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:496:19: = note: in expansion of macro 'BASE_INNER' 496 | #define BASE(seg) BASE_INNER(seg) | ^~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:503:14: = note: in expansion of macro 'BASE' 503 | .reg_name =3D BASE(mm ## block ## id ## _ ## reg_name ## _BASE_= IDX) + \ | ^~~~ drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h:37:2: note: in expansi= on of macro 'SRI' 37 | SRI(HUBPREQ_DEBUG, HUBP, id),\ | ^~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hubp.h:35:2: note: = in expansion of macro 'HUBP_REG_LIST_DCN' 35 | HUBP_REG_LIST_DCN(id),\ | ^~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hubp.h:65:2: note: = in expansion of macro 'HUBP_REG_LIST_DCN2_COMMON' 65 | HUBP_REG_LIST_DCN2_COMMON(id),\ | ^~~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:882:2: n= ote: in expansion of macro 'HUBP_REG_LIST_DCN20' 882 | HUBP_REG_LIST_DCN20(id)\ | ^~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:886:3: n= ote: in expansion of macro 'hubp_regs' 886 | hubp_regs(0), | ^~~~~~~~~ >> drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h:38:6: error: 'const st= ruct dcn_hubp2_registers' has no member named 'DCSURF_ADDR_CONFIG' 38 | SRI(DCSURF_ADDR_CONFIG, HUBP, id),\ | ^~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:503:3: n= ote: in definition of macro 'SRI' 503 | .reg_name =3D BASE(mm ## block ## id ## _ ## reg_name ## _BASE_= IDX) + \ | ^~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hubp.h:35:2: note: = in expansion of macro 'HUBP_REG_LIST_DCN' 35 | HUBP_REG_LIST_DCN(id),\ | ^~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hubp.h:65:2: note: = in expansion of macro 'HUBP_REG_LIST_DCN2_COMMON' 65 | HUBP_REG_LIST_DCN2_COMMON(id),\ | ^~~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:882:2: n= ote: in expansion of macro 'HUBP_REG_LIST_DCN20' 882 | HUBP_REG_LIST_DCN20(id)\ | ^~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:886:3: n= ote: in expansion of macro 'hubp_regs' 886 | hubp_regs(0), | ^~~~~~~~~ In file included from drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn= 20_resource.c:68: >> drivers/gpu/drm/amd/include/navi10_ip_offset.h:269:52: warning: excess e= lements in struct initializer 269 | #define DCN_BASE__INST0_SEG2 0x000034C0 | ^~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:494:25: = note: in expansion of macro 'DCN_BASE__INST0_SEG2' 494 | #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg | ^~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:496:19: = note: in expansion of macro 'BASE_INNER' 496 | #define BASE(seg) BASE_INNER(seg) | ^~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:503:14: = note: in expansion of macro 'BASE' 503 | .reg_name =3D BASE(mm ## block ## id ## _ ## reg_name ## _BASE_= IDX) + \ | ^~~~ drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h:38:2: note: in expansi= on of macro 'SRI' 38 | SRI(DCSURF_ADDR_CONFIG, HUBP, id),\ | ^~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hubp.h:35:2: note: = in expansion of macro 'HUBP_REG_LIST_DCN' 35 | HUBP_REG_LIST_DCN(id),\ | ^~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hubp.h:65:2: note: = in expansion of macro 'HUBP_REG_LIST_DCN2_COMMON' 65 | HUBP_REG_LIST_DCN2_COMMON(id),\ | ^~~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:882:2: n= ote: in expansion of macro 'HUBP_REG_LIST_DCN20' 882 | HUBP_REG_LIST_DCN20(id)\ | ^~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:886:3: n= ote: in expansion of macro 'hubp_regs' 886 | hubp_regs(0), | ^~~~~~~~~ drivers/gpu/drm/amd/include/navi10_ip_offset.h:269:52: note: (near initi= alization for 'hubp_regs[0]') 269 | #define DCN_BASE__INST0_SEG2 0x000034C0 | ^~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:494:25: = note: in expansion of macro 'DCN_BASE__INST0_SEG2' 494 | #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg | ^~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:496:19: = note: in expansion of macro 'BASE_INNER' 496 | #define BASE(seg) BASE_INNER(seg) | ^~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:503:14: = note: in expansion of macro 'BASE' 503 | .reg_name =3D BASE(mm ## block ## id ## _ ## reg_name ## _BASE_= IDX) + \ | ^~~~ drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h:38:2: note: in expansi= on of macro 'SRI' 38 | SRI(DCSURF_ADDR_CONFIG, HUBP, id),\ | ^~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hubp.h:35:2: note: = in expansion of macro 'HUBP_REG_LIST_DCN' 35 | HUBP_REG_LIST_DCN(id),\ | ^~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hubp.h:65:2: note: = in expansion of macro 'HUBP_REG_LIST_DCN2_COMMON' 65 | HUBP_REG_LIST_DCN2_COMMON(id),\ | ^~~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:882:2: n= ote: in expansion of macro 'HUBP_REG_LIST_DCN20' 882 | HUBP_REG_LIST_DCN20(id)\ | ^~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:886:3: n= ote: in expansion of macro 'hubp_regs' 886 | hubp_regs(0), | ^~~~~~~~~ >> drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h:39:6: error: 'const st= ruct dcn_hubp2_registers' has no member named 'DCSURF_TILING_CONFIG' 39 | SRI(DCSURF_TILING_CONFIG, HUBP, id),\ | ^~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:503:3: n= ote: in definition of macro 'SRI' 503 | .reg_name =3D BASE(mm ## block ## id ## _ ## reg_name ## _BASE_= IDX) + \ | ^~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hubp.h:35:2: note: = in expansion of macro 'HUBP_REG_LIST_DCN' 35 | HUBP_REG_LIST_DCN(id),\ | ^~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hubp.h:65:2: note: = in expansion of macro 'HUBP_REG_LIST_DCN2_COMMON' 65 | HUBP_REG_LIST_DCN2_COMMON(id),\ | ^~~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:882:2: n= ote: in expansion of macro 'HUBP_REG_LIST_DCN20' 882 | HUBP_REG_LIST_DCN20(id)\ | ^~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:886:3: n= ote: in expansion of macro 'hubp_regs' 886 | hubp_regs(0), | ^~~~~~~~~ In file included from drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn= 20_resource.c:68: >> drivers/gpu/drm/amd/include/navi10_ip_offset.h:269:52: warning: excess e= lements in struct initializer 269 | #define DCN_BASE__INST0_SEG2 0x000034C0 | ^~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:494:25: = note: in expansion of macro 'DCN_BASE__INST0_SEG2' 494 | #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg | ^~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:496:19: = note: in expansion of macro 'BASE_INNER' 496 | #define BASE(seg) BASE_INNER(seg) | ^~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:503:14: = note: in expansion of macro 'BASE' 503 | .reg_name =3D BASE(mm ## block ## id ## _ ## reg_name ## _BASE_= IDX) + \ | ^~~~ drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h:39:2: note: in expansi= on of macro 'SRI' 39 | SRI(DCSURF_TILING_CONFIG, HUBP, id),\ | ^~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hubp.h:35:2: note: = in expansion of macro 'HUBP_REG_LIST_DCN' 35 | HUBP_REG_LIST_DCN(id),\ | ^~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hubp.h:65:2: note: = in expansion of macro 'HUBP_REG_LIST_DCN2_COMMON' 65 | HUBP_REG_LIST_DCN2_COMMON(id),\ | ^~~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:882:2: n= ote: in expansion of macro 'HUBP_REG_LIST_DCN20' 882 | HUBP_REG_LIST_DCN20(id)\ | ^~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:886:3: n= ote: in expansion of macro 'hubp_regs' 886 | hubp_regs(0), | ^~~~~~~~~ drivers/gpu/drm/amd/include/navi10_ip_offset.h:269:52: note: (near initi= alization for 'hubp_regs[0]') 269 | #define DCN_BASE__INST0_SEG2 0x000034C0 | ^~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:494:25: = note: in expansion of macro 'DCN_BASE__INST0_SEG2' 494 | #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg | ^~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:496:19: = note: in expansion of macro 'BASE_INNER' 496 | #define BASE(seg) BASE_INNER(seg) | ^~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:503:14: = note: in expansion of macro 'BASE' 503 | .reg_name =3D BASE(mm ## block ## id ## _ ## reg_name ## _BASE_= IDX) + \ | ^~~~ drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h:39:2: note: in expansi= on of macro 'SRI' 39 | SRI(DCSURF_TILING_CONFIG, HUBP, id),\ | ^~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hubp.h:35:2: note: = in expansion of macro 'HUBP_REG_LIST_DCN' 35 | HUBP_REG_LIST_DCN(id),\ | ^~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hubp.h:65:2: note: = in expansion of macro 'HUBP_REG_LIST_DCN2_COMMON' 65 | HUBP_REG_LIST_DCN2_COMMON(id),\ | ^~~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:882:2: n= ote: in expansion of macro 'HUBP_REG_LIST_DCN20' 882 | HUBP_REG_LIST_DCN20(id)\ | ^~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:886:3: n= ote: in expansion of macro 'hubp_regs' 886 | hubp_regs(0), | ^~~~~~~~~ >> drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h:40:6: error: 'const st= ruct dcn_hubp2_registers' has no member named 'DCSURF_SURFACE_PITCH' 40 | SRI(DCSURF_SURFACE_PITCH, HUBPREQ, id),\ | ^~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:503:3: n= ote: in definition of macro 'SRI' 503 | .reg_name =3D BASE(mm ## block ## id ## _ ## reg_name ## _BASE_= IDX) + \ | ^~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hubp.h:35:2: note: = in expansion of macro 'HUBP_REG_LIST_DCN' 35 | HUBP_REG_LIST_DCN(id),\ | ^~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hubp.h:65:2: note: = in expansion of macro 'HUBP_REG_LIST_DCN2_COMMON' 65 | HUBP_REG_LIST_DCN2_COMMON(id),\ | ^~~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:882:2: n= ote: in expansion of macro 'HUBP_REG_LIST_DCN20' 882 | HUBP_REG_LIST_DCN20(id)\ | ^~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:886:3: n= ote: in expansion of macro 'hubp_regs' 886 | hubp_regs(0), | ^~~~~~~~~ In file included from drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn= 20_resource.c:68: >> drivers/gpu/drm/amd/include/navi10_ip_offset.h:269:52: warning: excess e= lements in struct initializer 269 | #define DCN_BASE__INST0_SEG2 0x000034C0 | ^~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:494:25: = note: in expansion of macro 'DCN_BASE__INST0_SEG2' 494 | #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg | ^~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:496:19: = note: in expansion of macro 'BASE_INNER' 496 | #define BASE(seg) BASE_INNER(seg) | ^~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:503:14: = note: in expansion of macro 'BASE' 503 | .reg_name =3D BASE(mm ## block ## id ## _ ## reg_name ## _BASE_= IDX) + \ | ^~~~ drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h:40:2: note: in expansi= on of macro 'SRI' 40 | SRI(DCSURF_SURFACE_PITCH, HUBPREQ, id),\ | ^~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hubp.h:35:2: note: = in expansion of macro 'HUBP_REG_LIST_DCN' 35 | HUBP_REG_LIST_DCN(id),\ | ^~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hubp.h:65:2: note: = in expansion of macro 'HUBP_REG_LIST_DCN2_COMMON' 65 | HUBP_REG_LIST_DCN2_COMMON(id),\ | ^~~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:882:2: n= ote: in expansion of macro 'HUBP_REG_LIST_DCN20' 882 | HUBP_REG_LIST_DCN20(id)\ | ^~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:886:3: n= ote: in expansion of macro 'hubp_regs' 886 | hubp_regs(0), | ^~~~~~~~~ drivers/gpu/drm/amd/include/navi10_ip_offset.h:269:52: note: (near initi= alization for 'hubp_regs[0]') 269 | #define DCN_BASE__INST0_SEG2 0x000034C0 | ^~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:494:25: = note: in expansion of macro 'DCN_BASE__INST0_SEG2' 494 | #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg | ^~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:496:19: = note: in expansion of macro 'BASE_INNER' 496 | #define BASE(seg) BASE_INNER(seg) | ^~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:503:14: = note: in expansion of macro 'BASE' 503 | .reg_name =3D BASE(mm ## block ## id ## _ ## reg_name ## _BASE_= IDX) + \ | ^~~~ drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h:40:2: note: in expansi= on of macro 'SRI' 40 | SRI(DCSURF_SURFACE_PITCH, HUBPREQ, id),\ | ^~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hubp.h:35:2: note: = in expansion of macro 'HUBP_REG_LIST_DCN' 35 | HUBP_REG_LIST_DCN(id),\ | ^~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hubp.h:65:2: note: = in expansion of macro 'HUBP_REG_LIST_DCN2_COMMON' 65 | HUBP_REG_LIST_DCN2_COMMON(id),\ | ^~~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:882:2: n= ote: in expansion of macro 'HUBP_REG_LIST_DCN20' 882 | HUBP_REG_LIST_DCN20(id)\ | ^~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:886:3: n= ote: in expansion of macro 'hubp_regs' 886 | hubp_regs(0), | ^~~~~~~~~ >> drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h:41:6: error: 'const st= ruct dcn_hubp2_registers' has no member named 'DCSURF_SURFACE_PITCH_C' 41 | SRI(DCSURF_SURFACE_PITCH_C, HUBPREQ, id),\ | ^~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:503:3: n= ote: in definition of macro 'SRI' 503 | .reg_name =3D BASE(mm ## block ## id ## _ ## reg_name ## _BASE_= IDX) + \ | ^~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hubp.h:35:2: note: = in expansion of macro 'HUBP_REG_LIST_DCN' 35 | HUBP_REG_LIST_DCN(id),\ | ^~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hubp.h:65:2: note: = in expansion of macro 'HUBP_REG_LIST_DCN2_COMMON' 65 | HUBP_REG_LIST_DCN2_COMMON(id),\ | ^~~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:882:2: n= ote: in expansion of macro 'HUBP_REG_LIST_DCN20' 882 | HUBP_REG_LIST_DCN20(id)\ | ^~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:886:3: n= ote: in expansion of macro 'hubp_regs' 886 | hubp_regs(0), | ^~~~~~~~~ In file included from drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn= 20_resource.c:68: >> drivers/gpu/drm/amd/include/navi10_ip_offset.h:269:52: warning: excess e= lements in struct initializer 269 | #define DCN_BASE__INST0_SEG2 0x000034C0 | ^~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:494:25: = note: in expansion of macro 'DCN_BASE__INST0_SEG2' 494 | #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg | ^~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:496:19: = note: in expansion of macro 'BASE_INNER' 496 | #define BASE(seg) BASE_INNER(seg) | ^~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:503:14: = note: in expansion of macro 'BASE' 503 | .reg_name =3D BASE(mm ## block ## id ## _ ## reg_name ## _BASE_= IDX) + \ | ^~~~ drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h:41:2: note: in expansi= on of macro 'SRI' 41 | SRI(DCSURF_SURFACE_PITCH_C, HUBPREQ, id),\ | ^~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hubp.h:35:2: note: = in expansion of macro 'HUBP_REG_LIST_DCN' 35 | HUBP_REG_LIST_DCN(id),\ | ^~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hubp.h:65:2: note: = in expansion of macro 'HUBP_REG_LIST_DCN2_COMMON' 65 | HUBP_REG_LIST_DCN2_COMMON(id),\ | ^~~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:882:2: n= ote: in expansion of macro 'HUBP_REG_LIST_DCN20' 882 | HUBP_REG_LIST_DCN20(id)\ | ^~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:886:3: n= ote: in expansion of macro 'hubp_regs' 886 | hubp_regs(0), | ^~~~~~~~~ drivers/gpu/drm/amd/include/navi10_ip_offset.h:269:52: note: (near initi= alization for 'hubp_regs[0]') 269 | #define DCN_BASE__INST0_SEG2 0x000034C0 | ^~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:494:25: = note: in expansion of macro 'DCN_BASE__INST0_SEG2' 494 | #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg | ^~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:496:19: = note: in expansion of macro 'BASE_INNER' 496 | #define BASE(seg) BASE_INNER(seg) | ^~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:503:14: = note: in expansion of macro 'BASE' 503 | .reg_name =3D BASE(mm ## block ## id ## _ ## reg_name ## _BASE_= IDX) + \ | ^~~~ drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h:41:2: note: in expansi= on of macro 'SRI' 41 | SRI(DCSURF_SURFACE_PITCH_C, HUBPREQ, id),\ | ^~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hubp.h:35:2: note: = in expansion of macro 'HUBP_REG_LIST_DCN' 35 | HUBP_REG_LIST_DCN(id),\ | ^~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hubp.h:65:2: note: = in expansion of macro 'HUBP_REG_LIST_DCN2_COMMON' 65 | HUBP_REG_LIST_DCN2_COMMON(id),\ | ^~~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:882:2: n= ote: in expansion of macro 'HUBP_REG_LIST_DCN20' 882 | HUBP_REG_LIST_DCN20(id)\ | ^~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:886:3: n= ote: in expansion of macro 'hubp_regs' 886 | hubp_regs(0), | ^~~~~~~~~ >> drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h:42:6: error: 'const st= ruct dcn_hubp2_registers' has no member named 'DCSURF_SURFACE_CONFIG' 42 | SRI(DCSURF_SURFACE_CONFIG, HUBP, id),\ | ^~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:503:3: n= ote: in definition of macro 'SRI' 503 | .reg_name =3D BASE(mm ## block ## id ## _ ## reg_name ## _BASE_= IDX) + \ | ^~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hubp.h:35:2: note: = in expansion of macro 'HUBP_REG_LIST_DCN' 35 | HUBP_REG_LIST_DCN(id),\ | ^~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hubp.h:65:2: note: = in expansion of macro 'HUBP_REG_LIST_DCN2_COMMON' 65 | HUBP_REG_LIST_DCN2_COMMON(id),\ | ^~~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:882:2: n= ote: in expansion of macro 'HUBP_REG_LIST_DCN20' 882 | HUBP_REG_LIST_DCN20(id)\ | ^~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:886:3: n= ote: in expansion of macro 'hubp_regs' 886 | hubp_regs(0), | ^~~~~~~~~ In file included from drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn= 20_resource.c:68: >> drivers/gpu/drm/amd/include/navi10_ip_offset.h:269:52: warning: excess e= lements in struct initializer 269 | #define DCN_BASE__INST0_SEG2 0x000034C0 | ^~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:494:25: = note: in expansion of macro 'DCN_BASE__INST0_SEG2' 494 | #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg | ^~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:496:19: = note: in expansion of macro 'BASE_INNER' 496 | #define BASE(seg) BASE_INNER(seg) | ^~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:503:14: = note: in expansion of macro 'BASE' 503 | .reg_name =3D BASE(mm ## block ## id ## _ ## reg_name ## _BASE_= IDX) + \ | ^~~~ drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h:42:2: note: in expansi= on of macro 'SRI' 42 | SRI(DCSURF_SURFACE_CONFIG, HUBP, id),\ | ^~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hubp.h:35:2: note: = in expansion of macro 'HUBP_REG_LIST_DCN' 35 | HUBP_REG_LIST_DCN(id),\ | ^~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hubp.h:65:2: note: = in expansion of macro 'HUBP_REG_LIST_DCN2_COMMON' 65 | HUBP_REG_LIST_DCN2_COMMON(id),\ | ^~~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:882:2: n= ote: in expansion of macro 'HUBP_REG_LIST_DCN20' 882 | HUBP_REG_LIST_DCN20(id)\ | ^~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:886:3: n= ote: in expansion of macro 'hubp_regs' 886 | hubp_regs(0), | ^~~~~~~~~ drivers/gpu/drm/amd/include/navi10_ip_offset.h:269:52: note: (near initi= alization for 'hubp_regs[0]') 269 | #define DCN_BASE__INST0_SEG2 0x000034C0 | ^~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:494:25: = note: in expansion of macro 'DCN_BASE__INST0_SEG2' 494 | #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg | ^~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:496:19: = note: in expansion of macro 'BASE_INNER' 496 | #define BASE(seg) BASE_INNER(seg) | ^~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:503:14: = note: in expansion of macro 'BASE' 503 | .reg_name =3D BASE(mm ## block ## id ## _ ## reg_name ## _BASE_= IDX) + \ | ^~~~ drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h:42:2: note: in expansi= on of macro 'SRI' 42 | SRI(DCSURF_SURFACE_CONFIG, HUBP, id),\ | ^~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hubp.h:35:2: note: = in expansion of macro 'HUBP_REG_LIST_DCN' 35 | HUBP_REG_LIST_DCN(id),\ | ^~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hubp.h:65:2: note: = in expansion of macro 'HUBP_REG_LIST_DCN2_COMMON' 65 | HUBP_REG_LIST_DCN2_COMMON(id),\ | ^~~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:882:2: n= ote: in expansion of macro 'HUBP_REG_LIST_DCN20' 882 | HUBP_REG_LIST_DCN20(id)\ | ^~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:886:3: n= ote: in expansion of macro 'hubp_regs' 886 | hubp_regs(0), | ^~~~~~~~~ >> drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h:43:6: error: 'const st= ruct dcn_hubp2_registers' has no member named 'DCSURF_FLIP_CONTROL' 43 | SRI(DCSURF_FLIP_CONTROL, HUBPREQ, id),\ | ^~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:503:3: n= ote: in definition of macro 'SRI' 503 | .reg_name =3D BASE(mm ## block ## id ## _ ## reg_name ## _BASE_= IDX) + \ | ^~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hubp.h:35:2: note: = in expansion of macro 'HUBP_REG_LIST_DCN' 35 | HUBP_REG_LIST_DCN(id),\ | ^~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hubp.h:65:2: note: = in expansion of macro 'HUBP_REG_LIST_DCN2_COMMON' 65 | HUBP_REG_LIST_DCN2_COMMON(id),\ | ^~~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:882:2: n= ote: in expansion of macro 'HUBP_REG_LIST_DCN20' 882 | HUBP_REG_LIST_DCN20(id)\ | ^~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:886:3: n= ote: in expansion of macro 'hubp_regs' 886 | hubp_regs(0), | ^~~~~~~~~ In file included from drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn= 20_resource.c:68: drivers/gpu/drm/amd/include/navi10_ip_offset.h:269:52: warning: excess e= lements in struct initializer 269 | #define DCN_BASE__INST0_SEG2 0x000034C0 | ^~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:494:25: = note: in expansion of macro 'DCN_BASE__INST0_SEG2' 494 | #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg | ^~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:496:19: = note: in expansion of macro 'BASE_INNER' 496 | #define BASE(seg) BASE_INNER(seg) | ^~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:503:14: = note: in expansion of macro 'BASE' 503 | .reg_name =3D BASE(mm ## block ## id ## _ ## reg_name ## _BASE_= IDX) + \ | ^~~~ drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h:43:2: note: in expansi= on of macro 'SRI' 43 | SRI(DCSURF_FLIP_CONTROL, HUBPREQ, id),\ | ^~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hubp.h:35:2: note: = in expansion of macro 'HUBP_REG_LIST_DCN' 35 | HUBP_REG_LIST_DCN(id),\ | ^~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hubp.h:65:2: note: = in expansion of macro 'HUBP_REG_LIST_DCN2_COMMON' 65 | HUBP_REG_LIST_DCN2_COMMON(id),\ | ^~~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:882:2: n= ote: in expansion of macro 'HUBP_REG_LIST_DCN20' 882 | HUBP_REG_LIST_DCN20(id)\ | ^~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:886:3: n= ote: in expansion of macro 'hubp_regs' 886 | hubp_regs(0), | ^~~~~~~~~ drivers/gpu/drm/amd/include/navi10_ip_offset.h:269:52: note: (near initi= alization for 'hubp_regs[0]') 269 | #define DCN_BASE__INST0_SEG2 0x000034C0 | ^~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:494:25: = note: in expansion of macro 'DCN_BASE__INST0_SEG2' 494 | #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg | ^~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:496:19: = note: in expansion of macro 'BASE_INNER' 496 | #define BASE(seg) BASE_INNER(seg) | ^~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:503:14: = note: in expansion of macro 'BASE' 503 | .reg_name =3D BASE(mm ## block ## id ## _ ## reg_name ## _BASE_= IDX) + \ | ^~~~ drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h:43:2: note: in expansi= on of macro 'SRI' 43 | SRI(DCSURF_FLIP_CONTROL, HUBPREQ, id),\ | ^~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hubp.h:35:2: note: = in expansion of macro 'HUBP_REG_LIST_DCN' 35 | HUBP_REG_LIST_DCN(id),\ | ^~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hubp.h:65:2: note: = in expansion of macro 'HUBP_REG_LIST_DCN2_COMMON' 65 | HUBP_REG_LIST_DCN2_COMMON(id),\ | ^~~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:882:2: n= ote: in expansion of macro 'HUBP_REG_LIST_DCN20' 882 | HUBP_REG_LIST_DCN20(id)\ | ^~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:886:3: n= ote: in expansion of macro 'hubp_regs' 886 | hubp_regs(0), | ^~~~~~~~~ drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h:44:6: error: 'const st= ruct dcn_hubp2_registers' has no member named 'DCSURF_PRI_VIEWPORT_DIMENSIO= N' 44 | SRI(DCSURF_PRI_VIEWPORT_DIMENSION, HUBP, id), \ | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:503:3: n= ote: in definition of macro 'SRI' 503 | .reg_name =3D BASE(mm ## block ## id ## _ ## reg_name ## _BASE_= IDX) + \ | ^~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hubp.h:35:2: note: = in expansion of macro 'HUBP_REG_LIST_DCN' 35 | HUBP_REG_LIST_DCN(id),\ | ^~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hubp.h:65:2: note: = in expansion of macro 'HUBP_REG_LIST_DCN2_COMMON' 65 | HUBP_REG_LIST_DCN2_COMMON(id),\ | ^~~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:882:2: n= ote: in expansion of macro 'HUBP_REG_LIST_DCN20' 882 | HUBP_REG_LIST_DCN20(id)\ | ^~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:886:3: n= ote: in expansion of macro 'hubp_regs' 886 | hubp_regs(0), | ^~~~~~~~~ In file included from drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn= 20_resource.c:68: drivers/gpu/drm/amd/include/navi10_ip_offset.h:269:52: warning: excess e= lements in struct initializer 269 | #define DCN_BASE__INST0_SEG2 0x000034C0 | ^~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:494:25: = note: in expansion of macro 'DCN_BASE__INST0_SEG2' 494 | #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg | ^~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:496:19: = note: in expansion of macro 'BASE_INNER' 496 | #define BASE(seg) BASE_INNER(seg) | ^~~~~~~~~~ .. vim +/DCN21_HUBP_REG_COMMON_VARIABLE_LIST +164 drivers/gpu/drm/amd/amdgpu/.= ./display/dc/dcn20/dcn20_hubp.h bbeb64d0eb78f4 Harry Wentland 2019-05-07 30 = bbeb64d0eb78f4 Harry Wentland 2019-05-07 31 #define TO_DCN20_HUBP(hub= p)\ bbeb64d0eb78f4 Harry Wentland 2019-05-07 32 container_of(hubp, struc= t dcn20_hubp, base) bbeb64d0eb78f4 Harry Wentland 2019-05-07 33 = 0213541d4b6b24 Yongqiang Sun 2019-03-28 34 #define HUBP_REG_LIST_DCN= 2_COMMON(id)\ bbeb64d0eb78f4 Harry Wentland 2019-05-07 35 HUBP_REG_LIST_DCN(id),\ bbeb64d0eb78f4 Harry Wentland 2019-05-07 36 HUBP_REG_LIST_DCN_VM(id)= ,\ bbeb64d0eb78f4 Harry Wentland 2019-05-07 @37 SRI(PREFETCH_SETTINGS, H= UBPREQ, id),\ bbeb64d0eb78f4 Harry Wentland 2019-05-07 @38 SRI(PREFETCH_SETTINGS_C,= HUBPREQ, id),\ bbeb64d0eb78f4 Harry Wentland 2019-05-07 @39 SRI(DCN_VM_SYSTEM_APERTU= RE_LOW_ADDR, HUBPREQ, id),\ bbeb64d0eb78f4 Harry Wentland 2019-05-07 @40 SRI(DCN_VM_SYSTEM_APERTU= RE_HIGH_ADDR, HUBPREQ, id),\ bbeb64d0eb78f4 Harry Wentland 2019-05-07 @41 SRI(CURSOR_SETTINGS, HUB= PREQ, id), \ bbeb64d0eb78f4 Harry Wentland 2019-05-07 @42 SRI(CURSOR_SURFACE_ADDRE= SS_HIGH, CURSOR0_, id), \ bbeb64d0eb78f4 Harry Wentland 2019-05-07 @43 SRI(CURSOR_SURFACE_ADDRE= SS, CURSOR0_, id), \ bbeb64d0eb78f4 Harry Wentland 2019-05-07 @44 SRI(CURSOR_SIZE, CURSOR0= _, id), \ bbeb64d0eb78f4 Harry Wentland 2019-05-07 @45 SRI(CURSOR_CONTROL, CURS= OR0_, id), \ bbeb64d0eb78f4 Harry Wentland 2019-05-07 @46 SRI(CURSOR_POSITION, CUR= SOR0_, id), \ bbeb64d0eb78f4 Harry Wentland 2019-05-07 @47 SRI(CURSOR_HOT_SPOT, CUR= SOR0_, id), \ bbeb64d0eb78f4 Harry Wentland 2019-05-07 @48 SRI(CURSOR_DST_OFFSET, C= URSOR0_, id), \ bbeb64d0eb78f4 Harry Wentland 2019-05-07 @49 SRI(DMDATA_ADDRESS_HIGH,= CURSOR0_, id), \ bbeb64d0eb78f4 Harry Wentland 2019-05-07 @50 SRI(DMDATA_ADDRESS_LOW, = CURSOR0_, id), \ bbeb64d0eb78f4 Harry Wentland 2019-05-07 @51 SRI(DMDATA_CNTL, CURSOR0= _, id), \ bbeb64d0eb78f4 Harry Wentland 2019-05-07 @52 SRI(DMDATA_SW_CNTL, CURS= OR0_, id), \ bbeb64d0eb78f4 Harry Wentland 2019-05-07 @53 SRI(DMDATA_QOS_CNTL, CUR= SOR0_, id), \ bbeb64d0eb78f4 Harry Wentland 2019-05-07 @54 SRI(DMDATA_SW_DATA, CURS= OR0_, id), \ bbeb64d0eb78f4 Harry Wentland 2019-05-07 @55 SRI(DMDATA_STATUS, CURSO= R0_, id),\ bbeb64d0eb78f4 Harry Wentland 2019-05-07 @56 SRI(FLIP_PARAMETERS_0, H= UBPREQ, id),\ bbeb64d0eb78f4 Harry Wentland 2019-05-07 @57 SRI(FLIP_PARAMETERS_1, H= UBPREQ, id),\ bbeb64d0eb78f4 Harry Wentland 2019-05-07 @58 SRI(FLIP_PARAMETERS_2, H= UBPREQ, id),\ 4850ce697f9892 Charlene Liu 2019-05-07 @59 SRI(DCN_CUR1_TTU_CNTL0, = HUBPREQ, id),\ bbeb64d0eb78f4 Harry Wentland 2019-05-07 @60 SRI(DCN_CUR1_TTU_CNTL1, = HUBPREQ, id),\ bbeb64d0eb78f4 Harry Wentland 2019-05-07 @61 SRI(DCSURF_FLIP_CONTROL2= , HUBPREQ, id), \ 0213541d4b6b24 Yongqiang Sun 2019-03-28 @62 SRI(VMID_SETTINGS_0, HUB= PREQ, id) 0213541d4b6b24 Yongqiang Sun 2019-03-28 63 = 0213541d4b6b24 Yongqiang Sun 2019-03-28 64 #define HUBP_REG_LIST_DCN= 20(id)\ 0213541d4b6b24 Yongqiang Sun 2019-03-28 65 HUBP_REG_LIST_DCN2_COMMO= N(id),\ bbeb64d0eb78f4 Harry Wentland 2019-05-07 @66 SR(DCN_VM_SYSTEM_APERTUR= E_DEFAULT_ADDR_MSB),\ bbeb64d0eb78f4 Harry Wentland 2019-05-07 @67 SR(DCN_VM_SYSTEM_APERTUR= E_DEFAULT_ADDR_LSB) bbeb64d0eb78f4 Harry Wentland 2019-05-07 68 = c70b4016306a10 Charlene Liu 2019-06-05 69 #define HUBP_MASK_SH_LIST= _DCN2_SHARE_COMMON(mask_sh)\ c70b4016306a10 Charlene Liu 2019-06-05 70 HUBP_MASK_SH_LIST_DCN_SH= ARE_COMMON(mask_sh),\ bbeb64d0eb78f4 Harry Wentland 2019-05-07 71 HUBP_MASK_SH_LIST_DCN_VM= (mask_sh),\ bbeb64d0eb78f4 Harry Wentland 2019-05-07 @72 HUBP_SF(HUBP0_DCSURF_SUR= FACE_CONFIG, ROTATION_ANGLE, mask_sh),\ bbeb64d0eb78f4 Harry Wentland 2019-05-07 @73 HUBP_SF(HUBP0_DCSURF_SUR= FACE_CONFIG, H_MIRROR_EN, mask_sh),\ bbeb64d0eb78f4 Harry Wentland 2019-05-07 @74 HUBP_SF(HUBPREQ0_PREFETC= H_SETTINGS, DST_Y_PREFETCH, mask_sh),\ bbeb64d0eb78f4 Harry Wentland 2019-05-07 @75 HUBP_SF(HUBPREQ0_PREFETC= H_SETTINGS, VRATIO_PREFETCH, mask_sh),\ bbeb64d0eb78f4 Harry Wentland 2019-05-07 @76 HUBP_SF(HUBPREQ0_PREFETC= H_SETTINGS_C, VRATIO_PREFETCH_C, mask_sh),\ bbeb64d0eb78f4 Harry Wentland 2019-05-07 @77 HUBP_SF(HUBPREQ0_DCN_VM_= SYSTEM_APERTURE_LOW_ADDR, MC_VM_SYSTEM_APERTURE_LOW_ADDR, mask_sh),\ bbeb64d0eb78f4 Harry Wentland 2019-05-07 @78 HUBP_SF(HUBPREQ0_DCN_VM_= SYSTEM_APERTURE_HIGH_ADDR, MC_VM_SYSTEM_APERTURE_HIGH_ADDR, mask_sh),\ bbeb64d0eb78f4 Harry Wentland 2019-05-07 @79 HUBP_SF(HUBPREQ0_CURSOR_= SETTINGS, CURSOR0_DST_Y_OFFSET, mask_sh), \ bbeb64d0eb78f4 Harry Wentland 2019-05-07 @80 HUBP_SF(HUBPREQ0_CURSOR_= SETTINGS, CURSOR0_CHUNK_HDL_ADJUST, mask_sh), \ bbeb64d0eb78f4 Harry Wentland 2019-05-07 @81 HUBP_SF(CURSOR0_0_CURSOR= _SURFACE_ADDRESS_HIGH, CURSOR_SURFACE_ADDRESS_HIGH, mask_sh), \ bbeb64d0eb78f4 Harry Wentland 2019-05-07 @82 HUBP_SF(CURSOR0_0_CURSOR= _SURFACE_ADDRESS, CURSOR_SURFACE_ADDRESS, mask_sh), \ bbeb64d0eb78f4 Harry Wentland 2019-05-07 @83 HUBP_SF(CURSOR0_0_CURSOR= _SIZE, CURSOR_WIDTH, mask_sh), \ bbeb64d0eb78f4 Harry Wentland 2019-05-07 @84 HUBP_SF(CURSOR0_0_CURSOR= _SIZE, CURSOR_HEIGHT, mask_sh), \ bbeb64d0eb78f4 Harry Wentland 2019-05-07 @85 HUBP_SF(CURSOR0_0_CURSOR= _CONTROL, CURSOR_MODE, mask_sh), \ bbeb64d0eb78f4 Harry Wentland 2019-05-07 @86 HUBP_SF(CURSOR0_0_CURSOR= _CONTROL, CURSOR_2X_MAGNIFY, mask_sh), \ bbeb64d0eb78f4 Harry Wentland 2019-05-07 @87 HUBP_SF(CURSOR0_0_CURSOR= _CONTROL, CURSOR_PITCH, mask_sh), \ bbeb64d0eb78f4 Harry Wentland 2019-05-07 @88 HUBP_SF(CURSOR0_0_CURSOR= _CONTROL, CURSOR_LINES_PER_CHUNK, mask_sh), \ bbeb64d0eb78f4 Harry Wentland 2019-05-07 @89 HUBP_SF(CURSOR0_0_CURSOR= _CONTROL, CURSOR_ENABLE, mask_sh), \ bbeb64d0eb78f4 Harry Wentland 2019-05-07 @90 HUBP_SF(CURSOR0_0_CURSOR= _POSITION, CURSOR_X_POSITION, mask_sh), \ bbeb64d0eb78f4 Harry Wentland 2019-05-07 @91 HUBP_SF(CURSOR0_0_CURSOR= _POSITION, CURSOR_Y_POSITION, mask_sh), \ bbeb64d0eb78f4 Harry Wentland 2019-05-07 @92 HUBP_SF(CURSOR0_0_CURSOR= _HOT_SPOT, CURSOR_HOT_SPOT_X, mask_sh), \ bbeb64d0eb78f4 Harry Wentland 2019-05-07 @93 HUBP_SF(CURSOR0_0_CURSOR= _HOT_SPOT, CURSOR_HOT_SPOT_Y, mask_sh), \ bbeb64d0eb78f4 Harry Wentland 2019-05-07 @94 HUBP_SF(CURSOR0_0_CURSOR= _DST_OFFSET, CURSOR_DST_X_OFFSET, mask_sh), \ bbeb64d0eb78f4 Harry Wentland 2019-05-07 @95 HUBP_SF(CURSOR0_0_DMDATA= _ADDRESS_HIGH, DMDATA_ADDRESS_HIGH, mask_sh), \ bbeb64d0eb78f4 Harry Wentland 2019-05-07 @96 HUBP_SF(CURSOR0_0_DMDATA= _CNTL, DMDATA_MODE, mask_sh), \ bbeb64d0eb78f4 Harry Wentland 2019-05-07 @97 HUBP_SF(CURSOR0_0_DMDATA= _CNTL, DMDATA_UPDATED, mask_sh), \ bbeb64d0eb78f4 Harry Wentland 2019-05-07 @98 HUBP_SF(CURSOR0_0_DMDATA= _CNTL, DMDATA_REPEAT, mask_sh), \ bbeb64d0eb78f4 Harry Wentland 2019-05-07 @99 HUBP_SF(CURSOR0_0_DMDATA= _CNTL, DMDATA_SIZE, mask_sh), \ bbeb64d0eb78f4 Harry Wentland 2019-05-07 @100 HUBP_SF(CURSOR0_0_DMDATA= _SW_CNTL, DMDATA_SW_UPDATED, mask_sh), \ bbeb64d0eb78f4 Harry Wentland 2019-05-07 @101 HUBP_SF(CURSOR0_0_DMDATA= _SW_CNTL, DMDATA_SW_REPEAT, mask_sh), \ bbeb64d0eb78f4 Harry Wentland 2019-05-07 @102 HUBP_SF(CURSOR0_0_DMDATA= _SW_CNTL, DMDATA_SW_SIZE, mask_sh), \ bbeb64d0eb78f4 Harry Wentland 2019-05-07 @103 HUBP_SF(CURSOR0_0_DMDATA= _QOS_CNTL, DMDATA_QOS_MODE, mask_sh), \ bbeb64d0eb78f4 Harry Wentland 2019-05-07 @104 HUBP_SF(CURSOR0_0_DMDATA= _QOS_CNTL, DMDATA_QOS_LEVEL, mask_sh), \ bbeb64d0eb78f4 Harry Wentland 2019-05-07 @105 HUBP_SF(CURSOR0_0_DMDATA= _QOS_CNTL, DMDATA_DL_DELTA, mask_sh), \ bbeb64d0eb78f4 Harry Wentland 2019-05-07 @106 HUBP_SF(CURSOR0_0_DMDATA= _STATUS, DMDATA_DONE, mask_sh),\ bbeb64d0eb78f4 Harry Wentland 2019-05-07 @107 HUBP_SF(HUBPREQ0_FLIP_PA= RAMETERS_0, DST_Y_PER_VM_FLIP, mask_sh),\ bbeb64d0eb78f4 Harry Wentland 2019-05-07 @108 HUBP_SF(HUBPREQ0_FLIP_PA= RAMETERS_0, DST_Y_PER_ROW_FLIP, mask_sh),\ bbeb64d0eb78f4 Harry Wentland 2019-05-07 @109 HUBP_SF(HUBPREQ0_FLIP_PA= RAMETERS_1, REFCYC_PER_PTE_GROUP_FLIP_L, mask_sh),\ bbeb64d0eb78f4 Harry Wentland 2019-05-07 @110 HUBP_SF(HUBPREQ0_FLIP_PA= RAMETERS_2, REFCYC_PER_META_CHUNK_FLIP_L, mask_sh),\ bbeb64d0eb78f4 Harry Wentland 2019-05-07 @111 HUBP_SF(HUBP0_DCHUBP_CNT= L, HUBP_VREADY_AT_OR_AFTER_VSYNC, mask_sh),\ bbeb64d0eb78f4 Harry Wentland 2019-05-07 @112 HUBP_SF(HUBP0_DCHUBP_CNT= L, HUBP_DISABLE_STOP_DATA_DURING_VM, mask_sh),\ bbeb64d0eb78f4 Harry Wentland 2019-05-07 @113 HUBP_SF(HUBPREQ0_DCSURF_= FLIP_CONTROL, HUBPREQ_MASTER_UPDATE_LOCK_STATUS, mask_sh),\ bbeb64d0eb78f4 Harry Wentland 2019-05-07 @114 HUBP_SF(HUBPREQ0_DCSURF_= FLIP_CONTROL2, SURFACE_GSL_ENABLE, mask_sh),\ bbeb64d0eb78f4 Harry Wentland 2019-05-07 @115 HUBP_SF(HUBPREQ0_DCSURF_= FLIP_CONTROL2, SURFACE_TRIPLE_BUFFER_ENABLE, mask_sh),\ 0213541d4b6b24 Yongqiang Sun 2019-03-28 @116 HUBP_SF(HUBPREQ0_VMID_SE= TTINGS_0, VMID, mask_sh) 0213541d4b6b24 Yongqiang Sun 2019-03-28 117 = c70b4016306a10 Charlene Liu 2019-06-05 118 /*DCN2.x and DCN1.x*/ c70b4016306a10 Charlene Liu 2019-06-05 119 #define HUBP_MASK_SH_LIST= _DCN2_COMMON(mask_sh)\ c70b4016306a10 Charlene Liu 2019-06-05 120 HUBP_MASK_SH_LIST_DCN2_S= HARE_COMMON(mask_sh),\ c70b4016306a10 Charlene Liu 2019-06-05 @121 HUBP_SF(HUBP0_DCSURF_TIL= ING_CONFIG, RB_ALIGNED, mask_sh),\ c70b4016306a10 Charlene Liu 2019-06-05 @122 HUBP_SF(HUBP0_DCHUBP_REQ= _SIZE_CONFIG, MPTE_GROUP_SIZE, mask_sh),\ c70b4016306a10 Charlene Liu 2019-06-05 @123 HUBP_SF(HUBP0_DCHUBP_REQ= _SIZE_CONFIG_C, MPTE_GROUP_SIZE_C, mask_sh) c70b4016306a10 Charlene Liu 2019-06-05 124 = c70b4016306a10 Charlene Liu 2019-06-05 125 /*DCN2.0 specific*/ 0213541d4b6b24 Yongqiang Sun 2019-03-28 126 #define HUBP_MASK_SH_LIST= _DCN20(mask_sh)\ 0213541d4b6b24 Yongqiang Sun 2019-03-28 127 HUBP_MASK_SH_LIST_DCN2_C= OMMON(mask_sh),\ bbeb64d0eb78f4 Harry Wentland 2019-05-07 @128 HUBP_SF(DCN_VM_SYSTEM_AP= ERTURE_DEFAULT_ADDR_MSB, DCN_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM, mask_sh),\ bbeb64d0eb78f4 Harry Wentland 2019-05-07 @129 HUBP_SF(DCN_VM_SYSTEM_AP= ERTURE_DEFAULT_ADDR_MSB, DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, mask_sh),\ bbeb64d0eb78f4 Harry Wentland 2019-05-07 @130 HUBP_SF(DCN_VM_SYSTEM_AP= ERTURE_DEFAULT_ADDR_LSB, DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, mask_sh) bbeb64d0eb78f4 Harry Wentland 2019-05-07 131 = c70b4016306a10 Charlene Liu 2019-06-05 132 /*DCN2.x */ bbeb64d0eb78f4 Harry Wentland 2019-05-07 133 #define DCN2_HUBP_REG_COM= MON_VARIABLE_LIST \ bbeb64d0eb78f4 Harry Wentland 2019-05-07 134 HUBP_COMMON_REG_VARIABLE= _LIST; \ bbeb64d0eb78f4 Harry Wentland 2019-05-07 135 uint32_t DMDATA_ADDRESS_= HIGH; \ bbeb64d0eb78f4 Harry Wentland 2019-05-07 136 uint32_t DMDATA_ADDRESS_= LOW; \ bbeb64d0eb78f4 Harry Wentland 2019-05-07 137 uint32_t DMDATA_CNTL; \ bbeb64d0eb78f4 Harry Wentland 2019-05-07 138 uint32_t DMDATA_SW_CNTL;= \ bbeb64d0eb78f4 Harry Wentland 2019-05-07 139 uint32_t DMDATA_QOS_CNTL= ; \ bbeb64d0eb78f4 Harry Wentland 2019-05-07 140 uint32_t DMDATA_SW_DATA;= \ bbeb64d0eb78f4 Harry Wentland 2019-05-07 141 uint32_t DMDATA_STATUS;\ bbeb64d0eb78f4 Harry Wentland 2019-05-07 142 uint32_t DCSURF_FLIP_CON= TROL2;\ bbeb64d0eb78f4 Harry Wentland 2019-05-07 143 uint32_t FLIP_PARAMETERS= _0;\ bbeb64d0eb78f4 Harry Wentland 2019-05-07 144 uint32_t FLIP_PARAMETERS= _1;\ bbeb64d0eb78f4 Harry Wentland 2019-05-07 145 uint32_t FLIP_PARAMETERS= _2;\ 4850ce697f9892 Charlene Liu 2019-05-07 146 uint32_t DCN_CUR1_TTU_CN= TL0;\ bbeb64d0eb78f4 Harry Wentland 2019-05-07 147 uint32_t DCN_CUR1_TTU_CN= TL1;\ c70b4016306a10 Charlene Liu 2019-06-05 148 uint32_t VMID_SETTINGS_0 c70b4016306a10 Charlene Liu 2019-06-05 149 = bbeb64d0eb78f4 Harry Wentland 2019-05-07 150 = 6162ba9234c124 Yifan Zhang 2019-11-28 151 #if defined(CONFIG_DRM_AM= D_DC_DCN2_1) 35b82ba8f2fa9b Bhawanpreet Lakha 2019-08-28 152 #define DCN21_HUBP_REG_CO= MMON_VARIABLE_LIST \ 35b82ba8f2fa9b Bhawanpreet Lakha 2019-08-28 153 DCN2_HUBP_REG_COMMON_VAR= IABLE_LIST; \ 35b82ba8f2fa9b Bhawanpreet Lakha 2019-08-28 154 uint32_t FLIP_PARAMETERS= _3;\ 35b82ba8f2fa9b Bhawanpreet Lakha 2019-08-28 155 uint32_t FLIP_PARAMETERS= _4;\ 35b82ba8f2fa9b Bhawanpreet Lakha 2019-08-28 156 uint32_t FLIP_PARAMETERS= _5;\ 35b82ba8f2fa9b Bhawanpreet Lakha 2019-08-28 157 uint32_t FLIP_PARAMETERS= _6;\ 35b82ba8f2fa9b Bhawanpreet Lakha 2019-08-28 158 uint32_t VBLANK_PARAMETE= RS_5;\ 35b82ba8f2fa9b Bhawanpreet Lakha 2019-08-28 159 uint32_t VBLANK_PARAMETE= RS_6 6162ba9234c124 Yifan Zhang 2019-11-28 160 #endif 35b82ba8f2fa9b Bhawanpreet Lakha 2019-08-28 161 = d2898ece6bedb5 Bhawanpreet Lakha 2020-05-21 162 #if defined(CONFIG_DRM_AM= D_DC_DCN3_0) d2898ece6bedb5 Bhawanpreet Lakha 2020-05-21 163 #define DCN30_HUBP_REG_CO= MMON_VARIABLE_LIST \ d2898ece6bedb5 Bhawanpreet Lakha 2020-05-21 @164 DCN21_HUBP_REG_COMMON_VA= RIABLE_LIST;\ d2898ece6bedb5 Bhawanpreet Lakha 2020-05-21 165 uint32_t DCN_DMDATA_VM_C= NTL d2898ece6bedb5 Bhawanpreet Lakha 2020-05-21 166 #endif d2898ece6bedb5 Bhawanpreet Lakha 2020-05-21 167 = bbeb64d0eb78f4 Harry Wentland 2019-05-07 168 #define DCN2_HUBP_REG_FIE= LD_VARIABLE_LIST(type) \ c70b4016306a10 Charlene Liu 2019-06-05 169 DCN_HUBP_REG_FIELD_BASE_= LIST(type); \ bbeb64d0eb78f4 Harry Wentland 2019-05-07 170 type DMDATA_ADDRESS_HIGH= ;\ bbeb64d0eb78f4 Harry Wentland 2019-05-07 171 type DMDATA_MODE;\ bbeb64d0eb78f4 Harry Wentland 2019-05-07 172 type DMDATA_UPDATED;\ bbeb64d0eb78f4 Harry Wentland 2019-05-07 173 type DMDATA_REPEAT;\ bbeb64d0eb78f4 Harry Wentland 2019-05-07 174 type DMDATA_SIZE;\ bbeb64d0eb78f4 Harry Wentland 2019-05-07 175 type DMDATA_SW_UPDATED;\ bbeb64d0eb78f4 Harry Wentland 2019-05-07 176 type DMDATA_SW_REPEAT;\ bbeb64d0eb78f4 Harry Wentland 2019-05-07 177 type DMDATA_SW_SIZE;\ bbeb64d0eb78f4 Harry Wentland 2019-05-07 178 type DMDATA_QOS_MODE;\ bbeb64d0eb78f4 Harry Wentland 2019-05-07 179 type DMDATA_QOS_LEVEL;\ bbeb64d0eb78f4 Harry Wentland 2019-05-07 180 type DMDATA_DL_DELTA;\ bbeb64d0eb78f4 Harry Wentland 2019-05-07 181 type DMDATA_DONE;\ bbeb64d0eb78f4 Harry Wentland 2019-05-07 182 type DST_Y_PER_VM_FLIP;\ bbeb64d0eb78f4 Harry Wentland 2019-05-07 183 type DST_Y_PER_ROW_FLIP;\ bbeb64d0eb78f4 Harry Wentland 2019-05-07 184 type REFCYC_PER_PTE_GROU= P_FLIP_L;\ bbeb64d0eb78f4 Harry Wentland 2019-05-07 185 type REFCYC_PER_META_CHU= NK_FLIP_L;\ bbeb64d0eb78f4 Harry Wentland 2019-05-07 186 type HUBP_VREADY_AT_OR_A= FTER_VSYNC;\ bbeb64d0eb78f4 Harry Wentland 2019-05-07 187 type HUBP_DISABLE_STOP_D= ATA_DURING_VM;\ bbeb64d0eb78f4 Harry Wentland 2019-05-07 188 type HUBPREQ_MASTER_UPDA= TE_LOCK_STATUS;\ bbeb64d0eb78f4 Harry Wentland 2019-05-07 189 type SURFACE_GSL_ENABLE;\ bbeb64d0eb78f4 Harry Wentland 2019-05-07 190 type SURFACE_TRIPLE_BUFF= ER_ENABLE;\ 64f223b0dd1200 Yongqiang Sun 2019-04-02 191 type VMID 64f223b0dd1200 Yongqiang Sun 2019-04-02 192 = 6162ba9234c124 Yifan Zhang 2019-11-28 193 #ifdef CONFIG_DRM_AMD_DC_= DCN2_1 35b82ba8f2fa9b Bhawanpreet Lakha 2019-08-28 194 #define DCN21_HUBP_REG_FI= ELD_VARIABLE_LIST(type) \ 35b82ba8f2fa9b Bhawanpreet Lakha 2019-08-28 195 DCN2_HUBP_REG_FIELD_VARI= ABLE_LIST(type);\ 35b82ba8f2fa9b Bhawanpreet Lakha 2019-08-28 196 type REFCYC_PER_VM_GROUP= _FLIP;\ 35b82ba8f2fa9b Bhawanpreet Lakha 2019-08-28 197 type REFCYC_PER_VM_REQ_F= LIP;\ 35b82ba8f2fa9b Bhawanpreet Lakha 2019-08-28 198 type REFCYC_PER_VM_GROUP= _VBLANK;\ 35b82ba8f2fa9b Bhawanpreet Lakha 2019-08-28 199 type REFCYC_PER_VM_REQ_V= BLANK;\ 35b82ba8f2fa9b Bhawanpreet Lakha 2019-08-28 200 type REFCYC_PER_PTE_GROU= P_FLIP_C; \ 35b82ba8f2fa9b Bhawanpreet Lakha 2019-08-28 201 type REFCYC_PER_META_CHU= NK_FLIP_C; \ 35b82ba8f2fa9b Bhawanpreet Lakha 2019-08-28 202 type VM_GROUP_SIZE 6162ba9234c124 Yifan Zhang 2019-11-28 203 #endif 35b82ba8f2fa9b Bhawanpreet Lakha 2019-08-28 204 = d2898ece6bedb5 Bhawanpreet Lakha 2020-05-21 205 #if defined(CONFIG_DRM_AM= D_DC_DCN3_0) d2898ece6bedb5 Bhawanpreet Lakha 2020-05-21 206 #define DCN30_HUBP_REG_FI= ELD_VARIABLE_LIST(type) \ d2898ece6bedb5 Bhawanpreet Lakha 2020-05-21 @207 DCN21_HUBP_REG_FIELD_VAR= IABLE_LIST(type);\ d2898ece6bedb5 Bhawanpreet Lakha 2020-05-21 208 type PRIMARY_SURFACE_DCC= _IND_BLK;\ d2898ece6bedb5 Bhawanpreet Lakha 2020-05-21 209 type SECONDARY_SURFACE_D= CC_IND_BLK;\ d2898ece6bedb5 Bhawanpreet Lakha 2020-05-21 210 type PRIMARY_SURFACE_DCC= _IND_BLK_C;\ d2898ece6bedb5 Bhawanpreet Lakha 2020-05-21 211 type SECONDARY_SURFACE_D= CC_IND_BLK_C;\ d2898ece6bedb5 Bhawanpreet Lakha 2020-05-21 212 type ALPHA_PLANE_EN;\ d2898ece6bedb5 Bhawanpreet Lakha 2020-05-21 213 type REFCYC_PER_VM_DMDAT= A;\ d2898ece6bedb5 Bhawanpreet Lakha 2020-05-21 214 type DMDATA_VM_FAULT_STA= TUS;\ d2898ece6bedb5 Bhawanpreet Lakha 2020-05-21 215 type DMDATA_VM_FAULT_STA= TUS_CLEAR; \ d2898ece6bedb5 Bhawanpreet Lakha 2020-05-21 216 type DMDATA_VM_UNDERFLOW= _STATUS;\ d2898ece6bedb5 Bhawanpreet Lakha 2020-05-21 217 type DMDATA_VM_LATE_STAT= US;\ d2898ece6bedb5 Bhawanpreet Lakha 2020-05-21 218 type DMDATA_VM_UNDERFLOW= _STATUS_CLEAR; \ d2898ece6bedb5 Bhawanpreet Lakha 2020-05-21 219 type DMDATA_VM_DONE; \ d2898ece6bedb5 Bhawanpreet Lakha 2020-05-21 220 type CROSSBAR_SRC_Y_G; \ d2898ece6bedb5 Bhawanpreet Lakha 2020-05-21 221 type CROSSBAR_SRC_ALPHA;= \ d2898ece6bedb5 Bhawanpreet Lakha 2020-05-21 222 type PACK_3TO2_ELEMENT_D= ISABLE; \ d2898ece6bedb5 Bhawanpreet Lakha 2020-05-21 223 type ROW_TTU_MODE; \ d2898ece6bedb5 Bhawanpreet Lakha 2020-05-21 224 type NUM_PKRS d2898ece6bedb5 Bhawanpreet Lakha 2020-05-21 225 #endif bbeb64d0eb78f4 Harry Wentland 2019-05-07 226 = :::::: The code at line 164 was first introduced by commit :::::: d2898ece6bedb5a51e5822369af38c7fda182838 drm/amd/display: Add DCN3 H= UBP :::::: TO: Bhawanpreet Lakha :::::: CC: Yang Xiong --- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org --===============3421469896192445084== Content-Type: application/gzip MIME-Version: 1.0 Content-Transfer-Encoding: base64 Content-Disposition: attachment; filename="config.gz" H4sICDCEuF8AAy5jb25maWcAlDzLcty2svt8xZSzSRZxJEtWnHtLC5AEOcgQBA2AoxltUIo8TlSx JV89TuK/v90AHwAIjnNSqUSDbjRe/UaD33/3/Yq8PD98vnm+u7359Onr6o/D/eHx5vnwYfXx7tPh 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--===============3421469896192445084==--