From: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
To: Sia Jee Heng <jee.heng.sia@intel.com>
Cc: vkoul@kernel.org, Eugeniy.Paltsev@synopsys.com,
robh+dt@kernel.org, dmaengine@vger.kernel.org,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org
Subject: Re: [PATCH v5 16/16] dmaengine: dw-axi-dmac: Virtually split the linked-list
Date: Mon, 23 Nov 2020 12:22:56 +0200 [thread overview]
Message-ID: <20201123102256.GV4077@smile.fi.intel.com> (raw)
In-Reply-To: <20201123023452.7894-17-jee.heng.sia@intel.com>
On Mon, Nov 23, 2020 at 10:34:52AM +0800, Sia Jee Heng wrote:
> AxiDMA driver exposed the dma_set_max_seg_size() to the DMAENGINE.
> It shall helps the DMA clients to create size-optimized linked-list
> for the controller.
>
> However, there are certain situations where DMA client might not be
> abled to benefit from the dma_get_max_seg_size() if the segment size
> can't meet the nature of the DMA client's operation.
>
> In the case of ALSA operation, ALSA application and driver expecting
> to run in a period of larger than 10ms regardless of the bit depth.
> With this large period, there is a strong request to split the linked-list
> in the AxiDMA driver.
I'm wondering why ASoC generic code can't use DMA channel and device
capabilities and prepare SG list with all limitations taken into account.
--
With Best Regards,
Andy Shevchenko
next prev parent reply other threads:[~2020-11-23 10:22 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-11-23 2:34 [PATCH v5 00/16] dmaengine: dw-axi-dmac: support Intel KeemBay AxiDMA Sia Jee Heng
2020-11-23 2:34 ` [PATCH v5 01/16] dt-bindings: dma: Add YAML schemas for dw-axi-dmac Sia Jee Heng
2020-11-30 22:25 ` Rob Herring
2020-12-09 3:21 ` Sia, Jee Heng
2020-12-10 1:22 ` Sia, Jee Heng
2020-11-23 2:34 ` [PATCH v5 02/16] dmaengine: dw-axi-dmac: simplify descriptor management Sia Jee Heng
2020-11-23 2:34 ` [PATCH v5 03/16] dmaengine: dw-axi-dmac: move dma_pool_create() to alloc_chan_resources() Sia Jee Heng
2020-11-23 2:34 ` [PATCH v5 04/16] dmaengine: dw-axi-dmac: Add device_synchronize() callback Sia Jee Heng
2020-11-23 2:34 ` [PATCH v5 05/16] dmaengine: dw-axi-dmac: Add device_config operation Sia Jee Heng
2020-11-23 2:34 ` [PATCH v5 06/16] dmaengine: dw-axi-dmac: Support device_prep_slave_sg Sia Jee Heng
2020-11-23 2:34 ` [PATCH v5 07/16] dmaegine: dw-axi-dmac: Support device_prep_dma_cyclic() Sia Jee Heng
2020-11-23 2:34 ` [PATCH v5 08/16] dmaengine: dw-axi-dmac: Support of_dma_controller_register() Sia Jee Heng
2020-11-23 2:34 ` [PATCH v5 09/16] dmaengine: dw-axi-dmac: Support burst residue granularity Sia Jee Heng
2020-11-23 2:34 ` [PATCH v5 10/16] dt-binding: dma: dw-axi-dmac: Add support for Intel KeemBay AxiDMA Sia Jee Heng
2020-11-30 22:29 ` Rob Herring
2020-12-09 1:53 ` Sia, Jee Heng
2020-11-23 2:34 ` [PATCH v5 11/16] dmaengine: dw-axi-dmac: Add Intel KeemBay DMA register fields Sia Jee Heng
2020-11-23 2:34 ` [PATCH v5 12/16] dmaengine: dw-axi-dmac: Add Intel KeemBay AxiDMA support Sia Jee Heng
2020-11-23 2:34 ` [PATCH v5 13/16] dmaengine: dw-axi-dmac: Add Intel KeemBay AxiDMA handshake Sia Jee Heng
2020-11-23 2:34 ` [PATCH v5 14/16] dmaengine: dw-axi-dmac: Add Intel KeemBay AxiDMA BYTE and HALFWORD registers Sia Jee Heng
2020-11-23 2:34 ` [PATCH v5 15/16] dmaengine: dw-axi-dmac: Set constraint to the Max segment size Sia Jee Heng
2020-11-23 2:34 ` [PATCH v5 16/16] dmaengine: dw-axi-dmac: Virtually split the linked-list Sia Jee Heng
2020-11-23 10:22 ` Andy Shevchenko [this message]
2020-12-09 1:47 ` Sia, Jee Heng
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