From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5DF30C2D0E4 for ; Mon, 23 Nov 2020 22:12:35 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id DB056206B7 for ; Mon, 23 Nov 2020 22:12:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728649AbgKWWMO (ORCPT ); Mon, 23 Nov 2020 17:12:14 -0500 Received: from asavdk3.altibox.net ([109.247.116.14]:43524 "EHLO asavdk3.altibox.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731193AbgKWWMO (ORCPT ); Mon, 23 Nov 2020 17:12:14 -0500 Received: from ravnborg.org (unknown [188.228.123.71]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by asavdk3.altibox.net (Postfix) with ESMTPS id A547420060; Mon, 23 Nov 2020 23:12:01 +0100 (CET) Date: Mon, 23 Nov 2020 23:12:00 +0100 From: Sam Ravnborg To: Linus Walleij Cc: dri-devel@lists.freedesktop.org, Maarten Lankhorst , Maxime Ripard , Sean Paul , upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, Stephan Gerhold , linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH 2/2] drm/mcde: Support DPI output Message-ID: <20201123221200.GC676783@ravnborg.org> References: <20201112142925.2571179-1-linus.walleij@linaro.org> <20201112142925.2571179-2-linus.walleij@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20201112142925.2571179-2-linus.walleij@linaro.org> X-CMAE-Score: 0 X-CMAE-Analysis: v=2.3 cv=VbvZwmh9 c=1 sm=1 tr=0 a=S6zTFyMACwkrwXSdXUNehg==:117 a=S6zTFyMACwkrwXSdXUNehg==:17 a=kj9zAlcOel0A:10 a=j8Cu_9a8AAAA:8 a=VwQbUJbxAAAA:8 a=KKAkSRfTAAAA:8 a=7gkXJVJtAAAA:8 a=LIJwATX_UdznJMEaHzIA:9 a=7Zwj6sZBwVKJAoWSPKxL6X1jA+E=:19 a=iwuXaNnC9wzv7rUf:21 a=dUYlXI-I-vqSHrK5:21 a=CjuIK1q_8ugA:10 a=A2jcf3dkIZPIRbEE90CI:22 a=AjGcO6oz07-iQ99wixmX:22 a=cvBusfyB2V15izCimMoJ:22 a=E9Po1WZjFZOl8hwRPBS3:22 Precedence: bulk List-ID: X-Mailing-List: phone-devel@vger.kernel.org Hi Linus. On Thu, Nov 12, 2020 at 03:29:25PM +0100, Linus Walleij wrote: > This implements support for DPI output using the port node > in the device tree to connect a DPI LCD display to the > MCDE. The block also supports TV-out but we leave that > for another day when we have a hardware using it. > > We implement parsing and handling of the "port" node, > and follow that to the DPI endpoint. > > The clock divider used by the MCDE to divide down the > "lcdclk" (this has been designed for TV-like frequencies) > is represented by an ordinary clock provider internally > in the MCDE. This idea was inspired by the PL111 solution > by Eric Anholt: the divider also works very similar to > the Pl111 clock divider. > > We take care to clear up some errors regarding the number > of available formatters and their type. We have 6 DSI > formatters and 2 DPI formatters. > > Tested on the Samsung GT-I9070 Janice mobile phone. > > Cc: Stephan Gerhold > Cc: phone-devel@vger.kernel.org > Cc: upstreaming@lists.sr.ht > Signed-off-by: Linus Walleij > --- > drivers/gpu/drm/mcde/Kconfig | 1 + > drivers/gpu/drm/mcde/Makefile | 2 +- > drivers/gpu/drm/mcde/mcde_clk_div.c | 192 ++++++++++++++ > drivers/gpu/drm/mcde/mcde_display.c | 304 ++++++++++++++++++++--- > drivers/gpu/drm/mcde/mcde_display_regs.h | 87 +++++++ > drivers/gpu/drm/mcde/mcde_drm.h | 10 + > drivers/gpu/drm/mcde/mcde_drv.c | 46 +++- > 7 files changed, 595 insertions(+), 47 deletions(-) > create mode 100644 drivers/gpu/drm/mcde/mcde_clk_div.c > > diff --git a/drivers/gpu/drm/mcde/Kconfig b/drivers/gpu/drm/mcde/Kconfig > index b3990126562c..71c689b573c9 100644 > --- a/drivers/gpu/drm/mcde/Kconfig > +++ b/drivers/gpu/drm/mcde/Kconfig > @@ -4,6 +4,7 @@ config DRM_MCDE > depends on CMA > depends on ARM || COMPILE_TEST > depends on OF > + depends on COMMON_CLK > select MFD_SYSCON > select DRM_MIPI_DSI > select DRM_BRIDGE > diff --git a/drivers/gpu/drm/mcde/Makefile b/drivers/gpu/drm/mcde/Makefile > index fe28f4e0fe46..15d9c89a3273 100644 > --- a/drivers/gpu/drm/mcde/Makefile > +++ b/drivers/gpu/drm/mcde/Makefile > @@ -1,3 +1,3 @@ > -mcde_drm-y += mcde_drv.o mcde_dsi.o mcde_display.o > +mcde_drm-y += mcde_drv.o mcde_dsi.o mcde_clk_div.o mcde_display.o > > obj-$(CONFIG_DRM_MCDE) += mcde_drm.o > diff --git a/drivers/gpu/drm/mcde/mcde_clk_div.c b/drivers/gpu/drm/mcde/mcde_clk_div.c > new file mode 100644 > index 000000000000..038821d2ef80 > --- /dev/null > +++ b/drivers/gpu/drm/mcde/mcde_clk_div.c > @@ -0,0 +1,192 @@ > +// SPDX-License-Identifier: GPL-2.0 > +#include > +#include > + > +#include "mcde_drm.h" > +#include "mcde_display_regs.h" > + > +/* The MCDE internal clock dividers for FIFO A and B */ > +struct mcde_clk_div { > + struct clk_hw hw; > + struct mcde *mcde; > + u32 cr; > + u32 cr_div; > +}; > + > +static int mcde_clk_div_enable(struct clk_hw *hw) > +{ > + struct mcde_clk_div *cdiv = container_of(hw, struct mcde_clk_div, hw); > + struct mcde *mcde = cdiv->mcde; > + u32 val; > + > + spin_lock(&mcde->fifo_crx1_lock); > + val = readl(mcde->regs + cdiv->cr); > + /* > + * Select the PLL72 (LCD) clock as parent > + * FIXME: implement other parents. > + */ > + val &= ~MCDE_CRX1_CLKSEL_MASK; > + val |= MCDE_CRX1_CLKSEL_CLKPLL72 << MCDE_CRX1_CLKSEL_SHIFT; > + /* Internal clock */ > + val |= MCDE_CRA1_CLKTYPE_TVXCLKSEL1; > + > + /* Clear then set the divider */ > + val &= ~(MCDE_CRX1_BCD | MCDE_CRX1_PCD_MASK); > + val |= cdiv->cr_div; > + > + writel(val, mcde->regs + cdiv->cr); > + spin_unlock(&mcde->fifo_crx1_lock); > + > + return 0; > +} > + > +static int mcde_clk_div_choose_div(struct clk_hw *hw, unsigned long rate, > + unsigned long *prate, bool set_parent) > +{ > + int best_div = 1, div; > + struct clk_hw *parent = clk_hw_get_parent(hw); > + unsigned long best_prate = 0; > + unsigned long best_diff = ~0ul; > + int max_div = (1 << MCDE_CRX1_PCD_BITS) - 1; > + > + for (div = 1; div < max_div; div++) { > + unsigned long this_prate, div_rate, diff; > + > + if (set_parent) > + this_prate = clk_hw_round_rate(parent, rate * div); > + else > + this_prate = *prate; > + div_rate = DIV_ROUND_UP_ULL(this_prate, div); > + diff = abs(rate - div_rate); > + > + if (diff < best_diff) { > + best_div = div; > + best_diff = diff; > + best_prate = this_prate; > + } > + } > + > + *prate = best_prate; > + return best_div; > +} > + > +static long mcde_clk_div_round_rate(struct clk_hw *hw, unsigned long rate, > + unsigned long *prate) > +{ > + int div = mcde_clk_div_choose_div(hw, rate, prate, true); > + > + return DIV_ROUND_UP_ULL(*prate, div); > +} > + > +static unsigned long mcde_clk_div_recalc_rate(struct clk_hw *hw, > + unsigned long prate) > +{ > + struct mcde_clk_div *cdiv = container_of(hw, struct mcde_clk_div, hw); > + struct mcde *mcde = cdiv->mcde; > + u32 cr; > + int div; > + > + /* > + * If the MCDE is not powered we can't access registers. > + * It will come up with 0 in the divider register bits, which > + * means "divide by 2". > + */ > + if (!regulator_is_enabled(mcde->epod)) > + return DIV_ROUND_UP_ULL(prate, 2); > + > + cr = readl(mcde->regs + cdiv->cr); > + if (cr & MCDE_CRX1_BCD) > + return prate; > + > + /* 0 in the PCD means "divide by 2", 1 means "divide by 3" etc */ > + div = cr & MCDE_CRX1_PCD_MASK; > + div += 2; > + > + return DIV_ROUND_UP_ULL(prate, div); > +} > + > +static int mcde_clk_div_set_rate(struct clk_hw *hw, unsigned long rate, > + unsigned long prate) > +{ > + struct mcde_clk_div *cdiv = container_of(hw, struct mcde_clk_div, hw); > + int div = mcde_clk_div_choose_div(hw, rate, &prate, false); > + u32 cr = 0; > + > + /* > + * We cache the CR bits to set the divide in the state so that > + * we can call this before we can even write to the hardware. > + */ > + if (div == 1) { > + /* Bypass clock divider */ > + cr |= MCDE_CRX1_BCD; > + } else { > + div -= 2; > + cr |= div & MCDE_CRX1_PCD_MASK; > + } > + cdiv->cr_div = cr; > + > + return 0; > +} > + > +static const struct clk_ops mcde_clk_div_ops = { > + .enable = mcde_clk_div_enable, > + .recalc_rate = mcde_clk_div_recalc_rate, > + .round_rate = mcde_clk_div_round_rate, > + .set_rate = mcde_clk_div_set_rate, > +}; > + > +int mcde_init_clock_divider(struct mcde *mcde) > +{ > + struct device *dev = mcde->dev; > + struct mcde_clk_div *fifoa; > + struct mcde_clk_div *fifob; > + const char *parent_name; > + struct clk_init_data fifoa_init = { const? > + .name = "fifoa", > + .ops = &mcde_clk_div_ops, > + .parent_names = &parent_name, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + }; > + struct clk_init_data fifob_init = { const? > + .name = "fifob", > + .ops = &mcde_clk_div_ops, > + .parent_names = &parent_name, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + }; > + int ret; > + > + spin_lock_init(&mcde->fifo_crx1_lock); > + parent_name = __clk_get_name(mcde->lcd_clk); > + > + /* Allocate 2 clocks */ > + fifoa = devm_kzalloc(dev, sizeof(*fifoa), GFP_KERNEL); > + if (!fifoa) > + return -ENOMEM; > + fifob = devm_kzalloc(dev, sizeof(*fifob), GFP_KERNEL); > + if (!fifob) > + return -ENOMEM; > + > + fifoa->mcde = mcde; > + fifoa->cr = MCDE_CRA1; > + fifoa->hw.init = &fifoa_init; > + ret = devm_clk_hw_register(dev, &fifoa->hw); > + if (ret) { > + dev_err(dev, "error registering FIFO A clock divider\n"); > + return ret; > + } > + mcde->fifoa_clk = fifoa->hw.clk; > + > + fifob->mcde = mcde; > + fifob->cr = MCDE_CRB1; > + fifob->hw.init = &fifob_init; > + ret = devm_clk_hw_register(dev, &fifob->hw); > + if (ret) { > + dev_err(dev, "error registering FIFO B clock divider\n"); > + return ret; > + } > + mcde->fifob_clk = fifob->hw.clk; > + > + return 0; > +} > diff --git a/drivers/gpu/drm/mcde/mcde_display.c b/drivers/gpu/drm/mcde/mcde_display.c > index 66a07e340f8a..14c76d3a8e5a 100644 > --- a/drivers/gpu/drm/mcde/mcde_display.c > +++ b/drivers/gpu/drm/mcde/mcde_display.c > @@ -8,6 +8,7 @@ > #include > #include > #include > +#include > > #include > #include > @@ -16,6 +17,7 @@ > #include > #include > #include > +#include > #include > #include