From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 60C12C64E8A for ; Sun, 29 Nov 2020 23:08:45 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 2EF3C2084C for ; Sun, 29 Nov 2020 23:08:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727543AbgK2XIb (ORCPT ); Sun, 29 Nov 2020 18:08:31 -0500 Received: from mail-wr1-f67.google.com ([209.85.221.67]:33986 "EHLO mail-wr1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726777AbgK2XIb (ORCPT ); Sun, 29 Nov 2020 18:08:31 -0500 Received: by mail-wr1-f67.google.com with SMTP id k14so13093807wrn.1 for ; Sun, 29 Nov 2020 15:08:13 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=wdEq2gl8a+PAeDGUba3SmwX1K8uJGnFaaAqpMDssDWo=; b=kEWl5V3lgFkXYBgiljW0vSbymGvC4efJeDNgxy81ZlHcrZLXK0PfZDBWhwhLyoK3o3 HnAI171us9pK5lFoklmaLs/BbNVcRRMe3AmYiUSlfyRp54SAT6onqEBZrPUDnt2omJPf DhDABqEMRTqyAIBN3OpIH+DoV+2gy41MMwz08bxwnz7x6XGZ8Z1EGnLA3lGGzruqFY4O 5VXFqIY7KCW/mGirLWyFXKswpoFD8crTZWdhQA2eyDhPWXmiL32tZTzhkBBM1R9ojgyB zCQZ70uWgruYrGBHDTpcHXz47eISc48Z6Za24J+YR3OAcSPP4+V7zYPv8CVtSDxFwLxm oOeg== X-Gm-Message-State: AOAM531lv2EPIvBFb7fXYw1rGsRz2sSxGhSN/1vLn2LuHY2hC0lBhBLM XDXQdmABzyE+yOyXZ7123is= X-Google-Smtp-Source: ABdhPJzemcgSIWckEmLG/WoWTheRZkQseBG6J/lGXVepGvFFOylFGIo2a+IOWOYyZ2ycSEeUpAhqng== X-Received: by 2002:adf:ead1:: with SMTP id o17mr25556413wrn.396.1606691267941; Sun, 29 Nov 2020 15:07:47 -0800 (PST) Received: from workstation.lan ([95.155.85.46]) by smtp.gmail.com with ESMTPSA id d2sm24831005wrn.43.2020.11.29.15.07.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 29 Nov 2020 15:07:47 -0800 (PST) From: =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= To: Bjorn Helgaas Cc: Rob Herring , Jonathan Cameron , Jonathan Chocron , Shawn Lin , Heiko Stuebner , Zhou Wang , Lorenzo Pieralisi , Will Deacon , Robert Richter , Michal Simek , Toan Le , Michael Ellerman , Benjamin Herrenschmidt , Paul Mackerras , Thomas Petazzoni , Nicolas Saenz Julienne , Florian Fainelli , Ray Jui , Scott Branden , Jonathan Derrick , linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linuxppc-dev@lists.ozlabs.org, linux-rockchip@lists.infradead.org, linux-rpi-kernel@lists.infradead.org, bcm-kernel-feedback-list@broadcom.com Subject: [PATCH v6 1/5] PCI: Unify ECAM constants in native PCI Express drivers Date: Sun, 29 Nov 2020 23:07:39 +0000 Message-Id: <20201129230743.3006978-2-kw@linux.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20201129230743.3006978-1-kw@linux.com> References: <20201129230743.3006978-1-kw@linux.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Add ECAM-related constants to provide a set of standard constants defining memory address shift values to the byte-level address that can be used to access the PCI Express Configuration Space, and then move native PCI Express controller drivers to use the newly introduced definitions retiring driver-specific ones. Refactor pci_ecam_map_bus() function to use newly added constants so that limits to the bus, device function and offset (now limited to 4K as per the specification) are in place to prevent the defective or malicious caller from supplying incorrect configuration offset and thus targeting the wrong device when accessing extended configuration space. This refactor also allows for the ".bus_shit" initialisers to be dropped when the user is not using a custom value as a default value will be used as per the PCI Express Specification. Suggested-by: Bjorn Helgaas Signed-off-by: Krzysztof Wilczyński --- drivers/pci/controller/dwc/pcie-al.c | 12 ++------- drivers/pci/controller/dwc/pcie-hisi.c | 2 -- drivers/pci/controller/pci-aardvark.c | 13 +++------- drivers/pci/controller/pci-host-generic.c | 1 - drivers/pci/controller/pci-thunder-ecam.c | 1 - drivers/pci/controller/pcie-brcmstb.c | 16 ++---------- drivers/pci/controller/pcie-rockchip-host.c | 27 ++++++++++----------- drivers/pci/controller/pcie-rockchip.h | 8 +----- drivers/pci/controller/pcie-tango.c | 1 - drivers/pci/controller/pcie-xilinx-nwl.c | 9 ++----- drivers/pci/controller/pcie-xilinx.c | 11 ++------- drivers/pci/controller/vmd.c | 11 ++++----- drivers/pci/ecam.c | 23 ++++++++++++------ include/linux/pci-ecam.h | 27 +++++++++++++++++++++ 14 files changed, 73 insertions(+), 89 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-al.c b/drivers/pci/controller/dwc/pcie-al.c index f973fbca90cf..af9e51ab1af8 100644 --- a/drivers/pci/controller/dwc/pcie-al.c +++ b/drivers/pci/controller/dwc/pcie-al.c @@ -76,7 +76,6 @@ static int al_pcie_init(struct pci_config_window *cfg) } const struct pci_ecam_ops al_pcie_ops = { - .bus_shift = 20, .init = al_pcie_init, .pci_ops = { .map_bus = al_pcie_map_bus, @@ -138,8 +137,6 @@ struct al_pcie { struct al_pcie_target_bus_cfg target_bus_cfg; }; -#define PCIE_ECAM_DEVFN(x) (((x) & 0xff) << 12) - #define to_al_pcie(x) dev_get_drvdata((x)->dev) static inline u32 al_pcie_controller_readl(struct al_pcie *pcie, u32 offset) @@ -226,11 +223,6 @@ static void __iomem *al_pcie_conf_addr_map_bus(struct pci_bus *bus, struct al_pcie_target_bus_cfg *target_bus_cfg = &pcie->target_bus_cfg; unsigned int busnr_ecam = busnr & target_bus_cfg->ecam_mask; unsigned int busnr_reg = busnr & target_bus_cfg->reg_mask; - void __iomem *pci_base_addr; - - pci_base_addr = (void __iomem *)((uintptr_t)pp->va_cfg0_base + - (busnr_ecam << 20) + - PCIE_ECAM_DEVFN(devfn)); if (busnr_reg != target_bus_cfg->reg_val) { dev_dbg(pcie->pci->dev, "Changing target bus busnum val from 0x%x to 0x%x\n", @@ -241,7 +233,7 @@ static void __iomem *al_pcie_conf_addr_map_bus(struct pci_bus *bus, target_bus_cfg->reg_mask); } - return pci_base_addr + where; + return pp->va_cfg0_base + PCIE_ECAM_OFFSET(busnr_ecam, devfn, where); } static struct pci_ops al_child_pci_ops = { @@ -264,7 +256,7 @@ static void al_pcie_config_prepare(struct al_pcie *pcie) target_bus_cfg = &pcie->target_bus_cfg; - ecam_bus_mask = (pcie->ecam_size >> 20) - 1; + ecam_bus_mask = (pcie->ecam_size >> PCIE_ECAM_BUS_SHIFT) - 1; if (ecam_bus_mask > 255) { dev_warn(pcie->dev, "ECAM window size is larger than 256MB. Cutting off at 256\n"); ecam_bus_mask = 255; diff --git a/drivers/pci/controller/dwc/pcie-hisi.c b/drivers/pci/controller/dwc/pcie-hisi.c index 5ca86796d43a..8fc5960faf28 100644 --- a/drivers/pci/controller/dwc/pcie-hisi.c +++ b/drivers/pci/controller/dwc/pcie-hisi.c @@ -100,7 +100,6 @@ static int hisi_pcie_init(struct pci_config_window *cfg) } const struct pci_ecam_ops hisi_pcie_ops = { - .bus_shift = 20, .init = hisi_pcie_init, .pci_ops = { .map_bus = hisi_pcie_map_bus, @@ -135,7 +134,6 @@ static int hisi_pcie_platform_init(struct pci_config_window *cfg) } static const struct pci_ecam_ops hisi_pcie_platform_ops = { - .bus_shift = 20, .init = hisi_pcie_platform_init, .pci_ops = { .map_bus = hisi_pcie_map_bus, diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c index 0be485a25327..1043e54c73bd 100644 --- a/drivers/pci/controller/pci-aardvark.c +++ b/drivers/pci/controller/pci-aardvark.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include #include @@ -164,14 +165,6 @@ #define PCIE_CONFIG_WR_TYPE0 0xa #define PCIE_CONFIG_WR_TYPE1 0xb -#define PCIE_CONF_BUS(bus) (((bus) & 0xff) << 20) -#define PCIE_CONF_DEV(dev) (((dev) & 0x1f) << 15) -#define PCIE_CONF_FUNC(fun) (((fun) & 0x7) << 12) -#define PCIE_CONF_REG(reg) ((reg) & 0xffc) -#define PCIE_CONF_ADDR(bus, devfn, where) \ - (PCIE_CONF_BUS(bus) | PCIE_CONF_DEV(PCI_SLOT(devfn)) | \ - PCIE_CONF_FUNC(PCI_FUNC(devfn)) | PCIE_CONF_REG(where)) - #define PIO_RETRY_CNT 500 #define PIO_RETRY_DELAY 2 /* 2 us*/ @@ -687,7 +680,7 @@ static int advk_pcie_rd_conf(struct pci_bus *bus, u32 devfn, advk_writel(pcie, reg, PIO_CTRL); /* Program the address registers */ - reg = PCIE_CONF_ADDR(bus->number, devfn, where); + reg = ALIGN_DOWN(PCIE_ECAM_OFFSET(bus->number, devfn, where), 4); advk_writel(pcie, reg, PIO_ADDR_LS); advk_writel(pcie, 0, PIO_ADDR_MS); @@ -748,7 +741,7 @@ static int advk_pcie_wr_conf(struct pci_bus *bus, u32 devfn, advk_writel(pcie, reg, PIO_CTRL); /* Program the address registers */ - reg = PCIE_CONF_ADDR(bus->number, devfn, where); + reg = ALIGN_DOWN(PCIE_ECAM_OFFSET(bus->number, devfn, where), 4); advk_writel(pcie, reg, PIO_ADDR_LS); advk_writel(pcie, 0, PIO_ADDR_MS); diff --git a/drivers/pci/controller/pci-host-generic.c b/drivers/pci/controller/pci-host-generic.c index b51977abfdf1..63865aeb636b 100644 --- a/drivers/pci/controller/pci-host-generic.c +++ b/drivers/pci/controller/pci-host-generic.c @@ -49,7 +49,6 @@ static void __iomem *pci_dw_ecam_map_bus(struct pci_bus *bus, } static const struct pci_ecam_ops pci_dw_ecam_bus_ops = { - .bus_shift = 20, .pci_ops = { .map_bus = pci_dw_ecam_map_bus, .read = pci_generic_config_read, diff --git a/drivers/pci/controller/pci-thunder-ecam.c b/drivers/pci/controller/pci-thunder-ecam.c index 7e8835fee5f7..f964fd26f7e0 100644 --- a/drivers/pci/controller/pci-thunder-ecam.c +++ b/drivers/pci/controller/pci-thunder-ecam.c @@ -346,7 +346,6 @@ static int thunder_ecam_config_write(struct pci_bus *bus, unsigned int devfn, } const struct pci_ecam_ops pci_thunder_ecam_ops = { - .bus_shift = 20, .pci_ops = { .map_bus = pci_ecam_map_bus, .read = thunder_ecam_config_read, diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c index bea86899bd5d..7fc80fd6f13f 100644 --- a/drivers/pci/controller/pcie-brcmstb.c +++ b/drivers/pci/controller/pcie-brcmstb.c @@ -22,6 +22,7 @@ #include #include #include +#include #include #include #include @@ -127,11 +128,7 @@ #define MSI_INT_MASK_CLR 0x14 #define PCIE_EXT_CFG_DATA 0x8000 - #define PCIE_EXT_CFG_INDEX 0x9000 -#define PCIE_EXT_BUSNUM_SHIFT 20 -#define PCIE_EXT_SLOT_SHIFT 15 -#define PCIE_EXT_FUNC_SHIFT 12 #define PCIE_RGR1_SW_INIT_1_PERST_MASK 0x1 #define PCIE_RGR1_SW_INIT_1_PERST_SHIFT 0x0 @@ -695,15 +692,6 @@ static bool brcm_pcie_link_up(struct brcm_pcie *pcie) return dla && plu; } -/* Configuration space read/write support */ -static inline int brcm_pcie_cfg_index(int busnr, int devfn, int reg) -{ - return ((PCI_SLOT(devfn) & 0x1f) << PCIE_EXT_SLOT_SHIFT) - | ((PCI_FUNC(devfn) & 0x07) << PCIE_EXT_FUNC_SHIFT) - | (busnr << PCIE_EXT_BUSNUM_SHIFT) - | (reg & ~3); -} - static void __iomem *brcm_pcie_map_conf(struct pci_bus *bus, unsigned int devfn, int where) { @@ -716,7 +704,7 @@ static void __iomem *brcm_pcie_map_conf(struct pci_bus *bus, unsigned int devfn, return PCI_SLOT(devfn) ? NULL : base + where; /* For devices, write to the config space index register */ - idx = brcm_pcie_cfg_index(bus->number, devfn, 0); + idx = PCIE_ECAM_OFFSET(bus->number, devfn, 0); writel(idx, pcie->base + PCIE_EXT_CFG_INDEX); return base + PCIE_EXT_CFG_DATA + where; } diff --git a/drivers/pci/controller/pcie-rockchip-host.c b/drivers/pci/controller/pcie-rockchip-host.c index 9705059523a6..f1d08a1b1591 100644 --- a/drivers/pci/controller/pcie-rockchip-host.c +++ b/drivers/pci/controller/pcie-rockchip-host.c @@ -157,12 +157,11 @@ static int rockchip_pcie_rd_other_conf(struct rockchip_pcie *rockchip, struct pci_bus *bus, u32 devfn, int where, int size, u32 *val) { - u32 busdev; + void __iomem *addr; - busdev = PCIE_ECAM_ADDR(bus->number, PCI_SLOT(devfn), - PCI_FUNC(devfn), where); + addr = rockchip->reg_base + PCIE_ECAM_OFFSET(bus->number, devfn, where); - if (!IS_ALIGNED(busdev, size)) { + if (!IS_ALIGNED((uintptr_t)addr, size)) { *val = 0; return PCIBIOS_BAD_REGISTER_NUMBER; } @@ -175,11 +174,11 @@ static int rockchip_pcie_rd_other_conf(struct rockchip_pcie *rockchip, AXI_WRAPPER_TYPE1_CFG); if (size == 4) { - *val = readl(rockchip->reg_base + busdev); + *val = readl(addr); } else if (size == 2) { - *val = readw(rockchip->reg_base + busdev); + *val = readw(addr); } else if (size == 1) { - *val = readb(rockchip->reg_base + busdev); + *val = readb(addr); } else { *val = 0; return PCIBIOS_BAD_REGISTER_NUMBER; @@ -191,11 +190,11 @@ static int rockchip_pcie_wr_other_conf(struct rockchip_pcie *rockchip, struct pci_bus *bus, u32 devfn, int where, int size, u32 val) { - u32 busdev; + void __iomem *addr; - busdev = PCIE_ECAM_ADDR(bus->number, PCI_SLOT(devfn), - PCI_FUNC(devfn), where); - if (!IS_ALIGNED(busdev, size)) + addr = rockchip->reg_base + PCIE_ECAM_OFFSET(bus->number, devfn, where); + + if (!IS_ALIGNED((uintptr_t)addr, size)) return PCIBIOS_BAD_REGISTER_NUMBER; if (pci_is_root_bus(bus->parent)) @@ -206,11 +205,11 @@ static int rockchip_pcie_wr_other_conf(struct rockchip_pcie *rockchip, AXI_WRAPPER_TYPE1_CFG); if (size == 4) - writel(val, rockchip->reg_base + busdev); + writel(val, addr); else if (size == 2) - writew(val, rockchip->reg_base + busdev); + writew(val, addr); else if (size == 1) - writeb(val, rockchip->reg_base + busdev); + writeb(val, addr); else return PCIBIOS_BAD_REGISTER_NUMBER; diff --git a/drivers/pci/controller/pcie-rockchip.h b/drivers/pci/controller/pcie-rockchip.h index c7d0178fc8c2..1650a5087450 100644 --- a/drivers/pci/controller/pcie-rockchip.h +++ b/drivers/pci/controller/pcie-rockchip.h @@ -13,6 +13,7 @@ #include #include +#include /* * The upper 16 bits of PCIE_CLIENT_CONFIG are a write mask for the lower 16 @@ -178,13 +179,6 @@ #define MIN_AXI_ADDR_BITS_PASSED 8 #define PCIE_RC_SEND_PME_OFF 0x11960 #define ROCKCHIP_VENDOR_ID 0x1d87 -#define PCIE_ECAM_BUS(x) (((x) & 0xff) << 20) -#define PCIE_ECAM_DEV(x) (((x) & 0x1f) << 15) -#define PCIE_ECAM_FUNC(x) (((x) & 0x7) << 12) -#define PCIE_ECAM_REG(x) (((x) & 0xfff) << 0) -#define PCIE_ECAM_ADDR(bus, dev, func, reg) \ - (PCIE_ECAM_BUS(bus) | PCIE_ECAM_DEV(dev) | \ - PCIE_ECAM_FUNC(func) | PCIE_ECAM_REG(reg)) #define PCIE_LINK_IS_L2(x) \ (((x) & PCIE_CLIENT_DEBUG_LTSSM_MASK) == PCIE_CLIENT_DEBUG_LTSSM_L2) #define PCIE_LINK_UP(x) \ diff --git a/drivers/pci/controller/pcie-tango.c b/drivers/pci/controller/pcie-tango.c index d093a8ce4bb1..62a061f1d62e 100644 --- a/drivers/pci/controller/pcie-tango.c +++ b/drivers/pci/controller/pcie-tango.c @@ -208,7 +208,6 @@ static int smp8759_config_write(struct pci_bus *bus, unsigned int devfn, } static const struct pci_ecam_ops smp8759_ecam_ops = { - .bus_shift = 20, .pci_ops = { .map_bus = pci_ecam_map_bus, .read = smp8759_config_read, diff --git a/drivers/pci/controller/pcie-xilinx-nwl.c b/drivers/pci/controller/pcie-xilinx-nwl.c index f3cf7d61924f..7f29c2fdcd51 100644 --- a/drivers/pci/controller/pcie-xilinx-nwl.c +++ b/drivers/pci/controller/pcie-xilinx-nwl.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #include @@ -124,8 +125,6 @@ #define E_ECAM_CR_ENABLE BIT(0) #define E_ECAM_SIZE_LOC GENMASK(20, 16) #define E_ECAM_SIZE_SHIFT 16 -#define ECAM_BUS_LOC_SHIFT 20 -#define ECAM_DEV_LOC_SHIFT 12 #define NWL_ECAM_VALUE_DEFAULT 12 #define CFG_DMA_REG_BAR GENMASK(2, 0) @@ -240,15 +239,11 @@ static void __iomem *nwl_pcie_map_bus(struct pci_bus *bus, unsigned int devfn, int where) { struct nwl_pcie *pcie = bus->sysdata; - int relbus; if (!nwl_pcie_valid_device(bus, devfn)) return NULL; - relbus = (bus->number << ECAM_BUS_LOC_SHIFT) | - (devfn << ECAM_DEV_LOC_SHIFT); - - return pcie->ecam_base + relbus + where; + return pcie->ecam_base + PCIE_ECAM_OFFSET(bus->number, devfn, where); } /* PCIe operations */ diff --git a/drivers/pci/controller/pcie-xilinx.c b/drivers/pci/controller/pcie-xilinx.c index 8523be61bba5..fa5baeb82653 100644 --- a/drivers/pci/controller/pcie-xilinx.c +++ b/drivers/pci/controller/pcie-xilinx.c @@ -21,6 +21,7 @@ #include #include #include +#include #include #include "../pci.h" @@ -86,10 +87,6 @@ /* Phy Status/Control Register definitions */ #define XILINX_PCIE_REG_PSCR_LNKUP BIT(11) -/* ECAM definitions */ -#define ECAM_BUS_NUM_SHIFT 20 -#define ECAM_DEV_NUM_SHIFT 12 - /* Number of MSI IRQs */ #define XILINX_NUM_MSI_IRQS 128 @@ -183,15 +180,11 @@ static void __iomem *xilinx_pcie_map_bus(struct pci_bus *bus, unsigned int devfn, int where) { struct xilinx_pcie_port *port = bus->sysdata; - int relbus; if (!xilinx_pcie_valid_device(bus, devfn)) return NULL; - relbus = (bus->number << ECAM_BUS_NUM_SHIFT) | - (devfn << ECAM_DEV_NUM_SHIFT); - - return port->reg_base + relbus + where; + return port->reg_base + PCIE_ECAM_OFFSET(bus->number, devfn, where); } /* PCIe operations */ diff --git a/drivers/pci/controller/vmd.c b/drivers/pci/controller/vmd.c index f375c21ceeb1..1361a79bd1e7 100644 --- a/drivers/pci/controller/vmd.c +++ b/drivers/pci/controller/vmd.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -328,15 +329,13 @@ static void vmd_remove_irq_domain(struct vmd_dev *vmd) static char __iomem *vmd_cfg_addr(struct vmd_dev *vmd, struct pci_bus *bus, unsigned int devfn, int reg, int len) { - char __iomem *addr = vmd->cfgbar + - ((bus->number - vmd->busn_start) << 20) + - (devfn << 12) + reg; + unsigned int busnr_ecam = bus->number - vmd->busn_start; + u32 offset = PCIE_ECAM_OFFSET(busnr_ecam, devfn, reg); - if ((addr - vmd->cfgbar) + len >= - resource_size(&vmd->dev->resource[VMD_CFGBAR])) + if (offset + len >= resource_size(&vmd->dev->resource[VMD_CFGBAR])) return NULL; - return addr; + return vmd->cfgbar + offset; } /* diff --git a/drivers/pci/ecam.c b/drivers/pci/ecam.c index b54d32a31669..59f91d434859 100644 --- a/drivers/pci/ecam.c +++ b/drivers/pci/ecam.c @@ -131,25 +131,36 @@ void __iomem *pci_ecam_map_bus(struct pci_bus *bus, unsigned int devfn, int where) { struct pci_config_window *cfg = bus->sysdata; + unsigned int bus_shift = cfg->ops->bus_shift; unsigned int devfn_shift = cfg->ops->bus_shift - 8; unsigned int busn = bus->number; void __iomem *base; + u32 bus_offset, devfn_offset; if (busn < cfg->busr.start || busn > cfg->busr.end) return NULL; busn -= cfg->busr.start; - if (per_bus_mapping) + if (per_bus_mapping) { base = cfg->winp[busn]; - else - base = cfg->win + (busn << cfg->ops->bus_shift); - return base + (devfn << devfn_shift) + where; + busn = 0; + } else + base = cfg->win; + + if (cfg->ops->bus_shift) { + bus_offset = (busn & PCIE_ECAM_BUS_MASK) << bus_shift; + devfn_offset = (devfn & PCIE_ECAM_DEVFN_MASK) << devfn_shift; + where &= PCIE_ECAM_REG_MASK; + + return base + (bus_offset | devfn_offset | where); + } + + return base + PCIE_ECAM_OFFSET(busn, devfn, where); } EXPORT_SYMBOL_GPL(pci_ecam_map_bus); /* ECAM ops */ const struct pci_ecam_ops pci_generic_ecam_ops = { - .bus_shift = 20, .pci_ops = { .map_bus = pci_ecam_map_bus, .read = pci_generic_config_read, @@ -161,7 +172,6 @@ EXPORT_SYMBOL_GPL(pci_generic_ecam_ops); #if defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS) /* ECAM ops for 32-bit access only (non-compliant) */ const struct pci_ecam_ops pci_32b_ops = { - .bus_shift = 20, .pci_ops = { .map_bus = pci_ecam_map_bus, .read = pci_generic_config_read32, @@ -171,7 +181,6 @@ const struct pci_ecam_ops pci_32b_ops = { /* ECAM ops for 32-bit read only (non-compliant) */ const struct pci_ecam_ops pci_32b_read_ops = { - .bus_shift = 20, .pci_ops = { .map_bus = pci_ecam_map_bus, .read = pci_generic_config_read32, diff --git a/include/linux/pci-ecam.h b/include/linux/pci-ecam.h index 033ce74f02e8..65d3d83015c3 100644 --- a/include/linux/pci-ecam.h +++ b/include/linux/pci-ecam.h @@ -9,6 +9,33 @@ #include #include +/* + * Memory address shift values for the byte-level address that + * can be used when accessing the PCI Express Configuration Space. + */ + +/* + * Enhanced Configuration Access Mechanism (ECAM) + * + * See PCI Express Base Specification, Revision 5.0, Version 1.0, + * Section 7.2.2, Table 7-1, p. 677. + */ +#define PCIE_ECAM_BUS_SHIFT 20 /* Bus number */ +#define PCIE_ECAM_DEVFN_SHIFT 12 /* Device and Function number */ + +#define PCIE_ECAM_BUS_MASK 0xff +#define PCIE_ECAM_DEVFN_MASK 0xff +#define PCIE_ECAM_REG_MASK 0xfff /* Limit offset to a maximum of 4K */ + +#define PCIE_ECAM_BUS(x) (((x) & PCIE_ECAM_BUS_MASK) << PCIE_ECAM_BUS_SHIFT) +#define PCIE_ECAM_DEVFN(x) (((x) & PCIE_ECAM_DEVFN_MASK) << PCIE_ECAM_DEVFN_SHIFT) +#define PCIE_ECAM_REG(x) ((x) & PCIE_ECAM_REG_MASK) + +#define PCIE_ECAM_OFFSET(bus, devfn, where) \ + (PCIE_ECAM_BUS(bus) | \ + PCIE_ECAM_DEVFN(devfn) | \ + PCIE_ECAM_REG(where)) + /* * struct to hold pci ops and bus shift of the config window * for a PCI controller. -- 2.29.2 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.2 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, 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Content-Transfer-Encoding: base64 Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org QWRkIEVDQU0tcmVsYXRlZCBjb25zdGFudHMgdG8gcHJvdmlkZSBhIHNldCBvZiBzdGFuZGFyZCBj b25zdGFudHMKZGVmaW5pbmcgbWVtb3J5IGFkZHJlc3Mgc2hpZnQgdmFsdWVzIHRvIHRoZSBieXRl LWxldmVsIGFkZHJlc3MgdGhhdCBjYW4KYmUgdXNlZCB0byBhY2Nlc3MgdGhlIFBDSSBFeHByZXNz IENvbmZpZ3VyYXRpb24gU3BhY2UsIGFuZCB0aGVuIG1vdmUKbmF0aXZlIFBDSSBFeHByZXNzIGNv bnRyb2xsZXIgZHJpdmVycyB0byB1c2UgdGhlIG5ld2x5IGludHJvZHVjZWQKZGVmaW5pdGlvbnMg cmV0aXJpbmcgZHJpdmVyLXNwZWNpZmljIG9uZXMuCgpSZWZhY3RvciBwY2lfZWNhbV9tYXBfYnVz KCkgZnVuY3Rpb24gdG8gdXNlIG5ld2x5IGFkZGVkIGNvbnN0YW50cyBzbwp0aGF0IGxpbWl0cyB0 byB0aGUgYnVzLCBkZXZpY2UgZnVuY3Rpb24gYW5kIG9mZnNldCAobm93IGxpbWl0ZWQgdG8gNEsg YXMKcGVyIHRoZSBzcGVjaWZpY2F0aW9uKSBhcmUgaW4gcGxhY2UgdG8gcHJldmVudCB0aGUgZGVm ZWN0aXZlIG9yCm1hbGljaW91cyBjYWxsZXIgZnJvbSBzdXBwbHlpbmcgaW5jb3JyZWN0IGNvbmZp Z3VyYXRpb24gb2Zmc2V0IGFuZCB0aHVzCnRhcmdldGluZyB0aGUgd3JvbmcgZGV2aWNlIHdoZW4g YWNjZXNzaW5nIGV4dGVuZGVkIGNvbmZpZ3VyYXRpb24gc3BhY2UuClRoaXMgcmVmYWN0b3IgYWxz byBhbGxvd3MgZm9yIHRoZSAiLmJ1c19zaGl0IiBpbml0aWFsaXNlcnMgdG8gYmUgZHJvcHBlZAp3 aGVuIHRoZSB1c2VyIGlzIG5vdCB1c2luZyBhIGN1c3RvbSB2YWx1ZSBhcyBhIGRlZmF1bHQgdmFs dWUgd2lsbCBiZQp1c2VkIGFzIHBlciB0aGUgUENJIEV4cHJlc3MgU3BlY2lmaWNhdGlvbi4KClN1 Z2dlc3RlZC1ieTogQmpvcm4gSGVsZ2FhcyA8YmhlbGdhYXNAZ29vZ2xlLmNvbT4KU2lnbmVkLW9m Zi1ieTogS3J6eXN6dG9mIFdpbGN6ecWEc2tpIDxrd0BsaW51eC5jb20+Ci0tLQogZHJpdmVycy9w Y2kvY29udHJvbGxlci9kd2MvcGNpZS1hbC5jICAgICAgICB8IDEyICsrLS0tLS0tLQogZHJpdmVy cy9wY2kvY29udHJvbGxlci9kd2MvcGNpZS1oaXNpLmMgICAgICB8ICAyIC0tCiBkcml2ZXJzL3Bj aS9jb250cm9sbGVyL3BjaS1hYXJkdmFyay5jICAgICAgIHwgMTMgKysrLS0tLS0tLQogZHJpdmVy cy9wY2kvY29udHJvbGxlci9wY2ktaG9zdC1nZW5lcmljLmMgICB8ICAxIC0KIGRyaXZlcnMvcGNp L2NvbnRyb2xsZXIvcGNpLXRodW5kZXItZWNhbS5jICAgfCAgMSAtCiBkcml2ZXJzL3BjaS9jb250 cm9sbGVyL3BjaWUtYnJjbXN0Yi5jICAgICAgIHwgMTYgKystLS0tLS0tLS0tCiBkcml2ZXJzL3Bj aS9jb250cm9sbGVyL3BjaWUtcm9ja2NoaXAtaG9zdC5jIHwgMjcgKysrKysrKysrKy0tLS0tLS0t LS0tCiBkcml2ZXJzL3BjaS9jb250cm9sbGVyL3BjaWUtcm9ja2NoaXAuaCAgICAgIHwgIDggKy0t LS0tCiBkcml2ZXJzL3BjaS9jb250cm9sbGVyL3BjaWUtdGFuZ28uYyAgICAgICAgIHwgIDEgLQog ZHJpdmVycy9wY2kvY29udHJvbGxlci9wY2llLXhpbGlueC1ud2wuYyAgICB8ICA5ICsrLS0tLS0K IGRyaXZlcnMvcGNpL2NvbnRyb2xsZXIvcGNpZS14aWxpbnguYyAgICAgICAgfCAxMSArKy0tLS0t LS0KIGRyaXZlcnMvcGNpL2NvbnRyb2xsZXIvdm1kLmMgICAgICAgICAgICAgICAgfCAxMSArKysr LS0tLS0KIGRyaXZlcnMvcGNpL2VjYW0uYyAgICAgICAgICAgICAgICAgICAgICAgICAgfCAyMyAr KysrKysrKysrKystLS0tLS0KIGluY2x1ZGUvbGludXgvcGNpLWVjYW0uaCAgICAgICAgICAgICAg ICAgICAgfCAyNyArKysrKysrKysrKysrKysrKysrKysKIDE0IGZpbGVzIGNoYW5nZWQsIDczIGlu c2VydGlvbnMoKyksIDg5IGRlbGV0aW9ucygtKQoKZGlmZiAtLWdpdCBhL2RyaXZlcnMvcGNpL2Nv bnRyb2xsZXIvZHdjL3BjaWUtYWwuYyBiL2RyaXZlcnMvcGNpL2NvbnRyb2xsZXIvZHdjL3BjaWUt YWwuYwppbmRleCBmOTczZmJjYTkwY2YuLmFmOWU1MWFiMWFmOCAxMDA2NDQKLS0tIGEvZHJpdmVy cy9wY2kvY29udHJvbGxlci9kd2MvcGNpZS1hbC5jCisrKyBiL2RyaXZlcnMvcGNpL2NvbnRyb2xs ZXIvZHdjL3BjaWUtYWwuYwpAQCAtNzYsNyArNzYsNiBAQCBzdGF0aWMgaW50IGFsX3BjaWVfaW5p dChzdHJ1Y3QgcGNpX2NvbmZpZ193aW5kb3cgKmNmZykKIH0KIAogY29uc3Qgc3RydWN0IHBjaV9l Y2FtX29wcyBhbF9wY2llX29wcyA9IHsKLQkuYnVzX3NoaWZ0ICAgID0gMjAsCiAJLmluaXQgICAg ICAgICA9ICBhbF9wY2llX2luaXQsCiAJLnBjaV9vcHMgICAgICA9IHsKIAkJLm1hcF9idXMgICAg PSBhbF9wY2llX21hcF9idXMsCkBAIC0xMzgsOCArMTM3LDYgQEAgc3RydWN0IGFsX3BjaWUgewog CXN0cnVjdCBhbF9wY2llX3RhcmdldF9idXNfY2ZnIHRhcmdldF9idXNfY2ZnOwogfTsKIAotI2Rl ZmluZSBQQ0lFX0VDQU1fREVWRk4oeCkJCSgoKHgpICYgMHhmZikgPDwgMTIpCi0KICNkZWZpbmUg dG9fYWxfcGNpZSh4KQkJZGV2X2dldF9kcnZkYXRhKCh4KS0+ZGV2KQogCiBzdGF0aWMgaW5saW5l IHUzMiBhbF9wY2llX2NvbnRyb2xsZXJfcmVhZGwoc3RydWN0IGFsX3BjaWUgKnBjaWUsIHUzMiBv ZmZzZXQpCkBAIC0yMjYsMTEgKzIyMyw2IEBAIHN0YXRpYyB2b2lkIF9faW9tZW0gKmFsX3BjaWVf Y29uZl9hZGRyX21hcF9idXMoc3RydWN0IHBjaV9idXMgKmJ1cywKIAlzdHJ1Y3QgYWxfcGNpZV90 YXJnZXRfYnVzX2NmZyAqdGFyZ2V0X2J1c19jZmcgPSAmcGNpZS0+dGFyZ2V0X2J1c19jZmc7CiAJ dW5zaWduZWQgaW50IGJ1c25yX2VjYW0gPSBidXNuciAmIHRhcmdldF9idXNfY2ZnLT5lY2FtX21h c2s7CiAJdW5zaWduZWQgaW50IGJ1c25yX3JlZyA9IGJ1c25yICYgdGFyZ2V0X2J1c19jZmctPnJl Z19tYXNrOwotCXZvaWQgX19pb21lbSAqcGNpX2Jhc2VfYWRkcjsKLQotCXBjaV9iYXNlX2FkZHIg PSAodm9pZCBfX2lvbWVtICopKCh1aW50cHRyX3QpcHAtPnZhX2NmZzBfYmFzZSArCi0JCQkJCSAo YnVzbnJfZWNhbSA8PCAyMCkgKwotCQkJCQkgUENJRV9FQ0FNX0RFVkZOKGRldmZuKSk7CiAKIAlp ZiAoYnVzbnJfcmVnICE9IHRhcmdldF9idXNfY2ZnLT5yZWdfdmFsKSB7CiAJCWRldl9kYmcocGNp ZS0+cGNpLT5kZXYsICJDaGFuZ2luZyB0YXJnZXQgYnVzIGJ1c251bSB2YWwgZnJvbSAweCV4IHRv IDB4JXhcbiIsCkBAIC0yNDEsNyArMjMzLDcgQEAgc3RhdGljIHZvaWQgX19pb21lbSAqYWxfcGNp ZV9jb25mX2FkZHJfbWFwX2J1cyhzdHJ1Y3QgcGNpX2J1cyAqYnVzLAogCQkJCSAgICAgICB0YXJn ZXRfYnVzX2NmZy0+cmVnX21hc2spOwogCX0KIAotCXJldHVybiBwY2lfYmFzZV9hZGRyICsgd2hl cmU7CisJcmV0dXJuIHBwLT52YV9jZmcwX2Jhc2UgKyBQQ0lFX0VDQU1fT0ZGU0VUKGJ1c25yX2Vj YW0sIGRldmZuLCB3aGVyZSk7CiB9CiAKIHN0YXRpYyBzdHJ1Y3QgcGNpX29wcyBhbF9jaGlsZF9w Y2lfb3BzID0gewpAQCAtMjY0LDcgKzI1Niw3IEBAIHN0YXRpYyB2b2lkIGFsX3BjaWVfY29uZmln X3ByZXBhcmUoc3RydWN0IGFsX3BjaWUgKnBjaWUpCiAKIAl0YXJnZXRfYnVzX2NmZyA9ICZwY2ll LT50YXJnZXRfYnVzX2NmZzsKIAotCWVjYW1fYnVzX21hc2sgPSAocGNpZS0+ZWNhbV9zaXplID4+ IDIwKSAtIDE7CisJZWNhbV9idXNfbWFzayA9IChwY2llLT5lY2FtX3NpemUgPj4gUENJRV9FQ0FN X0JVU19TSElGVCkgLSAxOwogCWlmIChlY2FtX2J1c19tYXNrID4gMjU1KSB7CiAJCWRldl93YXJu KHBjaWUtPmRldiwgIkVDQU0gd2luZG93IHNpemUgaXMgbGFyZ2VyIHRoYW4gMjU2TUIuIEN1dHRp bmcgb2ZmIGF0IDI1NlxuIik7CiAJCWVjYW1fYnVzX21hc2sgPSAyNTU7CmRpZmYgLS1naXQgYS9k cml2ZXJzL3BjaS9jb250cm9sbGVyL2R3Yy9wY2llLWhpc2kuYyBiL2RyaXZlcnMvcGNpL2NvbnRy b2xsZXIvZHdjL3BjaWUtaGlzaS5jCmluZGV4IDVjYTg2Nzk2ZDQzYS4uOGZjNTk2MGZhZjI4IDEw MDY0NAotLS0gYS9kcml2ZXJzL3BjaS9jb250cm9sbGVyL2R3Yy9wY2llLWhpc2kuYworKysgYi9k cml2ZXJzL3BjaS9jb250cm9sbGVyL2R3Yy9wY2llLWhpc2kuYwpAQCAtMTAwLDcgKzEwMCw2IEBA IHN0YXRpYyBpbnQgaGlzaV9wY2llX2luaXQoc3RydWN0IHBjaV9jb25maWdfd2luZG93ICpjZmcp CiB9CiAKIGNvbnN0IHN0cnVjdCBwY2lfZWNhbV9vcHMgaGlzaV9wY2llX29wcyA9IHsKLQkuYnVz X3NoaWZ0ICAgID0gMjAsCiAJLmluaXQgICAgICAgICA9ICBoaXNpX3BjaWVfaW5pdCwKIAkucGNp X29wcyAgICAgID0gewogCQkubWFwX2J1cyAgICA9IGhpc2lfcGNpZV9tYXBfYnVzLApAQCAtMTM1 LDcgKzEzNCw2IEBAIHN0YXRpYyBpbnQgaGlzaV9wY2llX3BsYXRmb3JtX2luaXQoc3RydWN0IHBj aV9jb25maWdfd2luZG93ICpjZmcpCiB9CiAKIHN0YXRpYyBjb25zdCBzdHJ1Y3QgcGNpX2VjYW1f b3BzIGhpc2lfcGNpZV9wbGF0Zm9ybV9vcHMgPSB7Ci0JLmJ1c19zaGlmdCAgICA9IDIwLAogCS5p bml0ICAgICAgICAgPSAgaGlzaV9wY2llX3BsYXRmb3JtX2luaXQsCiAJLnBjaV9vcHMgICAgICA9 IHsKIAkJLm1hcF9idXMgICAgPSBoaXNpX3BjaWVfbWFwX2J1cywKZGlmZiAtLWdpdCBhL2RyaXZl cnMvcGNpL2NvbnRyb2xsZXIvcGNpLWFhcmR2YXJrLmMgYi9kcml2ZXJzL3BjaS9jb250cm9sbGVy L3BjaS1hYXJkdmFyay5jCmluZGV4IDBiZTQ4NWEyNTMyNy4uMTA0M2U1NGM3M2JkIDEwMDY0NAot LS0gYS9kcml2ZXJzL3BjaS9jb250cm9sbGVyL3BjaS1hYXJkdmFyay5jCisrKyBiL2RyaXZlcnMv cGNpL2NvbnRyb2xsZXIvcGNpLWFhcmR2YXJrLmMKQEAgLTE2LDYgKzE2LDcgQEAKICNpbmNsdWRl IDxsaW51eC9rZXJuZWwuaD4KICNpbmNsdWRlIDxsaW51eC9tb2R1bGUuaD4KICNpbmNsdWRlIDxs aW51eC9wY2kuaD4KKyNpbmNsdWRlIDxsaW51eC9wY2ktZWNhbS5oPgogI2luY2x1ZGUgPGxpbnV4 L2luaXQuaD4KICNpbmNsdWRlIDxsaW51eC9waHkvcGh5Lmg+CiAjaW5jbHVkZSA8bGludXgvcGxh dGZvcm1fZGV2aWNlLmg+CkBAIC0xNjQsMTQgKzE2NSw2IEBACiAjZGVmaW5lIFBDSUVfQ09ORklH X1dSX1RZUEUwCQkJMHhhCiAjZGVmaW5lIFBDSUVfQ09ORklHX1dSX1RZUEUxCQkJMHhiCiAKLSNk ZWZpbmUgUENJRV9DT05GX0JVUyhidXMpCQkJKCgoYnVzKSAmIDB4ZmYpIDw8IDIwKQotI2RlZmlu ZSBQQ0lFX0NPTkZfREVWKGRldikJCQkoKChkZXYpICYgMHgxZikgPDwgMTUpCi0jZGVmaW5lIFBD SUVfQ09ORl9GVU5DKGZ1bikJCQkoKChmdW4pICYgMHg3KQk8PCAxMikKLSNkZWZpbmUgUENJRV9D T05GX1JFRyhyZWcpCQkJKChyZWcpICYgMHhmZmMpCi0jZGVmaW5lIFBDSUVfQ09ORl9BRERSKGJ1 cywgZGV2Zm4sIHdoZXJlKQlcCi0JKFBDSUVfQ09ORl9CVVMoYnVzKSB8IFBDSUVfQ09ORl9ERVYo UENJX1NMT1QoZGV2Zm4pKQl8IFwKLQkgUENJRV9DT05GX0ZVTkMoUENJX0ZVTkMoZGV2Zm4pKSB8 IFBDSUVfQ09ORl9SRUcod2hlcmUpKQotCiAjZGVmaW5lIFBJT19SRVRSWV9DTlQJCQk1MDAKICNk ZWZpbmUgUElPX1JFVFJZX0RFTEFZCQkJMiAvKiAyIHVzKi8KIApAQCAtNjg3LDcgKzY4MCw3IEBA IHN0YXRpYyBpbnQgYWR2a19wY2llX3JkX2NvbmYoc3RydWN0IHBjaV9idXMgKmJ1cywgdTMyIGRl dmZuLAogCWFkdmtfd3JpdGVsKHBjaWUsIHJlZywgUElPX0NUUkwpOwogCiAJLyogUHJvZ3JhbSB0 aGUgYWRkcmVzcyByZWdpc3RlcnMgKi8KLQlyZWcgPSBQQ0lFX0NPTkZfQUREUihidXMtPm51bWJl ciwgZGV2Zm4sIHdoZXJlKTsKKwlyZWcgPSBBTElHTl9ET1dOKFBDSUVfRUNBTV9PRkZTRVQoYnVz LT5udW1iZXIsIGRldmZuLCB3aGVyZSksIDQpOwogCWFkdmtfd3JpdGVsKHBjaWUsIHJlZywgUElP X0FERFJfTFMpOwogCWFkdmtfd3JpdGVsKHBjaWUsIDAsIFBJT19BRERSX01TKTsKIApAQCAtNzQ4 LDcgKzc0MSw3IEBAIHN0YXRpYyBpbnQgYWR2a19wY2llX3dyX2NvbmYoc3RydWN0IHBjaV9idXMg KmJ1cywgdTMyIGRldmZuLAogCWFkdmtfd3JpdGVsKHBjaWUsIHJlZywgUElPX0NUUkwpOwogCiAJ LyogUHJvZ3JhbSB0aGUgYWRkcmVzcyByZWdpc3RlcnMgKi8KLQlyZWcgPSBQQ0lFX0NPTkZfQURE UihidXMtPm51bWJlciwgZGV2Zm4sIHdoZXJlKTsKKwlyZWcgPSBBTElHTl9ET1dOKFBDSUVfRUNB TV9PRkZTRVQoYnVzLT5udW1iZXIsIGRldmZuLCB3aGVyZSksIDQpOwogCWFkdmtfd3JpdGVsKHBj aWUsIHJlZywgUElPX0FERFJfTFMpOwogCWFkdmtfd3JpdGVsKHBjaWUsIDAsIFBJT19BRERSX01T KTsKIApkaWZmIC0tZ2l0IGEvZHJpdmVycy9wY2kvY29udHJvbGxlci9wY2ktaG9zdC1nZW5lcmlj LmMgYi9kcml2ZXJzL3BjaS9jb250cm9sbGVyL3BjaS1ob3N0LWdlbmVyaWMuYwppbmRleCBiNTE5 NzdhYmZkZjEuLjYzODY1YWViNjM2YiAxMDA2NDQKLS0tIGEvZHJpdmVycy9wY2kvY29udHJvbGxl ci9wY2ktaG9zdC1nZW5lcmljLmMKKysrIGIvZHJpdmVycy9wY2kvY29udHJvbGxlci9wY2ktaG9z dC1nZW5lcmljLmMKQEAgLTQ5LDcgKzQ5LDYgQEAgc3RhdGljIHZvaWQgX19pb21lbSAqcGNpX2R3 X2VjYW1fbWFwX2J1cyhzdHJ1Y3QgcGNpX2J1cyAqYnVzLAogfQogCiBzdGF0aWMgY29uc3Qgc3Ry dWN0IHBjaV9lY2FtX29wcyBwY2lfZHdfZWNhbV9idXNfb3BzID0gewotCS5idXNfc2hpZnQJPSAy MCwKIAkucGNpX29wcwk9IHsKIAkJLm1hcF9idXMJPSBwY2lfZHdfZWNhbV9tYXBfYnVzLAogCQku cmVhZAkJPSBwY2lfZ2VuZXJpY19jb25maWdfcmVhZCwKZGlmZiAtLWdpdCBhL2RyaXZlcnMvcGNp L2NvbnRyb2xsZXIvcGNpLXRodW5kZXItZWNhbS5jIGIvZHJpdmVycy9wY2kvY29udHJvbGxlci9w Y2ktdGh1bmRlci1lY2FtLmMKaW5kZXggN2U4ODM1ZmVlNWY3Li5mOTY0ZmQyNmY3ZTAgMTAwNjQ0 Ci0tLSBhL2RyaXZlcnMvcGNpL2NvbnRyb2xsZXIvcGNpLXRodW5kZXItZWNhbS5jCisrKyBiL2Ry aXZlcnMvcGNpL2NvbnRyb2xsZXIvcGNpLXRodW5kZXItZWNhbS5jCkBAIC0zNDYsNyArMzQ2LDYg QEAgc3RhdGljIGludCB0aHVuZGVyX2VjYW1fY29uZmlnX3dyaXRlKHN0cnVjdCBwY2lfYnVzICpi dXMsIHVuc2lnbmVkIGludCBkZXZmbiwKIH0KIAogY29uc3Qgc3RydWN0IHBjaV9lY2FtX29wcyBw Y2lfdGh1bmRlcl9lY2FtX29wcyA9IHsKLQkuYnVzX3NoaWZ0CT0gMjAsCiAJLnBjaV9vcHMJPSB7 CiAJCS5tYXBfYnVzICAgICAgICA9IHBjaV9lY2FtX21hcF9idXMsCiAJCS5yZWFkICAgICAgICAg ICA9IHRodW5kZXJfZWNhbV9jb25maWdfcmVhZCwKZGlmZiAtLWdpdCBhL2RyaXZlcnMvcGNpL2Nv bnRyb2xsZXIvcGNpZS1icmNtc3RiLmMgYi9kcml2ZXJzL3BjaS9jb250cm9sbGVyL3BjaWUtYnJj bXN0Yi5jCmluZGV4IGJlYTg2ODk5YmQ1ZC4uN2ZjODBmZDZmMTNmIDEwMDY0NAotLS0gYS9kcml2 ZXJzL3BjaS9jb250cm9sbGVyL3BjaWUtYnJjbXN0Yi5jCisrKyBiL2RyaXZlcnMvcGNpL2NvbnRy b2xsZXIvcGNpZS1icmNtc3RiLmMKQEAgLTIyLDYgKzIyLDcgQEAKICNpbmNsdWRlIDxsaW51eC9v Zl9wY2kuaD4KICNpbmNsdWRlIDxsaW51eC9vZl9wbGF0Zm9ybS5oPgogI2luY2x1ZGUgPGxpbnV4 L3BjaS5oPgorI2luY2x1ZGUgPGxpbnV4L3BjaS1lY2FtLmg+CiAjaW5jbHVkZSA8bGludXgvcHJp bnRrLmg+CiAjaW5jbHVkZSA8bGludXgvcmVzZXQuaD4KICNpbmNsdWRlIDxsaW51eC9zaXplcy5o PgpAQCAtMTI3LDExICsxMjgsNyBAQAogI2RlZmluZSAgTVNJX0lOVF9NQVNLX0NMUgkJMHgxNAog CiAjZGVmaW5lIFBDSUVfRVhUX0NGR19EQVRBCQkJCTB4ODAwMAotCiAjZGVmaW5lIFBDSUVfRVhU X0NGR19JTkRFWAkJCQkweDkwMDAKLSNkZWZpbmUgIFBDSUVfRVhUX0JVU05VTV9TSElGVAkJCQky MAotI2RlZmluZSAgUENJRV9FWFRfU0xPVF9TSElGVAkJCQkxNQotI2RlZmluZSAgUENJRV9FWFRf RlVOQ19TSElGVAkJCQkxMgogCiAjZGVmaW5lICBQQ0lFX1JHUjFfU1dfSU5JVF8xX1BFUlNUX01B U0sJCQkweDEKICNkZWZpbmUgIFBDSUVfUkdSMV9TV19JTklUXzFfUEVSU1RfU0hJRlQJCTB4MApA QCAtNjk1LDE1ICs2OTIsNiBAQCBzdGF0aWMgYm9vbCBicmNtX3BjaWVfbGlua191cChzdHJ1Y3Qg YnJjbV9wY2llICpwY2llKQogCXJldHVybiBkbGEgJiYgcGx1OwogfQogCi0vKiBDb25maWd1cmF0 aW9uIHNwYWNlIHJlYWQvd3JpdGUgc3VwcG9ydCAqLwotc3RhdGljIGlubGluZSBpbnQgYnJjbV9w Y2llX2NmZ19pbmRleChpbnQgYnVzbnIsIGludCBkZXZmbiwgaW50IHJlZykKLXsKLQlyZXR1cm4g KChQQ0lfU0xPVChkZXZmbikgJiAweDFmKSA8PCBQQ0lFX0VYVF9TTE9UX1NISUZUKQotCQl8ICgo UENJX0ZVTkMoZGV2Zm4pICYgMHgwNykgPDwgUENJRV9FWFRfRlVOQ19TSElGVCkKLQkJfCAoYnVz bnIgPDwgUENJRV9FWFRfQlVTTlVNX1NISUZUKQotCQl8IChyZWcgJiB+Myk7Ci19Ci0KIHN0YXRp YyB2b2lkIF9faW9tZW0gKmJyY21fcGNpZV9tYXBfY29uZihzdHJ1Y3QgcGNpX2J1cyAqYnVzLCB1 bnNpZ25lZCBpbnQgZGV2Zm4sCiAJCQkJCWludCB3aGVyZSkKIHsKQEAgLTcxNiw3ICs3MDQsNyBA QCBzdGF0aWMgdm9pZCBfX2lvbWVtICpicmNtX3BjaWVfbWFwX2NvbmYoc3RydWN0IHBjaV9idXMg KmJ1cywgdW5zaWduZWQgaW50IGRldmZuLAogCQlyZXR1cm4gUENJX1NMT1QoZGV2Zm4pID8gTlVM TCA6IGJhc2UgKyB3aGVyZTsKIAogCS8qIEZvciBkZXZpY2VzLCB3cml0ZSB0byB0aGUgY29uZmln IHNwYWNlIGluZGV4IHJlZ2lzdGVyICovCi0JaWR4ID0gYnJjbV9wY2llX2NmZ19pbmRleChidXMt Pm51bWJlciwgZGV2Zm4sIDApOworCWlkeCA9IFBDSUVfRUNBTV9PRkZTRVQoYnVzLT5udW1iZXIs IGRldmZuLCAwKTsKIAl3cml0ZWwoaWR4LCBwY2llLT5iYXNlICsgUENJRV9FWFRfQ0ZHX0lOREVY KTsKIAlyZXR1cm4gYmFzZSArIFBDSUVfRVhUX0NGR19EQVRBICsgd2hlcmU7CiB9CmRpZmYgLS1n aXQgYS9kcml2ZXJzL3BjaS9jb250cm9sbGVyL3BjaWUtcm9ja2NoaXAtaG9zdC5jIGIvZHJpdmVy cy9wY2kvY29udHJvbGxlci9wY2llLXJvY2tjaGlwLWhvc3QuYwppbmRleCA5NzA1MDU5NTIzYTYu LmYxZDA4YTFiMTU5MSAxMDA2NDQKLS0tIGEvZHJpdmVycy9wY2kvY29udHJvbGxlci9wY2llLXJv Y2tjaGlwLWhvc3QuYworKysgYi9kcml2ZXJzL3BjaS9jb250cm9sbGVyL3BjaWUtcm9ja2NoaXAt aG9zdC5jCkBAIC0xNTcsMTIgKzE1NywxMSBAQCBzdGF0aWMgaW50IHJvY2tjaGlwX3BjaWVfcmRf b3RoZXJfY29uZihzdHJ1Y3Qgcm9ja2NoaXBfcGNpZSAqcm9ja2NoaXAsCiAJCQkJICAgICAgIHN0 cnVjdCBwY2lfYnVzICpidXMsIHUzMiBkZXZmbiwKIAkJCQkgICAgICAgaW50IHdoZXJlLCBpbnQg c2l6ZSwgdTMyICp2YWwpCiB7Ci0JdTMyIGJ1c2RldjsKKwl2b2lkIF9faW9tZW0gKmFkZHI7CiAK LQlidXNkZXYgPSBQQ0lFX0VDQU1fQUREUihidXMtPm51bWJlciwgUENJX1NMT1QoZGV2Zm4pLAot CQkJCVBDSV9GVU5DKGRldmZuKSwgd2hlcmUpOworCWFkZHIgPSByb2NrY2hpcC0+cmVnX2Jhc2Ug KyBQQ0lFX0VDQU1fT0ZGU0VUKGJ1cy0+bnVtYmVyLCBkZXZmbiwgd2hlcmUpOwogCi0JaWYgKCFJ U19BTElHTkVEKGJ1c2Rldiwgc2l6ZSkpIHsKKwlpZiAoIUlTX0FMSUdORUQoKHVpbnRwdHJfdClh ZGRyLCBzaXplKSkgewogCQkqdmFsID0gMDsKIAkJcmV0dXJuIFBDSUJJT1NfQkFEX1JFR0lTVEVS X05VTUJFUjsKIAl9CkBAIC0xNzUsMTEgKzE3NCwxMSBAQCBzdGF0aWMgaW50IHJvY2tjaGlwX3Bj aWVfcmRfb3RoZXJfY29uZihzdHJ1Y3Qgcm9ja2NoaXBfcGNpZSAqcm9ja2NoaXAsCiAJCQkJCQlB WElfV1JBUFBFUl9UWVBFMV9DRkcpOwogCiAJaWYgKHNpemUgPT0gNCkgewotCQkqdmFsID0gcmVh ZGwocm9ja2NoaXAtPnJlZ19iYXNlICsgYnVzZGV2KTsKKwkJKnZhbCA9IHJlYWRsKGFkZHIpOwog CX0gZWxzZSBpZiAoc2l6ZSA9PSAyKSB7Ci0JCSp2YWwgPSByZWFkdyhyb2NrY2hpcC0+cmVnX2Jh c2UgKyBidXNkZXYpOworCQkqdmFsID0gcmVhZHcoYWRkcik7CiAJfSBlbHNlIGlmIChzaXplID09 IDEpIHsKLQkJKnZhbCA9IHJlYWRiKHJvY2tjaGlwLT5yZWdfYmFzZSArIGJ1c2Rldik7CisJCSp2 YWwgPSByZWFkYihhZGRyKTsKIAl9IGVsc2UgewogCQkqdmFsID0gMDsKIAkJcmV0dXJuIFBDSUJJ T1NfQkFEX1JFR0lTVEVSX05VTUJFUjsKQEAgLTE5MSwxMSArMTkwLDExIEBAIHN0YXRpYyBpbnQg cm9ja2NoaXBfcGNpZV93cl9vdGhlcl9jb25mKHN0cnVjdCByb2NrY2hpcF9wY2llICpyb2NrY2hp cCwKIAkJCQkgICAgICAgc3RydWN0IHBjaV9idXMgKmJ1cywgdTMyIGRldmZuLAogCQkJCSAgICAg ICBpbnQgd2hlcmUsIGludCBzaXplLCB1MzIgdmFsKQogewotCXUzMiBidXNkZXY7CisJdm9pZCBf X2lvbWVtICphZGRyOwogCi0JYnVzZGV2ID0gUENJRV9FQ0FNX0FERFIoYnVzLT5udW1iZXIsIFBD SV9TTE9UKGRldmZuKSwKLQkJCQlQQ0lfRlVOQyhkZXZmbiksIHdoZXJlKTsKLQlpZiAoIUlTX0FM SUdORUQoYnVzZGV2LCBzaXplKSkKKwlhZGRyID0gcm9ja2NoaXAtPnJlZ19iYXNlICsgUENJRV9F Q0FNX09GRlNFVChidXMtPm51bWJlciwgZGV2Zm4sIHdoZXJlKTsKKworCWlmICghSVNfQUxJR05F RCgodWludHB0cl90KWFkZHIsIHNpemUpKQogCQlyZXR1cm4gUENJQklPU19CQURfUkVHSVNURVJf TlVNQkVSOwogCiAJaWYgKHBjaV9pc19yb290X2J1cyhidXMtPnBhcmVudCkpCkBAIC0yMDYsMTEg KzIwNSwxMSBAQCBzdGF0aWMgaW50IHJvY2tjaGlwX3BjaWVfd3Jfb3RoZXJfY29uZihzdHJ1Y3Qg cm9ja2NoaXBfcGNpZSAqcm9ja2NoaXAsCiAJCQkJCQlBWElfV1JBUFBFUl9UWVBFMV9DRkcpOwog CiAJaWYgKHNpemUgPT0gNCkKLQkJd3JpdGVsKHZhbCwgcm9ja2NoaXAtPnJlZ19iYXNlICsgYnVz ZGV2KTsKKwkJd3JpdGVsKHZhbCwgYWRkcik7CiAJZWxzZSBpZiAoc2l6ZSA9PSAyKQotCQl3cml0 ZXcodmFsLCByb2NrY2hpcC0+cmVnX2Jhc2UgKyBidXNkZXYpOworCQl3cml0ZXcodmFsLCBhZGRy KTsKIAllbHNlIGlmIChzaXplID09IDEpCi0JCXdyaXRlYih2YWwsIHJvY2tjaGlwLT5yZWdfYmFz ZSArIGJ1c2Rldik7CisJCXdyaXRlYih2YWwsIGFkZHIpOwogCWVsc2UKIAkJcmV0dXJuIFBDSUJJ T1NfQkFEX1JFR0lTVEVSX05VTUJFUjsKIApkaWZmIC0tZ2l0IGEvZHJpdmVycy9wY2kvY29udHJv bGxlci9wY2llLXJvY2tjaGlwLmggYi9kcml2ZXJzL3BjaS9jb250cm9sbGVyL3BjaWUtcm9ja2No aXAuaAppbmRleCBjN2QwMTc4ZmM4YzIuLjE2NTBhNTA4NzQ1MCAxMDA2NDQKLS0tIGEvZHJpdmVy cy9wY2kvY29udHJvbGxlci9wY2llLXJvY2tjaGlwLmgKKysrIGIvZHJpdmVycy9wY2kvY29udHJv bGxlci9wY2llLXJvY2tjaGlwLmgKQEAgLTEzLDYgKzEzLDcgQEAKIAogI2luY2x1ZGUgPGxpbnV4 L2tlcm5lbC5oPgogI2luY2x1ZGUgPGxpbnV4L3BjaS5oPgorI2luY2x1ZGUgPGxpbnV4L3BjaS1l Y2FtLmg+CiAKIC8qCiAgKiBUaGUgdXBwZXIgMTYgYml0cyBvZiBQQ0lFX0NMSUVOVF9DT05GSUcg YXJlIGEgd3JpdGUgbWFzayBmb3IgdGhlIGxvd2VyIDE2CkBAIC0xNzgsMTMgKzE3OSw2IEBACiAj ZGVmaW5lIE1JTl9BWElfQUREUl9CSVRTX1BBU1NFRAkJOAogI2RlZmluZSBQQ0lFX1JDX1NFTkRf UE1FX09GRgkJCTB4MTE5NjAKICNkZWZpbmUgUk9DS0NISVBfVkVORE9SX0lECQkJMHgxZDg3Ci0j ZGVmaW5lIFBDSUVfRUNBTV9CVVMoeCkJCQkoKCh4KSAmIDB4ZmYpIDw8IDIwKQotI2RlZmluZSBQ Q0lFX0VDQU1fREVWKHgpCQkJKCgoeCkgJiAweDFmKSA8PCAxNSkKLSNkZWZpbmUgUENJRV9FQ0FN X0ZVTkMoeCkJCQkoKCh4KSAmIDB4NykgPDwgMTIpCi0jZGVmaW5lIFBDSUVfRUNBTV9SRUcoeCkJ CQkoKCh4KSAmIDB4ZmZmKSA8PCAwKQotI2RlZmluZSBQQ0lFX0VDQU1fQUREUihidXMsIGRldiwg ZnVuYywgcmVnKSBcCi0JICAoUENJRV9FQ0FNX0JVUyhidXMpIHwgUENJRV9FQ0FNX0RFVihkZXYp IHwgXAotCSAgIFBDSUVfRUNBTV9GVU5DKGZ1bmMpIHwgUENJRV9FQ0FNX1JFRyhyZWcpKQogI2Rl ZmluZSBQQ0lFX0xJTktfSVNfTDIoeCkgXAogCSgoKHgpICYgUENJRV9DTElFTlRfREVCVUdfTFRT U01fTUFTSykgPT0gUENJRV9DTElFTlRfREVCVUdfTFRTU01fTDIpCiAjZGVmaW5lIFBDSUVfTElO S19VUCh4KSBcCmRpZmYgLS1naXQgYS9kcml2ZXJzL3BjaS9jb250cm9sbGVyL3BjaWUtdGFuZ28u YyBiL2RyaXZlcnMvcGNpL2NvbnRyb2xsZXIvcGNpZS10YW5nby5jCmluZGV4IGQwOTNhOGNlNGJi MS4uNjJhMDYxZjFkNjJlIDEwMDY0NAotLS0gYS9kcml2ZXJzL3BjaS9jb250cm9sbGVyL3BjaWUt dGFuZ28uYworKysgYi9kcml2ZXJzL3BjaS9jb250cm9sbGVyL3BjaWUtdGFuZ28uYwpAQCAtMjA4 LDcgKzIwOCw2IEBAIHN0YXRpYyBpbnQgc21wODc1OV9jb25maWdfd3JpdGUoc3RydWN0IHBjaV9i dXMgKmJ1cywgdW5zaWduZWQgaW50IGRldmZuLAogfQogCiBzdGF0aWMgY29uc3Qgc3RydWN0IHBj aV9lY2FtX29wcyBzbXA4NzU5X2VjYW1fb3BzID0gewotCS5idXNfc2hpZnQJPSAyMCwKIAkucGNp X29wcwk9IHsKIAkJLm1hcF9idXMJPSBwY2lfZWNhbV9tYXBfYnVzLAogCQkucmVhZAkJPSBzbXA4 NzU5X2NvbmZpZ19yZWFkLApkaWZmIC0tZ2l0IGEvZHJpdmVycy9wY2kvY29udHJvbGxlci9wY2ll LXhpbGlueC1ud2wuYyBiL2RyaXZlcnMvcGNpL2NvbnRyb2xsZXIvcGNpZS14aWxpbngtbndsLmMK aW5kZXggZjNjZjdkNjE5MjRmLi43ZjI5YzJmZGNkNTEgMTAwNjQ0Ci0tLSBhL2RyaXZlcnMvcGNp L2NvbnRyb2xsZXIvcGNpZS14aWxpbngtbndsLmMKKysrIGIvZHJpdmVycy9wY2kvY29udHJvbGxl ci9wY2llLXhpbGlueC1ud2wuYwpAQCAtMTgsNiArMTgsNyBAQAogI2luY2x1ZGUgPGxpbnV4L29m X3BsYXRmb3JtLmg+CiAjaW5jbHVkZSA8bGludXgvb2ZfaXJxLmg+CiAjaW5jbHVkZSA8bGludXgv cGNpLmg+CisjaW5jbHVkZSA8bGludXgvcGNpLWVjYW0uaD4KICNpbmNsdWRlIDxsaW51eC9wbGF0 Zm9ybV9kZXZpY2UuaD4KICNpbmNsdWRlIDxsaW51eC9pcnFjaGlwL2NoYWluZWRfaXJxLmg+CiAK QEAgLTEyNCw4ICsxMjUsNiBAQAogI2RlZmluZSBFX0VDQU1fQ1JfRU5BQkxFCQlCSVQoMCkKICNk ZWZpbmUgRV9FQ0FNX1NJWkVfTE9DCQkJR0VOTUFTSygyMCwgMTYpCiAjZGVmaW5lIEVfRUNBTV9T SVpFX1NISUZUCQkxNgotI2RlZmluZSBFQ0FNX0JVU19MT0NfU0hJRlQJCTIwCi0jZGVmaW5lIEVD QU1fREVWX0xPQ19TSElGVAkJMTIKICNkZWZpbmUgTldMX0VDQU1fVkFMVUVfREVGQVVMVAkJMTIK IAogI2RlZmluZSBDRkdfRE1BX1JFR19CQVIJCQlHRU5NQVNLKDIsIDApCkBAIC0yNDAsMTUgKzIz OSwxMSBAQCBzdGF0aWMgdm9pZCBfX2lvbWVtICpud2xfcGNpZV9tYXBfYnVzKHN0cnVjdCBwY2lf YnVzICpidXMsIHVuc2lnbmVkIGludCBkZXZmbiwKIAkJCQkgICAgICBpbnQgd2hlcmUpCiB7CiAJ c3RydWN0IG53bF9wY2llICpwY2llID0gYnVzLT5zeXNkYXRhOwotCWludCByZWxidXM7CiAKIAlp ZiAoIW53bF9wY2llX3ZhbGlkX2RldmljZShidXMsIGRldmZuKSkKIAkJcmV0dXJuIE5VTEw7CiAK LQlyZWxidXMgPSAoYnVzLT5udW1iZXIgPDwgRUNBTV9CVVNfTE9DX1NISUZUKSB8Ci0JCQkoZGV2 Zm4gPDwgRUNBTV9ERVZfTE9DX1NISUZUKTsKLQotCXJldHVybiBwY2llLT5lY2FtX2Jhc2UgKyBy ZWxidXMgKyB3aGVyZTsKKwlyZXR1cm4gcGNpZS0+ZWNhbV9iYXNlICsgUENJRV9FQ0FNX09GRlNF VChidXMtPm51bWJlciwgZGV2Zm4sIHdoZXJlKTsKIH0KIAogLyogUENJZSBvcGVyYXRpb25zICov CmRpZmYgLS1naXQgYS9kcml2ZXJzL3BjaS9jb250cm9sbGVyL3BjaWUteGlsaW54LmMgYi9kcml2 ZXJzL3BjaS9jb250cm9sbGVyL3BjaWUteGlsaW54LmMKaW5kZXggODUyM2JlNjFiYmE1Li5mYTVi YWViODI2NTMgMTAwNjQ0Ci0tLSBhL2RyaXZlcnMvcGNpL2NvbnRyb2xsZXIvcGNpZS14aWxpbngu YworKysgYi9kcml2ZXJzL3BjaS9jb250cm9sbGVyL3BjaWUteGlsaW54LmMKQEAgLTIxLDYgKzIx LDcgQEAKICNpbmNsdWRlIDxsaW51eC9vZl9wbGF0Zm9ybS5oPgogI2luY2x1ZGUgPGxpbnV4L29m X2lycS5oPgogI2luY2x1ZGUgPGxpbnV4L3BjaS5oPgorI2luY2x1ZGUgPGxpbnV4L3BjaS1lY2Ft Lmg+CiAjaW5jbHVkZSA8bGludXgvcGxhdGZvcm1fZGV2aWNlLmg+CiAKICNpbmNsdWRlICIuLi9w Y2kuaCIKQEAgLTg2LDEwICs4Nyw2IEBACiAvKiBQaHkgU3RhdHVzL0NvbnRyb2wgUmVnaXN0ZXIg ZGVmaW5pdGlvbnMgKi8KICNkZWZpbmUgWElMSU5YX1BDSUVfUkVHX1BTQ1JfTE5LVVAJQklUKDEx KQogCi0vKiBFQ0FNIGRlZmluaXRpb25zICovCi0jZGVmaW5lIEVDQU1fQlVTX05VTV9TSElGVAkJ MjAKLSNkZWZpbmUgRUNBTV9ERVZfTlVNX1NISUZUCQkxMgotCiAvKiBOdW1iZXIgb2YgTVNJIElS UXMgKi8KICNkZWZpbmUgWElMSU5YX05VTV9NU0lfSVJRUwkJMTI4CiAKQEAgLTE4MywxNSArMTgw LDExIEBAIHN0YXRpYyB2b2lkIF9faW9tZW0gKnhpbGlueF9wY2llX21hcF9idXMoc3RydWN0IHBj aV9idXMgKmJ1cywKIAkJCQkJIHVuc2lnbmVkIGludCBkZXZmbiwgaW50IHdoZXJlKQogewogCXN0 cnVjdCB4aWxpbnhfcGNpZV9wb3J0ICpwb3J0ID0gYnVzLT5zeXNkYXRhOwotCWludCByZWxidXM7 CiAKIAlpZiAoIXhpbGlueF9wY2llX3ZhbGlkX2RldmljZShidXMsIGRldmZuKSkKIAkJcmV0dXJu IE5VTEw7CiAKLQlyZWxidXMgPSAoYnVzLT5udW1iZXIgPDwgRUNBTV9CVVNfTlVNX1NISUZUKSB8 Ci0JCSAoZGV2Zm4gPDwgRUNBTV9ERVZfTlVNX1NISUZUKTsKLQotCXJldHVybiBwb3J0LT5yZWdf YmFzZSArIHJlbGJ1cyArIHdoZXJlOworCXJldHVybiBwb3J0LT5yZWdfYmFzZSArIFBDSUVfRUNB TV9PRkZTRVQoYnVzLT5udW1iZXIsIGRldmZuLCB3aGVyZSk7CiB9CiAKIC8qIFBDSWUgb3BlcmF0 aW9ucyAqLwpkaWZmIC0tZ2l0IGEvZHJpdmVycy9wY2kvY29udHJvbGxlci92bWQuYyBiL2RyaXZl cnMvcGNpL2NvbnRyb2xsZXIvdm1kLmMKaW5kZXggZjM3NWMyMWNlZWIxLi4xMzYxYTc5YmQxZTcg MTAwNjQ0Ci0tLSBhL2RyaXZlcnMvcGNpL2NvbnRyb2xsZXIvdm1kLmMKKysrIGIvZHJpdmVycy9w Y2kvY29udHJvbGxlci92bWQuYwpAQCAtMTEsNiArMTEsNyBAQAogI2luY2x1ZGUgPGxpbnV4L21v ZHVsZS5oPgogI2luY2x1ZGUgPGxpbnV4L21zaS5oPgogI2luY2x1ZGUgPGxpbnV4L3BjaS5oPgor I2luY2x1ZGUgPGxpbnV4L3BjaS1lY2FtLmg+CiAjaW5jbHVkZSA8bGludXgvc3JjdS5oPgogI2lu Y2x1ZGUgPGxpbnV4L3JjdWxpc3QuaD4KICNpbmNsdWRlIDxsaW51eC9yY3VwZGF0ZS5oPgpAQCAt MzI4LDE1ICszMjksMTMgQEAgc3RhdGljIHZvaWQgdm1kX3JlbW92ZV9pcnFfZG9tYWluKHN0cnVj dCB2bWRfZGV2ICp2bWQpCiBzdGF0aWMgY2hhciBfX2lvbWVtICp2bWRfY2ZnX2FkZHIoc3RydWN0 IHZtZF9kZXYgKnZtZCwgc3RydWN0IHBjaV9idXMgKmJ1cywKIAkJCQkgIHVuc2lnbmVkIGludCBk ZXZmbiwgaW50IHJlZywgaW50IGxlbikKIHsKLQljaGFyIF9faW9tZW0gKmFkZHIgPSB2bWQtPmNm Z2JhciArCi0JCQkgICAgICgoYnVzLT5udW1iZXIgLSB2bWQtPmJ1c25fc3RhcnQpIDw8IDIwKSAr Ci0JCQkgICAgIChkZXZmbiA8PCAxMikgKyByZWc7CisJdW5zaWduZWQgaW50IGJ1c25yX2VjYW0g PSBidXMtPm51bWJlciAtIHZtZC0+YnVzbl9zdGFydDsKKwl1MzIgb2Zmc2V0ID0gUENJRV9FQ0FN X09GRlNFVChidXNucl9lY2FtLCBkZXZmbiwgcmVnKTsKIAotCWlmICgoYWRkciAtIHZtZC0+Y2Zn YmFyKSArIGxlbiA+PQotCSAgICByZXNvdXJjZV9zaXplKCZ2bWQtPmRldi0+cmVzb3VyY2VbVk1E X0NGR0JBUl0pKQorCWlmIChvZmZzZXQgKyBsZW4gPj0gcmVzb3VyY2Vfc2l6ZSgmdm1kLT5kZXYt PnJlc291cmNlW1ZNRF9DRkdCQVJdKSkKIAkJcmV0dXJuIE5VTEw7CiAKLQlyZXR1cm4gYWRkcjsK KwlyZXR1cm4gdm1kLT5jZmdiYXIgKyBvZmZzZXQ7CiB9CiAKIC8qCmRpZmYgLS1naXQgYS9kcml2 ZXJzL3BjaS9lY2FtLmMgYi9kcml2ZXJzL3BjaS9lY2FtLmMKaW5kZXggYjU0ZDMyYTMxNjY5Li41 OWY5MWQ0MzQ4NTkgMTAwNjQ0Ci0tLSBhL2RyaXZlcnMvcGNpL2VjYW0uYworKysgYi9kcml2ZXJz L3BjaS9lY2FtLmMKQEAgLTEzMSwyNSArMTMxLDM2IEBAIHZvaWQgX19pb21lbSAqcGNpX2VjYW1f bWFwX2J1cyhzdHJ1Y3QgcGNpX2J1cyAqYnVzLCB1bnNpZ25lZCBpbnQgZGV2Zm4sCiAJCQkgICAg ICAgaW50IHdoZXJlKQogewogCXN0cnVjdCBwY2lfY29uZmlnX3dpbmRvdyAqY2ZnID0gYnVzLT5z eXNkYXRhOworCXVuc2lnbmVkIGludCBidXNfc2hpZnQgPSBjZmctPm9wcy0+YnVzX3NoaWZ0Owog CXVuc2lnbmVkIGludCBkZXZmbl9zaGlmdCA9IGNmZy0+b3BzLT5idXNfc2hpZnQgLSA4OwogCXVu c2lnbmVkIGludCBidXNuID0gYnVzLT5udW1iZXI7CiAJdm9pZCBfX2lvbWVtICpiYXNlOworCXUz MiBidXNfb2Zmc2V0LCBkZXZmbl9vZmZzZXQ7CiAKIAlpZiAoYnVzbiA8IGNmZy0+YnVzci5zdGFy dCB8fCBidXNuID4gY2ZnLT5idXNyLmVuZCkKIAkJcmV0dXJuIE5VTEw7CiAKIAlidXNuIC09IGNm Zy0+YnVzci5zdGFydDsKLQlpZiAocGVyX2J1c19tYXBwaW5nKQorCWlmIChwZXJfYnVzX21hcHBp bmcpIHsKIAkJYmFzZSA9IGNmZy0+d2lucFtidXNuXTsKLQllbHNlCi0JCWJhc2UgPSBjZmctPndp biArIChidXNuIDw8IGNmZy0+b3BzLT5idXNfc2hpZnQpOwotCXJldHVybiBiYXNlICsgKGRldmZu IDw8IGRldmZuX3NoaWZ0KSArIHdoZXJlOworCQlidXNuID0gMDsKKwl9IGVsc2UKKwkJYmFzZSA9 IGNmZy0+d2luOworCisJaWYgKGNmZy0+b3BzLT5idXNfc2hpZnQpIHsKKwkJYnVzX29mZnNldCA9 IChidXNuICYgUENJRV9FQ0FNX0JVU19NQVNLKSA8PCBidXNfc2hpZnQ7CisJCWRldmZuX29mZnNl dCA9IChkZXZmbiAmIFBDSUVfRUNBTV9ERVZGTl9NQVNLKSA8PCBkZXZmbl9zaGlmdDsKKwkJd2hl cmUgJj0gUENJRV9FQ0FNX1JFR19NQVNLOworCisJCXJldHVybiBiYXNlICsgKGJ1c19vZmZzZXQg fCBkZXZmbl9vZmZzZXQgfCB3aGVyZSk7CisJfQorCisJcmV0dXJuIGJhc2UgKyBQQ0lFX0VDQU1f T0ZGU0VUKGJ1c24sIGRldmZuLCB3aGVyZSk7CiB9CiBFWFBPUlRfU1lNQk9MX0dQTChwY2lfZWNh bV9tYXBfYnVzKTsKIAogLyogRUNBTSBvcHMgKi8KIGNvbnN0IHN0cnVjdCBwY2lfZWNhbV9vcHMg cGNpX2dlbmVyaWNfZWNhbV9vcHMgPSB7Ci0JLmJ1c19zaGlmdAk9IDIwLAogCS5wY2lfb3BzCT0g ewogCQkubWFwX2J1cwk9IHBjaV9lY2FtX21hcF9idXMsCiAJCS5yZWFkCQk9IHBjaV9nZW5lcmlj X2NvbmZpZ19yZWFkLApAQCAtMTYxLDcgKzE3Miw2IEBAIEVYUE9SVF9TWU1CT0xfR1BMKHBjaV9n ZW5lcmljX2VjYW1fb3BzKTsKICNpZiBkZWZpbmVkKENPTkZJR19BQ1BJKSAmJiBkZWZpbmVkKENP TkZJR19QQ0lfUVVJUktTKQogLyogRUNBTSBvcHMgZm9yIDMyLWJpdCBhY2Nlc3Mgb25seSAobm9u LWNvbXBsaWFudCkgKi8KIGNvbnN0IHN0cnVjdCBwY2lfZWNhbV9vcHMgcGNpXzMyYl9vcHMgPSB7 Ci0JLmJ1c19zaGlmdAk9IDIwLAogCS5wY2lfb3BzCT0gewogCQkubWFwX2J1cwk9IHBjaV9lY2Ft X21hcF9idXMsCiAJCS5yZWFkCQk9IHBjaV9nZW5lcmljX2NvbmZpZ19yZWFkMzIsCkBAIC0xNzEs NyArMTgxLDYgQEAgY29uc3Qgc3RydWN0IHBjaV9lY2FtX29wcyBwY2lfMzJiX29wcyA9IHsKIAog LyogRUNBTSBvcHMgZm9yIDMyLWJpdCByZWFkIG9ubHkgKG5vbi1jb21wbGlhbnQpICovCiBjb25z dCBzdHJ1Y3QgcGNpX2VjYW1fb3BzIHBjaV8zMmJfcmVhZF9vcHMgPSB7Ci0JLmJ1c19zaGlmdAk9 IDIwLAogCS5wY2lfb3BzCT0gewogCQkubWFwX2J1cwk9IHBjaV9lY2FtX21hcF9idXMsCiAJCS5y ZWFkCQk9IHBjaV9nZW5lcmljX2NvbmZpZ19yZWFkMzIsCmRpZmYgLS1naXQgYS9pbmNsdWRlL2xp bnV4L3BjaS1lY2FtLmggYi9pbmNsdWRlL2xpbnV4L3BjaS1lY2FtLmgKaW5kZXggMDMzY2U3NGYw MmU4Li42NWQzZDgzMDE1YzMgMTAwNjQ0Ci0tLSBhL2luY2x1ZGUvbGludXgvcGNpLWVjYW0uaAor KysgYi9pbmNsdWRlL2xpbnV4L3BjaS1lY2FtLmgKQEAgLTksNiArOSwzMyBAQAogI2luY2x1ZGUg PGxpbnV4L2tlcm5lbC5oPgogI2luY2x1ZGUgPGxpbnV4L3BsYXRmb3JtX2RldmljZS5oPgogCisv KgorICogTWVtb3J5IGFkZHJlc3Mgc2hpZnQgdmFsdWVzIGZvciB0aGUgYnl0ZS1sZXZlbCBhZGRy ZXNzIHRoYXQKKyAqIGNhbiBiZSB1c2VkIHdoZW4gYWNjZXNzaW5nIHRoZSBQQ0kgRXhwcmVzcyBD b25maWd1cmF0aW9uIFNwYWNlLgorICovCisKKy8qCisgKiBFbmhhbmNlZCBDb25maWd1cmF0aW9u IEFjY2VzcyBNZWNoYW5pc20gKEVDQU0pCisgKgorICogU2VlIFBDSSBFeHByZXNzIEJhc2UgU3Bl Y2lmaWNhdGlvbiwgUmV2aXNpb24gNS4wLCBWZXJzaW9uIDEuMCwKKyAqIFNlY3Rpb24gNy4yLjIs IFRhYmxlIDctMSwgcC4gNjc3LgorICovCisjZGVmaW5lIFBDSUVfRUNBTV9CVVNfU0hJRlQJMjAg LyogQnVzIG51bWJlciAqLworI2RlZmluZSBQQ0lFX0VDQU1fREVWRk5fU0hJRlQJMTIgLyogRGV2 aWNlIGFuZCBGdW5jdGlvbiBudW1iZXIgKi8KKworI2RlZmluZSBQQ0lFX0VDQU1fQlVTX01BU0sJ MHhmZgorI2RlZmluZSBQQ0lFX0VDQU1fREVWRk5fTUFTSwkweGZmCisjZGVmaW5lIFBDSUVfRUNB TV9SRUdfTUFTSwkweGZmZiAvKiBMaW1pdCBvZmZzZXQgdG8gYSBtYXhpbXVtIG9mIDRLICovCisK KyNkZWZpbmUgUENJRV9FQ0FNX0JVUyh4KQkoKCh4KSAmIFBDSUVfRUNBTV9CVVNfTUFTSykgPDwg UENJRV9FQ0FNX0JVU19TSElGVCkKKyNkZWZpbmUgUENJRV9FQ0FNX0RFVkZOKHgpCSgoKHgpICYg UENJRV9FQ0FNX0RFVkZOX01BU0spIDw8IFBDSUVfRUNBTV9ERVZGTl9TSElGVCkKKyNkZWZpbmUg UENJRV9FQ0FNX1JFRyh4KQkoKHgpICYgUENJRV9FQ0FNX1JFR19NQVNLKQorCisjZGVmaW5lIFBD SUVfRUNBTV9PRkZTRVQoYnVzLCBkZXZmbiwgd2hlcmUpIFwKKwkoUENJRV9FQ0FNX0JVUyhidXMp IHwgXAorCSBQQ0lFX0VDQU1fREVWRk4oZGV2Zm4pIHwgXAorCSBQQ0lFX0VDQU1fUkVHKHdoZXJl KSkKKwogLyoKICAqIHN0cnVjdCB0byBob2xkIHBjaSBvcHMgYW5kIGJ1cyBzaGlmdCBvZiB0aGUg Y29uZmlnIHdpbmRvdwogICogZm9yIGEgUENJIGNvbnRyb2xsZXIuCi0tIAoyLjI5LjIKCgpfX19f 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linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Heiko Stuebner , Shawn Lin , Paul Mackerras , Thomas Petazzoni , Jonathan Chocron , Toan Le , Will Deacon , Rob Herring , Lorenzo Pieralisi , Michal Simek , linux-rockchip@lists.infradead.org, bcm-kernel-feedback-list@broadcom.com, Jonathan Derrick , linux-pci@vger.kernel.org, Ray Jui , Florian Fainelli , linux-rpi-kernel@lists.infradead.org, Jonathan Cameron , linux-arm-kernel@lists.infradead.org, Scott Branden , Zhou Wang , Robert Richter , linuxppc-dev@lists.ozlabs.org, Nicolas Saenz Julienne Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" Add ECAM-related constants to provide a set of standard constants defining memory address shift values to the byte-level address that can be used to access the PCI Express Configuration Space, and then move native PCI Express controller drivers to use the newly introduced definitions retiring driver-specific ones. Refactor pci_ecam_map_bus() function to use newly added constants so that limits to the bus, device function and offset (now limited to 4K as per the specification) are in place to prevent the defective or malicious caller from supplying incorrect configuration offset and thus targeting the wrong device when accessing extended configuration space. This refactor also allows for the ".bus_shit" initialisers to be dropped when the user is not using a custom value as a default value will be used as per the PCI Express Specification. Suggested-by: Bjorn Helgaas Signed-off-by: Krzysztof Wilczyński --- drivers/pci/controller/dwc/pcie-al.c | 12 ++------- drivers/pci/controller/dwc/pcie-hisi.c | 2 -- drivers/pci/controller/pci-aardvark.c | 13 +++------- drivers/pci/controller/pci-host-generic.c | 1 - drivers/pci/controller/pci-thunder-ecam.c | 1 - drivers/pci/controller/pcie-brcmstb.c | 16 ++---------- drivers/pci/controller/pcie-rockchip-host.c | 27 ++++++++++----------- drivers/pci/controller/pcie-rockchip.h | 8 +----- drivers/pci/controller/pcie-tango.c | 1 - drivers/pci/controller/pcie-xilinx-nwl.c | 9 ++----- drivers/pci/controller/pcie-xilinx.c | 11 ++------- drivers/pci/controller/vmd.c | 11 ++++----- drivers/pci/ecam.c | 23 ++++++++++++------ include/linux/pci-ecam.h | 27 +++++++++++++++++++++ 14 files changed, 73 insertions(+), 89 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-al.c b/drivers/pci/controller/dwc/pcie-al.c index f973fbca90cf..af9e51ab1af8 100644 --- a/drivers/pci/controller/dwc/pcie-al.c +++ b/drivers/pci/controller/dwc/pcie-al.c @@ -76,7 +76,6 @@ static int al_pcie_init(struct pci_config_window *cfg) } const struct pci_ecam_ops al_pcie_ops = { - .bus_shift = 20, .init = al_pcie_init, .pci_ops = { .map_bus = al_pcie_map_bus, @@ -138,8 +137,6 @@ struct al_pcie { struct al_pcie_target_bus_cfg target_bus_cfg; }; -#define PCIE_ECAM_DEVFN(x) (((x) & 0xff) << 12) - #define to_al_pcie(x) dev_get_drvdata((x)->dev) static inline u32 al_pcie_controller_readl(struct al_pcie *pcie, u32 offset) @@ -226,11 +223,6 @@ static void __iomem *al_pcie_conf_addr_map_bus(struct pci_bus *bus, struct al_pcie_target_bus_cfg *target_bus_cfg = &pcie->target_bus_cfg; unsigned int busnr_ecam = busnr & target_bus_cfg->ecam_mask; unsigned int busnr_reg = busnr & target_bus_cfg->reg_mask; - void __iomem *pci_base_addr; - - pci_base_addr = (void __iomem *)((uintptr_t)pp->va_cfg0_base + - (busnr_ecam << 20) + - PCIE_ECAM_DEVFN(devfn)); if (busnr_reg != target_bus_cfg->reg_val) { dev_dbg(pcie->pci->dev, "Changing target bus busnum val from 0x%x to 0x%x\n", @@ -241,7 +233,7 @@ static void __iomem *al_pcie_conf_addr_map_bus(struct pci_bus *bus, target_bus_cfg->reg_mask); } - return pci_base_addr + where; + return pp->va_cfg0_base + PCIE_ECAM_OFFSET(busnr_ecam, devfn, where); } static struct pci_ops al_child_pci_ops = { @@ -264,7 +256,7 @@ static void al_pcie_config_prepare(struct al_pcie *pcie) target_bus_cfg = &pcie->target_bus_cfg; - ecam_bus_mask = (pcie->ecam_size >> 20) - 1; + ecam_bus_mask = (pcie->ecam_size >> PCIE_ECAM_BUS_SHIFT) - 1; if (ecam_bus_mask > 255) { dev_warn(pcie->dev, "ECAM window size is larger than 256MB. Cutting off at 256\n"); ecam_bus_mask = 255; diff --git a/drivers/pci/controller/dwc/pcie-hisi.c b/drivers/pci/controller/dwc/pcie-hisi.c index 5ca86796d43a..8fc5960faf28 100644 --- a/drivers/pci/controller/dwc/pcie-hisi.c +++ b/drivers/pci/controller/dwc/pcie-hisi.c @@ -100,7 +100,6 @@ static int hisi_pcie_init(struct pci_config_window *cfg) } const struct pci_ecam_ops hisi_pcie_ops = { - .bus_shift = 20, .init = hisi_pcie_init, .pci_ops = { .map_bus = hisi_pcie_map_bus, @@ -135,7 +134,6 @@ static int hisi_pcie_platform_init(struct pci_config_window *cfg) } static const struct pci_ecam_ops hisi_pcie_platform_ops = { - .bus_shift = 20, .init = hisi_pcie_platform_init, .pci_ops = { .map_bus = hisi_pcie_map_bus, diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c index 0be485a25327..1043e54c73bd 100644 --- a/drivers/pci/controller/pci-aardvark.c +++ b/drivers/pci/controller/pci-aardvark.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include #include @@ -164,14 +165,6 @@ #define PCIE_CONFIG_WR_TYPE0 0xa #define PCIE_CONFIG_WR_TYPE1 0xb -#define PCIE_CONF_BUS(bus) (((bus) & 0xff) << 20) -#define PCIE_CONF_DEV(dev) (((dev) & 0x1f) << 15) -#define PCIE_CONF_FUNC(fun) (((fun) & 0x7) << 12) -#define PCIE_CONF_REG(reg) ((reg) & 0xffc) -#define PCIE_CONF_ADDR(bus, devfn, where) \ - (PCIE_CONF_BUS(bus) | PCIE_CONF_DEV(PCI_SLOT(devfn)) | \ - PCIE_CONF_FUNC(PCI_FUNC(devfn)) | PCIE_CONF_REG(where)) - #define PIO_RETRY_CNT 500 #define PIO_RETRY_DELAY 2 /* 2 us*/ @@ -687,7 +680,7 @@ static int advk_pcie_rd_conf(struct pci_bus *bus, u32 devfn, advk_writel(pcie, reg, PIO_CTRL); /* Program the address registers */ - reg = PCIE_CONF_ADDR(bus->number, devfn, where); + reg = ALIGN_DOWN(PCIE_ECAM_OFFSET(bus->number, devfn, where), 4); advk_writel(pcie, reg, PIO_ADDR_LS); advk_writel(pcie, 0, PIO_ADDR_MS); @@ -748,7 +741,7 @@ static int advk_pcie_wr_conf(struct pci_bus *bus, u32 devfn, advk_writel(pcie, reg, PIO_CTRL); /* Program the address registers */ - reg = PCIE_CONF_ADDR(bus->number, devfn, where); + reg = ALIGN_DOWN(PCIE_ECAM_OFFSET(bus->number, devfn, where), 4); advk_writel(pcie, reg, PIO_ADDR_LS); advk_writel(pcie, 0, PIO_ADDR_MS); diff --git a/drivers/pci/controller/pci-host-generic.c b/drivers/pci/controller/pci-host-generic.c index b51977abfdf1..63865aeb636b 100644 --- a/drivers/pci/controller/pci-host-generic.c +++ b/drivers/pci/controller/pci-host-generic.c @@ -49,7 +49,6 @@ static void __iomem *pci_dw_ecam_map_bus(struct pci_bus *bus, } static const struct pci_ecam_ops pci_dw_ecam_bus_ops = { - .bus_shift = 20, .pci_ops = { .map_bus = pci_dw_ecam_map_bus, .read = pci_generic_config_read, diff --git a/drivers/pci/controller/pci-thunder-ecam.c b/drivers/pci/controller/pci-thunder-ecam.c index 7e8835fee5f7..f964fd26f7e0 100644 --- a/drivers/pci/controller/pci-thunder-ecam.c +++ b/drivers/pci/controller/pci-thunder-ecam.c @@ -346,7 +346,6 @@ static int thunder_ecam_config_write(struct pci_bus *bus, unsigned int devfn, } const struct pci_ecam_ops pci_thunder_ecam_ops = { - .bus_shift = 20, .pci_ops = { .map_bus = pci_ecam_map_bus, .read = thunder_ecam_config_read, diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c index bea86899bd5d..7fc80fd6f13f 100644 --- a/drivers/pci/controller/pcie-brcmstb.c +++ b/drivers/pci/controller/pcie-brcmstb.c @@ -22,6 +22,7 @@ #include #include #include +#include #include #include #include @@ -127,11 +128,7 @@ #define MSI_INT_MASK_CLR 0x14 #define PCIE_EXT_CFG_DATA 0x8000 - #define PCIE_EXT_CFG_INDEX 0x9000 -#define PCIE_EXT_BUSNUM_SHIFT 20 -#define PCIE_EXT_SLOT_SHIFT 15 -#define PCIE_EXT_FUNC_SHIFT 12 #define PCIE_RGR1_SW_INIT_1_PERST_MASK 0x1 #define PCIE_RGR1_SW_INIT_1_PERST_SHIFT 0x0 @@ -695,15 +692,6 @@ static bool brcm_pcie_link_up(struct brcm_pcie *pcie) return dla && plu; } -/* Configuration space read/write support */ -static inline int brcm_pcie_cfg_index(int busnr, int devfn, int reg) -{ - return ((PCI_SLOT(devfn) & 0x1f) << PCIE_EXT_SLOT_SHIFT) - | ((PCI_FUNC(devfn) & 0x07) << PCIE_EXT_FUNC_SHIFT) - | (busnr << PCIE_EXT_BUSNUM_SHIFT) - | (reg & ~3); -} - static void __iomem *brcm_pcie_map_conf(struct pci_bus *bus, unsigned int devfn, int where) { @@ -716,7 +704,7 @@ static void __iomem *brcm_pcie_map_conf(struct pci_bus *bus, unsigned int devfn, return PCI_SLOT(devfn) ? NULL : base + where; /* For devices, write to the config space index register */ - idx = brcm_pcie_cfg_index(bus->number, devfn, 0); + idx = PCIE_ECAM_OFFSET(bus->number, devfn, 0); writel(idx, pcie->base + PCIE_EXT_CFG_INDEX); return base + PCIE_EXT_CFG_DATA + where; } diff --git a/drivers/pci/controller/pcie-rockchip-host.c b/drivers/pci/controller/pcie-rockchip-host.c index 9705059523a6..f1d08a1b1591 100644 --- a/drivers/pci/controller/pcie-rockchip-host.c +++ b/drivers/pci/controller/pcie-rockchip-host.c @@ -157,12 +157,11 @@ static int rockchip_pcie_rd_other_conf(struct rockchip_pcie *rockchip, struct pci_bus *bus, u32 devfn, int where, int size, u32 *val) { - u32 busdev; + void __iomem *addr; - busdev = PCIE_ECAM_ADDR(bus->number, PCI_SLOT(devfn), - PCI_FUNC(devfn), where); + addr = rockchip->reg_base + PCIE_ECAM_OFFSET(bus->number, devfn, where); - if (!IS_ALIGNED(busdev, size)) { + if (!IS_ALIGNED((uintptr_t)addr, size)) { *val = 0; return PCIBIOS_BAD_REGISTER_NUMBER; } @@ -175,11 +174,11 @@ static int rockchip_pcie_rd_other_conf(struct rockchip_pcie *rockchip, AXI_WRAPPER_TYPE1_CFG); if (size == 4) { - *val = readl(rockchip->reg_base + busdev); + *val = readl(addr); } else if (size == 2) { - *val = readw(rockchip->reg_base + busdev); + *val = readw(addr); } else if (size == 1) { - *val = readb(rockchip->reg_base + busdev); + *val = readb(addr); } else { *val = 0; return PCIBIOS_BAD_REGISTER_NUMBER; @@ -191,11 +190,11 @@ static int rockchip_pcie_wr_other_conf(struct rockchip_pcie *rockchip, struct pci_bus *bus, u32 devfn, int where, int size, u32 val) { - u32 busdev; + void __iomem *addr; - busdev = PCIE_ECAM_ADDR(bus->number, PCI_SLOT(devfn), - PCI_FUNC(devfn), where); - if (!IS_ALIGNED(busdev, size)) + addr = rockchip->reg_base + PCIE_ECAM_OFFSET(bus->number, devfn, where); + + if (!IS_ALIGNED((uintptr_t)addr, size)) return PCIBIOS_BAD_REGISTER_NUMBER; if (pci_is_root_bus(bus->parent)) @@ -206,11 +205,11 @@ static int rockchip_pcie_wr_other_conf(struct rockchip_pcie *rockchip, AXI_WRAPPER_TYPE1_CFG); if (size == 4) - writel(val, rockchip->reg_base + busdev); + writel(val, addr); else if (size == 2) - writew(val, rockchip->reg_base + busdev); + writew(val, addr); else if (size == 1) - writeb(val, rockchip->reg_base + busdev); + writeb(val, addr); else return PCIBIOS_BAD_REGISTER_NUMBER; diff --git a/drivers/pci/controller/pcie-rockchip.h b/drivers/pci/controller/pcie-rockchip.h index c7d0178fc8c2..1650a5087450 100644 --- a/drivers/pci/controller/pcie-rockchip.h +++ b/drivers/pci/controller/pcie-rockchip.h @@ -13,6 +13,7 @@ #include #include +#include /* * The upper 16 bits of PCIE_CLIENT_CONFIG are a write mask for the lower 16 @@ -178,13 +179,6 @@ #define MIN_AXI_ADDR_BITS_PASSED 8 #define PCIE_RC_SEND_PME_OFF 0x11960 #define ROCKCHIP_VENDOR_ID 0x1d87 -#define PCIE_ECAM_BUS(x) (((x) & 0xff) << 20) -#define PCIE_ECAM_DEV(x) (((x) & 0x1f) << 15) -#define PCIE_ECAM_FUNC(x) (((x) & 0x7) << 12) -#define PCIE_ECAM_REG(x) (((x) & 0xfff) << 0) -#define PCIE_ECAM_ADDR(bus, dev, func, reg) \ - (PCIE_ECAM_BUS(bus) | PCIE_ECAM_DEV(dev) | \ - PCIE_ECAM_FUNC(func) | PCIE_ECAM_REG(reg)) #define PCIE_LINK_IS_L2(x) \ (((x) & PCIE_CLIENT_DEBUG_LTSSM_MASK) == PCIE_CLIENT_DEBUG_LTSSM_L2) #define PCIE_LINK_UP(x) \ diff --git a/drivers/pci/controller/pcie-tango.c b/drivers/pci/controller/pcie-tango.c index d093a8ce4bb1..62a061f1d62e 100644 --- a/drivers/pci/controller/pcie-tango.c +++ b/drivers/pci/controller/pcie-tango.c @@ -208,7 +208,6 @@ static int smp8759_config_write(struct pci_bus *bus, unsigned int devfn, } static const struct pci_ecam_ops smp8759_ecam_ops = { - .bus_shift = 20, .pci_ops = { .map_bus = pci_ecam_map_bus, .read = smp8759_config_read, diff --git a/drivers/pci/controller/pcie-xilinx-nwl.c b/drivers/pci/controller/pcie-xilinx-nwl.c index f3cf7d61924f..7f29c2fdcd51 100644 --- a/drivers/pci/controller/pcie-xilinx-nwl.c +++ b/drivers/pci/controller/pcie-xilinx-nwl.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #include @@ -124,8 +125,6 @@ #define E_ECAM_CR_ENABLE BIT(0) #define E_ECAM_SIZE_LOC GENMASK(20, 16) #define E_ECAM_SIZE_SHIFT 16 -#define ECAM_BUS_LOC_SHIFT 20 -#define ECAM_DEV_LOC_SHIFT 12 #define NWL_ECAM_VALUE_DEFAULT 12 #define CFG_DMA_REG_BAR GENMASK(2, 0) @@ -240,15 +239,11 @@ static void __iomem *nwl_pcie_map_bus(struct pci_bus *bus, unsigned int devfn, int where) { struct nwl_pcie *pcie = bus->sysdata; - int relbus; if (!nwl_pcie_valid_device(bus, devfn)) return NULL; - relbus = (bus->number << ECAM_BUS_LOC_SHIFT) | - (devfn << ECAM_DEV_LOC_SHIFT); - - return pcie->ecam_base + relbus + where; + return pcie->ecam_base + PCIE_ECAM_OFFSET(bus->number, devfn, where); } /* PCIe operations */ diff --git a/drivers/pci/controller/pcie-xilinx.c b/drivers/pci/controller/pcie-xilinx.c index 8523be61bba5..fa5baeb82653 100644 --- a/drivers/pci/controller/pcie-xilinx.c +++ b/drivers/pci/controller/pcie-xilinx.c @@ -21,6 +21,7 @@ #include #include #include +#include #include #include "../pci.h" @@ -86,10 +87,6 @@ /* Phy Status/Control Register definitions */ #define XILINX_PCIE_REG_PSCR_LNKUP BIT(11) -/* ECAM definitions */ -#define ECAM_BUS_NUM_SHIFT 20 -#define ECAM_DEV_NUM_SHIFT 12 - /* Number of MSI IRQs */ #define XILINX_NUM_MSI_IRQS 128 @@ -183,15 +180,11 @@ static void __iomem *xilinx_pcie_map_bus(struct pci_bus *bus, unsigned int devfn, int where) { struct xilinx_pcie_port *port = bus->sysdata; - int relbus; if (!xilinx_pcie_valid_device(bus, devfn)) return NULL; - relbus = (bus->number << ECAM_BUS_NUM_SHIFT) | - (devfn << ECAM_DEV_NUM_SHIFT); - - return port->reg_base + relbus + where; + return port->reg_base + PCIE_ECAM_OFFSET(bus->number, devfn, where); } /* PCIe operations */ diff --git a/drivers/pci/controller/vmd.c b/drivers/pci/controller/vmd.c index f375c21ceeb1..1361a79bd1e7 100644 --- a/drivers/pci/controller/vmd.c +++ b/drivers/pci/controller/vmd.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -328,15 +329,13 @@ static void vmd_remove_irq_domain(struct vmd_dev *vmd) static char __iomem *vmd_cfg_addr(struct vmd_dev *vmd, struct pci_bus *bus, unsigned int devfn, int reg, int len) { - char __iomem *addr = vmd->cfgbar + - ((bus->number - vmd->busn_start) << 20) + - (devfn << 12) + reg; + unsigned int busnr_ecam = bus->number - vmd->busn_start; + u32 offset = PCIE_ECAM_OFFSET(busnr_ecam, devfn, reg); - if ((addr - vmd->cfgbar) + len >= - resource_size(&vmd->dev->resource[VMD_CFGBAR])) + if (offset + len >= resource_size(&vmd->dev->resource[VMD_CFGBAR])) return NULL; - return addr; + return vmd->cfgbar + offset; } /* diff --git a/drivers/pci/ecam.c b/drivers/pci/ecam.c index b54d32a31669..59f91d434859 100644 --- a/drivers/pci/ecam.c +++ b/drivers/pci/ecam.c @@ -131,25 +131,36 @@ void __iomem *pci_ecam_map_bus(struct pci_bus *bus, unsigned int devfn, int where) { struct pci_config_window *cfg = bus->sysdata; + unsigned int bus_shift = cfg->ops->bus_shift; unsigned int devfn_shift = cfg->ops->bus_shift - 8; unsigned int busn = bus->number; void __iomem *base; + u32 bus_offset, devfn_offset; if (busn < cfg->busr.start || busn > cfg->busr.end) return NULL; busn -= cfg->busr.start; - if (per_bus_mapping) + if (per_bus_mapping) { base = cfg->winp[busn]; - else - base = cfg->win + (busn << cfg->ops->bus_shift); - return base + (devfn << devfn_shift) + where; + busn = 0; + } else + base = cfg->win; + + if (cfg->ops->bus_shift) { + bus_offset = (busn & PCIE_ECAM_BUS_MASK) << bus_shift; + devfn_offset = (devfn & PCIE_ECAM_DEVFN_MASK) << devfn_shift; + where &= PCIE_ECAM_REG_MASK; + + return base + (bus_offset | devfn_offset | where); + } + + return base + PCIE_ECAM_OFFSET(busn, devfn, where); } EXPORT_SYMBOL_GPL(pci_ecam_map_bus); /* ECAM ops */ const struct pci_ecam_ops pci_generic_ecam_ops = { - .bus_shift = 20, .pci_ops = { .map_bus = pci_ecam_map_bus, .read = pci_generic_config_read, @@ -161,7 +172,6 @@ EXPORT_SYMBOL_GPL(pci_generic_ecam_ops); #if defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS) /* ECAM ops for 32-bit access only (non-compliant) */ const struct pci_ecam_ops pci_32b_ops = { - .bus_shift = 20, .pci_ops = { .map_bus = pci_ecam_map_bus, .read = pci_generic_config_read32, @@ -171,7 +181,6 @@ const struct pci_ecam_ops pci_32b_ops = { /* ECAM ops for 32-bit read only (non-compliant) */ const struct pci_ecam_ops pci_32b_read_ops = { - .bus_shift = 20, .pci_ops = { .map_bus = pci_ecam_map_bus, .read = pci_generic_config_read32, diff --git a/include/linux/pci-ecam.h b/include/linux/pci-ecam.h index 033ce74f02e8..65d3d83015c3 100644 --- a/include/linux/pci-ecam.h +++ b/include/linux/pci-ecam.h @@ -9,6 +9,33 @@ #include #include +/* + * Memory address shift values for the byte-level address that + * can be used when accessing the PCI Express Configuration Space. + */ + +/* + * Enhanced Configuration Access Mechanism (ECAM) + * + * See PCI Express Base Specification, Revision 5.0, Version 1.0, + * Section 7.2.2, Table 7-1, p. 677. + */ +#define PCIE_ECAM_BUS_SHIFT 20 /* Bus number */ +#define PCIE_ECAM_DEVFN_SHIFT 12 /* Device and Function number */ + +#define PCIE_ECAM_BUS_MASK 0xff +#define PCIE_ECAM_DEVFN_MASK 0xff +#define PCIE_ECAM_REG_MASK 0xfff /* Limit offset to a maximum of 4K */ + +#define PCIE_ECAM_BUS(x) (((x) & PCIE_ECAM_BUS_MASK) << PCIE_ECAM_BUS_SHIFT) +#define PCIE_ECAM_DEVFN(x) (((x) & PCIE_ECAM_DEVFN_MASK) << PCIE_ECAM_DEVFN_SHIFT) +#define PCIE_ECAM_REG(x) ((x) & PCIE_ECAM_REG_MASK) + +#define PCIE_ECAM_OFFSET(bus, devfn, where) \ + (PCIE_ECAM_BUS(bus) | \ + PCIE_ECAM_DEVFN(devfn) | \ + PCIE_ECAM_REG(where)) + /* * struct to hold pci ops and bus shift of the config window * for a PCI controller. -- 2.29.2 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.2 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, 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"linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org QWRkIEVDQU0tcmVsYXRlZCBjb25zdGFudHMgdG8gcHJvdmlkZSBhIHNldCBvZiBzdGFuZGFyZCBj b25zdGFudHMKZGVmaW5pbmcgbWVtb3J5IGFkZHJlc3Mgc2hpZnQgdmFsdWVzIHRvIHRoZSBieXRl LWxldmVsIGFkZHJlc3MgdGhhdCBjYW4KYmUgdXNlZCB0byBhY2Nlc3MgdGhlIFBDSSBFeHByZXNz IENvbmZpZ3VyYXRpb24gU3BhY2UsIGFuZCB0aGVuIG1vdmUKbmF0aXZlIFBDSSBFeHByZXNzIGNv bnRyb2xsZXIgZHJpdmVycyB0byB1c2UgdGhlIG5ld2x5IGludHJvZHVjZWQKZGVmaW5pdGlvbnMg cmV0aXJpbmcgZHJpdmVyLXNwZWNpZmljIG9uZXMuCgpSZWZhY3RvciBwY2lfZWNhbV9tYXBfYnVz KCkgZnVuY3Rpb24gdG8gdXNlIG5ld2x5IGFkZGVkIGNvbnN0YW50cyBzbwp0aGF0IGxpbWl0cyB0 byB0aGUgYnVzLCBkZXZpY2UgZnVuY3Rpb24gYW5kIG9mZnNldCAobm93IGxpbWl0ZWQgdG8gNEsg YXMKcGVyIHRoZSBzcGVjaWZpY2F0aW9uKSBhcmUgaW4gcGxhY2UgdG8gcHJldmVudCB0aGUgZGVm ZWN0aXZlIG9yCm1hbGljaW91cyBjYWxsZXIgZnJvbSBzdXBwbHlpbmcgaW5jb3JyZWN0IGNvbmZp Z3VyYXRpb24gb2Zmc2V0IGFuZCB0aHVzCnRhcmdldGluZyB0aGUgd3JvbmcgZGV2aWNlIHdoZW4g YWNjZXNzaW5nIGV4dGVuZGVkIGNvbmZpZ3VyYXRpb24gc3BhY2UuClRoaXMgcmVmYWN0b3IgYWxz byBhbGxvd3MgZm9yIHRoZSAiLmJ1c19zaGl0IiBpbml0aWFsaXNlcnMgdG8gYmUgZHJvcHBlZAp3 aGVuIHRoZSB1c2VyIGlzIG5vdCB1c2luZyBhIGN1c3RvbSB2YWx1ZSBhcyBhIGRlZmF1bHQgdmFs dWUgd2lsbCBiZQp1c2VkIGFzIHBlciB0aGUgUENJIEV4cHJlc3MgU3BlY2lmaWNhdGlvbi4KClN1 Z2dlc3RlZC1ieTogQmpvcm4gSGVsZ2FhcyA8YmhlbGdhYXNAZ29vZ2xlLmNvbT4KU2lnbmVkLW9m Zi1ieTogS3J6eXN6dG9mIFdpbGN6ecWEc2tpIDxrd0BsaW51eC5jb20+Ci0tLQogZHJpdmVycy9w Y2kvY29udHJvbGxlci9kd2MvcGNpZS1hbC5jICAgICAgICB8IDEyICsrLS0tLS0tLQogZHJpdmVy cy9wY2kvY29udHJvbGxlci9kd2MvcGNpZS1oaXNpLmMgICAgICB8ICAyIC0tCiBkcml2ZXJzL3Bj aS9jb250cm9sbGVyL3BjaS1hYXJkdmFyay5jICAgICAgIHwgMTMgKysrLS0tLS0tLQogZHJpdmVy cy9wY2kvY29udHJvbGxlci9wY2ktaG9zdC1nZW5lcmljLmMgICB8ICAxIC0KIGRyaXZlcnMvcGNp L2NvbnRyb2xsZXIvcGNpLXRodW5kZXItZWNhbS5jICAgfCAgMSAtCiBkcml2ZXJzL3BjaS9jb250 cm9sbGVyL3BjaWUtYnJjbXN0Yi5jICAgICAgIHwgMTYgKystLS0tLS0tLS0tCiBkcml2ZXJzL3Bj aS9jb250cm9sbGVyL3BjaWUtcm9ja2NoaXAtaG9zdC5jIHwgMjcgKysrKysrKysrKy0tLS0tLS0t LS0tCiBkcml2ZXJzL3BjaS9jb250cm9sbGVyL3BjaWUtcm9ja2NoaXAuaCAgICAgIHwgIDggKy0t LS0tCiBkcml2ZXJzL3BjaS9jb250cm9sbGVyL3BjaWUtdGFuZ28uYyAgICAgICAgIHwgIDEgLQog ZHJpdmVycy9wY2kvY29udHJvbGxlci9wY2llLXhpbGlueC1ud2wuYyAgICB8ICA5ICsrLS0tLS0K IGRyaXZlcnMvcGNpL2NvbnRyb2xsZXIvcGNpZS14aWxpbnguYyAgICAgICAgfCAxMSArKy0tLS0t LS0KIGRyaXZlcnMvcGNpL2NvbnRyb2xsZXIvdm1kLmMgICAgICAgICAgICAgICAgfCAxMSArKysr LS0tLS0KIGRyaXZlcnMvcGNpL2VjYW0uYyAgICAgICAgICAgICAgICAgICAgICAgICAgfCAyMyAr KysrKysrKysrKystLS0tLS0KIGluY2x1ZGUvbGludXgvcGNpLWVjYW0uaCAgICAgICAgICAgICAg ICAgICAgfCAyNyArKysrKysrKysrKysrKysrKysrKysKIDE0IGZpbGVzIGNoYW5nZWQsIDczIGlu c2VydGlvbnMoKyksIDg5IGRlbGV0aW9ucygtKQoKZGlmZiAtLWdpdCBhL2RyaXZlcnMvcGNpL2Nv bnRyb2xsZXIvZHdjL3BjaWUtYWwuYyBiL2RyaXZlcnMvcGNpL2NvbnRyb2xsZXIvZHdjL3BjaWUt YWwuYwppbmRleCBmOTczZmJjYTkwY2YuLmFmOWU1MWFiMWFmOCAxMDA2NDQKLS0tIGEvZHJpdmVy cy9wY2kvY29udHJvbGxlci9kd2MvcGNpZS1hbC5jCisrKyBiL2RyaXZlcnMvcGNpL2NvbnRyb2xs ZXIvZHdjL3BjaWUtYWwuYwpAQCAtNzYsNyArNzYsNiBAQCBzdGF0aWMgaW50IGFsX3BjaWVfaW5p dChzdHJ1Y3QgcGNpX2NvbmZpZ193aW5kb3cgKmNmZykKIH0KIAogY29uc3Qgc3RydWN0IHBjaV9l Y2FtX29wcyBhbF9wY2llX29wcyA9IHsKLQkuYnVzX3NoaWZ0ICAgID0gMjAsCiAJLmluaXQgICAg ICAgICA9ICBhbF9wY2llX2luaXQsCiAJLnBjaV9vcHMgICAgICA9IHsKIAkJLm1hcF9idXMgICAg PSBhbF9wY2llX21hcF9idXMsCkBAIC0xMzgsOCArMTM3LDYgQEAgc3RydWN0IGFsX3BjaWUgewog CXN0cnVjdCBhbF9wY2llX3RhcmdldF9idXNfY2ZnIHRhcmdldF9idXNfY2ZnOwogfTsKIAotI2Rl ZmluZSBQQ0lFX0VDQU1fREVWRk4oeCkJCSgoKHgpICYgMHhmZikgPDwgMTIpCi0KICNkZWZpbmUg dG9fYWxfcGNpZSh4KQkJZGV2X2dldF9kcnZkYXRhKCh4KS0+ZGV2KQogCiBzdGF0aWMgaW5saW5l IHUzMiBhbF9wY2llX2NvbnRyb2xsZXJfcmVhZGwoc3RydWN0IGFsX3BjaWUgKnBjaWUsIHUzMiBv ZmZzZXQpCkBAIC0yMjYsMTEgKzIyMyw2IEBAIHN0YXRpYyB2b2lkIF9faW9tZW0gKmFsX3BjaWVf Y29uZl9hZGRyX21hcF9idXMoc3RydWN0IHBjaV9idXMgKmJ1cywKIAlzdHJ1Y3QgYWxfcGNpZV90 YXJnZXRfYnVzX2NmZyAqdGFyZ2V0X2J1c19jZmcgPSAmcGNpZS0+dGFyZ2V0X2J1c19jZmc7CiAJ dW5zaWduZWQgaW50IGJ1c25yX2VjYW0gPSBidXNuciAmIHRhcmdldF9idXNfY2ZnLT5lY2FtX21h c2s7CiAJdW5zaWduZWQgaW50IGJ1c25yX3JlZyA9IGJ1c25yICYgdGFyZ2V0X2J1c19jZmctPnJl Z19tYXNrOwotCXZvaWQgX19pb21lbSAqcGNpX2Jhc2VfYWRkcjsKLQotCXBjaV9iYXNlX2FkZHIg PSAodm9pZCBfX2lvbWVtICopKCh1aW50cHRyX3QpcHAtPnZhX2NmZzBfYmFzZSArCi0JCQkJCSAo YnVzbnJfZWNhbSA8PCAyMCkgKwotCQkJCQkgUENJRV9FQ0FNX0RFVkZOKGRldmZuKSk7CiAKIAlp ZiAoYnVzbnJfcmVnICE9IHRhcmdldF9idXNfY2ZnLT5yZWdfdmFsKSB7CiAJCWRldl9kYmcocGNp ZS0+cGNpLT5kZXYsICJDaGFuZ2luZyB0YXJnZXQgYnVzIGJ1c251bSB2YWwgZnJvbSAweCV4IHRv IDB4JXhcbiIsCkBAIC0yNDEsNyArMjMzLDcgQEAgc3RhdGljIHZvaWQgX19pb21lbSAqYWxfcGNp ZV9jb25mX2FkZHJfbWFwX2J1cyhzdHJ1Y3QgcGNpX2J1cyAqYnVzLAogCQkJCSAgICAgICB0YXJn ZXRfYnVzX2NmZy0+cmVnX21hc2spOwogCX0KIAotCXJldHVybiBwY2lfYmFzZV9hZGRyICsgd2hl cmU7CisJcmV0dXJuIHBwLT52YV9jZmcwX2Jhc2UgKyBQQ0lFX0VDQU1fT0ZGU0VUKGJ1c25yX2Vj YW0sIGRldmZuLCB3aGVyZSk7CiB9CiAKIHN0YXRpYyBzdHJ1Y3QgcGNpX29wcyBhbF9jaGlsZF9w Y2lfb3BzID0gewpAQCAtMjY0LDcgKzI1Niw3IEBAIHN0YXRpYyB2b2lkIGFsX3BjaWVfY29uZmln X3ByZXBhcmUoc3RydWN0IGFsX3BjaWUgKnBjaWUpCiAKIAl0YXJnZXRfYnVzX2NmZyA9ICZwY2ll LT50YXJnZXRfYnVzX2NmZzsKIAotCWVjYW1fYnVzX21hc2sgPSAocGNpZS0+ZWNhbV9zaXplID4+ IDIwKSAtIDE7CisJZWNhbV9idXNfbWFzayA9IChwY2llLT5lY2FtX3NpemUgPj4gUENJRV9FQ0FN X0JVU19TSElGVCkgLSAxOwogCWlmIChlY2FtX2J1c19tYXNrID4gMjU1KSB7CiAJCWRldl93YXJu KHBjaWUtPmRldiwgIkVDQU0gd2luZG93IHNpemUgaXMgbGFyZ2VyIHRoYW4gMjU2TUIuIEN1dHRp bmcgb2ZmIGF0IDI1NlxuIik7CiAJCWVjYW1fYnVzX21hc2sgPSAyNTU7CmRpZmYgLS1naXQgYS9k cml2ZXJzL3BjaS9jb250cm9sbGVyL2R3Yy9wY2llLWhpc2kuYyBiL2RyaXZlcnMvcGNpL2NvbnRy b2xsZXIvZHdjL3BjaWUtaGlzaS5jCmluZGV4IDVjYTg2Nzk2ZDQzYS4uOGZjNTk2MGZhZjI4IDEw MDY0NAotLS0gYS9kcml2ZXJzL3BjaS9jb250cm9sbGVyL2R3Yy9wY2llLWhpc2kuYworKysgYi9k cml2ZXJzL3BjaS9jb250cm9sbGVyL2R3Yy9wY2llLWhpc2kuYwpAQCAtMTAwLDcgKzEwMCw2IEBA IHN0YXRpYyBpbnQgaGlzaV9wY2llX2luaXQoc3RydWN0IHBjaV9jb25maWdfd2luZG93ICpjZmcp CiB9CiAKIGNvbnN0IHN0cnVjdCBwY2lfZWNhbV9vcHMgaGlzaV9wY2llX29wcyA9IHsKLQkuYnVz X3NoaWZ0ICAgID0gMjAsCiAJLmluaXQgICAgICAgICA9ICBoaXNpX3BjaWVfaW5pdCwKIAkucGNp X29wcyAgICAgID0gewogCQkubWFwX2J1cyAgICA9IGhpc2lfcGNpZV9tYXBfYnVzLApAQCAtMTM1 LDcgKzEzNCw2IEBAIHN0YXRpYyBpbnQgaGlzaV9wY2llX3BsYXRmb3JtX2luaXQoc3RydWN0IHBj aV9jb25maWdfd2luZG93ICpjZmcpCiB9CiAKIHN0YXRpYyBjb25zdCBzdHJ1Y3QgcGNpX2VjYW1f b3BzIGhpc2lfcGNpZV9wbGF0Zm9ybV9vcHMgPSB7Ci0JLmJ1c19zaGlmdCAgICA9IDIwLAogCS5p bml0ICAgICAgICAgPSAgaGlzaV9wY2llX3BsYXRmb3JtX2luaXQsCiAJLnBjaV9vcHMgICAgICA9 IHsKIAkJLm1hcF9idXMgICAgPSBoaXNpX3BjaWVfbWFwX2J1cywKZGlmZiAtLWdpdCBhL2RyaXZl cnMvcGNpL2NvbnRyb2xsZXIvcGNpLWFhcmR2YXJrLmMgYi9kcml2ZXJzL3BjaS9jb250cm9sbGVy L3BjaS1hYXJkdmFyay5jCmluZGV4IDBiZTQ4NWEyNTMyNy4uMTA0M2U1NGM3M2JkIDEwMDY0NAot LS0gYS9kcml2ZXJzL3BjaS9jb250cm9sbGVyL3BjaS1hYXJkdmFyay5jCisrKyBiL2RyaXZlcnMv cGNpL2NvbnRyb2xsZXIvcGNpLWFhcmR2YXJrLmMKQEAgLTE2LDYgKzE2LDcgQEAKICNpbmNsdWRl IDxsaW51eC9rZXJuZWwuaD4KICNpbmNsdWRlIDxsaW51eC9tb2R1bGUuaD4KICNpbmNsdWRlIDxs aW51eC9wY2kuaD4KKyNpbmNsdWRlIDxsaW51eC9wY2ktZWNhbS5oPgogI2luY2x1ZGUgPGxpbnV4 L2luaXQuaD4KICNpbmNsdWRlIDxsaW51eC9waHkvcGh5Lmg+CiAjaW5jbHVkZSA8bGludXgvcGxh dGZvcm1fZGV2aWNlLmg+CkBAIC0xNjQsMTQgKzE2NSw2IEBACiAjZGVmaW5lIFBDSUVfQ09ORklH X1dSX1RZUEUwCQkJMHhhCiAjZGVmaW5lIFBDSUVfQ09ORklHX1dSX1RZUEUxCQkJMHhiCiAKLSNk ZWZpbmUgUENJRV9DT05GX0JVUyhidXMpCQkJKCgoYnVzKSAmIDB4ZmYpIDw8IDIwKQotI2RlZmlu ZSBQQ0lFX0NPTkZfREVWKGRldikJCQkoKChkZXYpICYgMHgxZikgPDwgMTUpCi0jZGVmaW5lIFBD SUVfQ09ORl9GVU5DKGZ1bikJCQkoKChmdW4pICYgMHg3KQk8PCAxMikKLSNkZWZpbmUgUENJRV9D T05GX1JFRyhyZWcpCQkJKChyZWcpICYgMHhmZmMpCi0jZGVmaW5lIFBDSUVfQ09ORl9BRERSKGJ1 cywgZGV2Zm4sIHdoZXJlKQlcCi0JKFBDSUVfQ09ORl9CVVMoYnVzKSB8IFBDSUVfQ09ORl9ERVYo UENJX1NMT1QoZGV2Zm4pKQl8IFwKLQkgUENJRV9DT05GX0ZVTkMoUENJX0ZVTkMoZGV2Zm4pKSB8 IFBDSUVfQ09ORl9SRUcod2hlcmUpKQotCiAjZGVmaW5lIFBJT19SRVRSWV9DTlQJCQk1MDAKICNk ZWZpbmUgUElPX1JFVFJZX0RFTEFZCQkJMiAvKiAyIHVzKi8KIApAQCAtNjg3LDcgKzY4MCw3IEBA IHN0YXRpYyBpbnQgYWR2a19wY2llX3JkX2NvbmYoc3RydWN0IHBjaV9idXMgKmJ1cywgdTMyIGRl dmZuLAogCWFkdmtfd3JpdGVsKHBjaWUsIHJlZywgUElPX0NUUkwpOwogCiAJLyogUHJvZ3JhbSB0 aGUgYWRkcmVzcyByZWdpc3RlcnMgKi8KLQlyZWcgPSBQQ0lFX0NPTkZfQUREUihidXMtPm51bWJl ciwgZGV2Zm4sIHdoZXJlKTsKKwlyZWcgPSBBTElHTl9ET1dOKFBDSUVfRUNBTV9PRkZTRVQoYnVz LT5udW1iZXIsIGRldmZuLCB3aGVyZSksIDQpOwogCWFkdmtfd3JpdGVsKHBjaWUsIHJlZywgUElP X0FERFJfTFMpOwogCWFkdmtfd3JpdGVsKHBjaWUsIDAsIFBJT19BRERSX01TKTsKIApAQCAtNzQ4 LDcgKzc0MSw3IEBAIHN0YXRpYyBpbnQgYWR2a19wY2llX3dyX2NvbmYoc3RydWN0IHBjaV9idXMg KmJ1cywgdTMyIGRldmZuLAogCWFkdmtfd3JpdGVsKHBjaWUsIHJlZywgUElPX0NUUkwpOwogCiAJ LyogUHJvZ3JhbSB0aGUgYWRkcmVzcyByZWdpc3RlcnMgKi8KLQlyZWcgPSBQQ0lFX0NPTkZfQURE UihidXMtPm51bWJlciwgZGV2Zm4sIHdoZXJlKTsKKwlyZWcgPSBBTElHTl9ET1dOKFBDSUVfRUNB TV9PRkZTRVQoYnVzLT5udW1iZXIsIGRldmZuLCB3aGVyZSksIDQpOwogCWFkdmtfd3JpdGVsKHBj aWUsIHJlZywgUElPX0FERFJfTFMpOwogCWFkdmtfd3JpdGVsKHBjaWUsIDAsIFBJT19BRERSX01T KTsKIApkaWZmIC0tZ2l0IGEvZHJpdmVycy9wY2kvY29udHJvbGxlci9wY2ktaG9zdC1nZW5lcmlj LmMgYi9kcml2ZXJzL3BjaS9jb250cm9sbGVyL3BjaS1ob3N0LWdlbmVyaWMuYwppbmRleCBiNTE5 NzdhYmZkZjEuLjYzODY1YWViNjM2YiAxMDA2NDQKLS0tIGEvZHJpdmVycy9wY2kvY29udHJvbGxl ci9wY2ktaG9zdC1nZW5lcmljLmMKKysrIGIvZHJpdmVycy9wY2kvY29udHJvbGxlci9wY2ktaG9z dC1nZW5lcmljLmMKQEAgLTQ5LDcgKzQ5LDYgQEAgc3RhdGljIHZvaWQgX19pb21lbSAqcGNpX2R3 X2VjYW1fbWFwX2J1cyhzdHJ1Y3QgcGNpX2J1cyAqYnVzLAogfQogCiBzdGF0aWMgY29uc3Qgc3Ry dWN0IHBjaV9lY2FtX29wcyBwY2lfZHdfZWNhbV9idXNfb3BzID0gewotCS5idXNfc2hpZnQJPSAy MCwKIAkucGNpX29wcwk9IHsKIAkJLm1hcF9idXMJPSBwY2lfZHdfZWNhbV9tYXBfYnVzLAogCQku cmVhZAkJPSBwY2lfZ2VuZXJpY19jb25maWdfcmVhZCwKZGlmZiAtLWdpdCBhL2RyaXZlcnMvcGNp L2NvbnRyb2xsZXIvcGNpLXRodW5kZXItZWNhbS5jIGIvZHJpdmVycy9wY2kvY29udHJvbGxlci9w Y2ktdGh1bmRlci1lY2FtLmMKaW5kZXggN2U4ODM1ZmVlNWY3Li5mOTY0ZmQyNmY3ZTAgMTAwNjQ0 Ci0tLSBhL2RyaXZlcnMvcGNpL2NvbnRyb2xsZXIvcGNpLXRodW5kZXItZWNhbS5jCisrKyBiL2Ry aXZlcnMvcGNpL2NvbnRyb2xsZXIvcGNpLXRodW5kZXItZWNhbS5jCkBAIC0zNDYsNyArMzQ2LDYg QEAgc3RhdGljIGludCB0aHVuZGVyX2VjYW1fY29uZmlnX3dyaXRlKHN0cnVjdCBwY2lfYnVzICpi dXMsIHVuc2lnbmVkIGludCBkZXZmbiwKIH0KIAogY29uc3Qgc3RydWN0IHBjaV9lY2FtX29wcyBw Y2lfdGh1bmRlcl9lY2FtX29wcyA9IHsKLQkuYnVzX3NoaWZ0CT0gMjAsCiAJLnBjaV9vcHMJPSB7 CiAJCS5tYXBfYnVzICAgICAgICA9IHBjaV9lY2FtX21hcF9idXMsCiAJCS5yZWFkICAgICAgICAg ICA9IHRodW5kZXJfZWNhbV9jb25maWdfcmVhZCwKZGlmZiAtLWdpdCBhL2RyaXZlcnMvcGNpL2Nv bnRyb2xsZXIvcGNpZS1icmNtc3RiLmMgYi9kcml2ZXJzL3BjaS9jb250cm9sbGVyL3BjaWUtYnJj bXN0Yi5jCmluZGV4IGJlYTg2ODk5YmQ1ZC4uN2ZjODBmZDZmMTNmIDEwMDY0NAotLS0gYS9kcml2 ZXJzL3BjaS9jb250cm9sbGVyL3BjaWUtYnJjbXN0Yi5jCisrKyBiL2RyaXZlcnMvcGNpL2NvbnRy b2xsZXIvcGNpZS1icmNtc3RiLmMKQEAgLTIyLDYgKzIyLDcgQEAKICNpbmNsdWRlIDxsaW51eC9v Zl9wY2kuaD4KICNpbmNsdWRlIDxsaW51eC9vZl9wbGF0Zm9ybS5oPgogI2luY2x1ZGUgPGxpbnV4 L3BjaS5oPgorI2luY2x1ZGUgPGxpbnV4L3BjaS1lY2FtLmg+CiAjaW5jbHVkZSA8bGludXgvcHJp bnRrLmg+CiAjaW5jbHVkZSA8bGludXgvcmVzZXQuaD4KICNpbmNsdWRlIDxsaW51eC9zaXplcy5o PgpAQCAtMTI3LDExICsxMjgsNyBAQAogI2RlZmluZSAgTVNJX0lOVF9NQVNLX0NMUgkJMHgxNAog CiAjZGVmaW5lIFBDSUVfRVhUX0NGR19EQVRBCQkJCTB4ODAwMAotCiAjZGVmaW5lIFBDSUVfRVhU X0NGR19JTkRFWAkJCQkweDkwMDAKLSNkZWZpbmUgIFBDSUVfRVhUX0JVU05VTV9TSElGVAkJCQky MAotI2RlZmluZSAgUENJRV9FWFRfU0xPVF9TSElGVAkJCQkxNQotI2RlZmluZSAgUENJRV9FWFRf RlVOQ19TSElGVAkJCQkxMgogCiAjZGVmaW5lICBQQ0lFX1JHUjFfU1dfSU5JVF8xX1BFUlNUX01B U0sJCQkweDEKICNkZWZpbmUgIFBDSUVfUkdSMV9TV19JTklUXzFfUEVSU1RfU0hJRlQJCTB4MApA QCAtNjk1LDE1ICs2OTIsNiBAQCBzdGF0aWMgYm9vbCBicmNtX3BjaWVfbGlua191cChzdHJ1Y3Qg YnJjbV9wY2llICpwY2llKQogCXJldHVybiBkbGEgJiYgcGx1OwogfQogCi0vKiBDb25maWd1cmF0 aW9uIHNwYWNlIHJlYWQvd3JpdGUgc3VwcG9ydCAqLwotc3RhdGljIGlubGluZSBpbnQgYnJjbV9w Y2llX2NmZ19pbmRleChpbnQgYnVzbnIsIGludCBkZXZmbiwgaW50IHJlZykKLXsKLQlyZXR1cm4g KChQQ0lfU0xPVChkZXZmbikgJiAweDFmKSA8PCBQQ0lFX0VYVF9TTE9UX1NISUZUKQotCQl8ICgo UENJX0ZVTkMoZGV2Zm4pICYgMHgwNykgPDwgUENJRV9FWFRfRlVOQ19TSElGVCkKLQkJfCAoYnVz bnIgPDwgUENJRV9FWFRfQlVTTlVNX1NISUZUKQotCQl8IChyZWcgJiB+Myk7Ci19Ci0KIHN0YXRp YyB2b2lkIF9faW9tZW0gKmJyY21fcGNpZV9tYXBfY29uZihzdHJ1Y3QgcGNpX2J1cyAqYnVzLCB1 bnNpZ25lZCBpbnQgZGV2Zm4sCiAJCQkJCWludCB3aGVyZSkKIHsKQEAgLTcxNiw3ICs3MDQsNyBA QCBzdGF0aWMgdm9pZCBfX2lvbWVtICpicmNtX3BjaWVfbWFwX2NvbmYoc3RydWN0IHBjaV9idXMg KmJ1cywgdW5zaWduZWQgaW50IGRldmZuLAogCQlyZXR1cm4gUENJX1NMT1QoZGV2Zm4pID8gTlVM TCA6IGJhc2UgKyB3aGVyZTsKIAogCS8qIEZvciBkZXZpY2VzLCB3cml0ZSB0byB0aGUgY29uZmln IHNwYWNlIGluZGV4IHJlZ2lzdGVyICovCi0JaWR4ID0gYnJjbV9wY2llX2NmZ19pbmRleChidXMt Pm51bWJlciwgZGV2Zm4sIDApOworCWlkeCA9IFBDSUVfRUNBTV9PRkZTRVQoYnVzLT5udW1iZXIs IGRldmZuLCAwKTsKIAl3cml0ZWwoaWR4LCBwY2llLT5iYXNlICsgUENJRV9FWFRfQ0ZHX0lOREVY KTsKIAlyZXR1cm4gYmFzZSArIFBDSUVfRVhUX0NGR19EQVRBICsgd2hlcmU7CiB9CmRpZmYgLS1n aXQgYS9kcml2ZXJzL3BjaS9jb250cm9sbGVyL3BjaWUtcm9ja2NoaXAtaG9zdC5jIGIvZHJpdmVy cy9wY2kvY29udHJvbGxlci9wY2llLXJvY2tjaGlwLWhvc3QuYwppbmRleCA5NzA1MDU5NTIzYTYu LmYxZDA4YTFiMTU5MSAxMDA2NDQKLS0tIGEvZHJpdmVycy9wY2kvY29udHJvbGxlci9wY2llLXJv Y2tjaGlwLWhvc3QuYworKysgYi9kcml2ZXJzL3BjaS9jb250cm9sbGVyL3BjaWUtcm9ja2NoaXAt aG9zdC5jCkBAIC0xNTcsMTIgKzE1NywxMSBAQCBzdGF0aWMgaW50IHJvY2tjaGlwX3BjaWVfcmRf b3RoZXJfY29uZihzdHJ1Y3Qgcm9ja2NoaXBfcGNpZSAqcm9ja2NoaXAsCiAJCQkJICAgICAgIHN0 cnVjdCBwY2lfYnVzICpidXMsIHUzMiBkZXZmbiwKIAkJCQkgICAgICAgaW50IHdoZXJlLCBpbnQg c2l6ZSwgdTMyICp2YWwpCiB7Ci0JdTMyIGJ1c2RldjsKKwl2b2lkIF9faW9tZW0gKmFkZHI7CiAK LQlidXNkZXYgPSBQQ0lFX0VDQU1fQUREUihidXMtPm51bWJlciwgUENJX1NMT1QoZGV2Zm4pLAot CQkJCVBDSV9GVU5DKGRldmZuKSwgd2hlcmUpOworCWFkZHIgPSByb2NrY2hpcC0+cmVnX2Jhc2Ug KyBQQ0lFX0VDQU1fT0ZGU0VUKGJ1cy0+bnVtYmVyLCBkZXZmbiwgd2hlcmUpOwogCi0JaWYgKCFJ U19BTElHTkVEKGJ1c2Rldiwgc2l6ZSkpIHsKKwlpZiAoIUlTX0FMSUdORUQoKHVpbnRwdHJfdClh ZGRyLCBzaXplKSkgewogCQkqdmFsID0gMDsKIAkJcmV0dXJuIFBDSUJJT1NfQkFEX1JFR0lTVEVS X05VTUJFUjsKIAl9CkBAIC0xNzUsMTEgKzE3NCwxMSBAQCBzdGF0aWMgaW50IHJvY2tjaGlwX3Bj aWVfcmRfb3RoZXJfY29uZihzdHJ1Y3Qgcm9ja2NoaXBfcGNpZSAqcm9ja2NoaXAsCiAJCQkJCQlB WElfV1JBUFBFUl9UWVBFMV9DRkcpOwogCiAJaWYgKHNpemUgPT0gNCkgewotCQkqdmFsID0gcmVh ZGwocm9ja2NoaXAtPnJlZ19iYXNlICsgYnVzZGV2KTsKKwkJKnZhbCA9IHJlYWRsKGFkZHIpOwog CX0gZWxzZSBpZiAoc2l6ZSA9PSAyKSB7Ci0JCSp2YWwgPSByZWFkdyhyb2NrY2hpcC0+cmVnX2Jh c2UgKyBidXNkZXYpOworCQkqdmFsID0gcmVhZHcoYWRkcik7CiAJfSBlbHNlIGlmIChzaXplID09 IDEpIHsKLQkJKnZhbCA9IHJlYWRiKHJvY2tjaGlwLT5yZWdfYmFzZSArIGJ1c2Rldik7CisJCSp2 YWwgPSByZWFkYihhZGRyKTsKIAl9IGVsc2UgewogCQkqdmFsID0gMDsKIAkJcmV0dXJuIFBDSUJJ T1NfQkFEX1JFR0lTVEVSX05VTUJFUjsKQEAgLTE5MSwxMSArMTkwLDExIEBAIHN0YXRpYyBpbnQg cm9ja2NoaXBfcGNpZV93cl9vdGhlcl9jb25mKHN0cnVjdCByb2NrY2hpcF9wY2llICpyb2NrY2hp cCwKIAkJCQkgICAgICAgc3RydWN0IHBjaV9idXMgKmJ1cywgdTMyIGRldmZuLAogCQkJCSAgICAg ICBpbnQgd2hlcmUsIGludCBzaXplLCB1MzIgdmFsKQogewotCXUzMiBidXNkZXY7CisJdm9pZCBf X2lvbWVtICphZGRyOwogCi0JYnVzZGV2ID0gUENJRV9FQ0FNX0FERFIoYnVzLT5udW1iZXIsIFBD SV9TTE9UKGRldmZuKSwKLQkJCQlQQ0lfRlVOQyhkZXZmbiksIHdoZXJlKTsKLQlpZiAoIUlTX0FM SUdORUQoYnVzZGV2LCBzaXplKSkKKwlhZGRyID0gcm9ja2NoaXAtPnJlZ19iYXNlICsgUENJRV9F Q0FNX09GRlNFVChidXMtPm51bWJlciwgZGV2Zm4sIHdoZXJlKTsKKworCWlmICghSVNfQUxJR05F RCgodWludHB0cl90KWFkZHIsIHNpemUpKQogCQlyZXR1cm4gUENJQklPU19CQURfUkVHSVNURVJf TlVNQkVSOwogCiAJaWYgKHBjaV9pc19yb290X2J1cyhidXMtPnBhcmVudCkpCkBAIC0yMDYsMTEg KzIwNSwxMSBAQCBzdGF0aWMgaW50IHJvY2tjaGlwX3BjaWVfd3Jfb3RoZXJfY29uZihzdHJ1Y3Qg cm9ja2NoaXBfcGNpZSAqcm9ja2NoaXAsCiAJCQkJCQlBWElfV1JBUFBFUl9UWVBFMV9DRkcpOwog CiAJaWYgKHNpemUgPT0gNCkKLQkJd3JpdGVsKHZhbCwgcm9ja2NoaXAtPnJlZ19iYXNlICsgYnVz ZGV2KTsKKwkJd3JpdGVsKHZhbCwgYWRkcik7CiAJZWxzZSBpZiAoc2l6ZSA9PSAyKQotCQl3cml0 ZXcodmFsLCByb2NrY2hpcC0+cmVnX2Jhc2UgKyBidXNkZXYpOworCQl3cml0ZXcodmFsLCBhZGRy KTsKIAllbHNlIGlmIChzaXplID09IDEpCi0JCXdyaXRlYih2YWwsIHJvY2tjaGlwLT5yZWdfYmFz ZSArIGJ1c2Rldik7CisJCXdyaXRlYih2YWwsIGFkZHIpOwogCWVsc2UKIAkJcmV0dXJuIFBDSUJJ T1NfQkFEX1JFR0lTVEVSX05VTUJFUjsKIApkaWZmIC0tZ2l0IGEvZHJpdmVycy9wY2kvY29udHJv bGxlci9wY2llLXJvY2tjaGlwLmggYi9kcml2ZXJzL3BjaS9jb250cm9sbGVyL3BjaWUtcm9ja2No aXAuaAppbmRleCBjN2QwMTc4ZmM4YzIuLjE2NTBhNTA4NzQ1MCAxMDA2NDQKLS0tIGEvZHJpdmVy cy9wY2kvY29udHJvbGxlci9wY2llLXJvY2tjaGlwLmgKKysrIGIvZHJpdmVycy9wY2kvY29udHJv bGxlci9wY2llLXJvY2tjaGlwLmgKQEAgLTEzLDYgKzEzLDcgQEAKIAogI2luY2x1ZGUgPGxpbnV4 L2tlcm5lbC5oPgogI2luY2x1ZGUgPGxpbnV4L3BjaS5oPgorI2luY2x1ZGUgPGxpbnV4L3BjaS1l Y2FtLmg+CiAKIC8qCiAgKiBUaGUgdXBwZXIgMTYgYml0cyBvZiBQQ0lFX0NMSUVOVF9DT05GSUcg YXJlIGEgd3JpdGUgbWFzayBmb3IgdGhlIGxvd2VyIDE2CkBAIC0xNzgsMTMgKzE3OSw2IEBACiAj ZGVmaW5lIE1JTl9BWElfQUREUl9CSVRTX1BBU1NFRAkJOAogI2RlZmluZSBQQ0lFX1JDX1NFTkRf UE1FX09GRgkJCTB4MTE5NjAKICNkZWZpbmUgUk9DS0NISVBfVkVORE9SX0lECQkJMHgxZDg3Ci0j ZGVmaW5lIFBDSUVfRUNBTV9CVVMoeCkJCQkoKCh4KSAmIDB4ZmYpIDw8IDIwKQotI2RlZmluZSBQ Q0lFX0VDQU1fREVWKHgpCQkJKCgoeCkgJiAweDFmKSA8PCAxNSkKLSNkZWZpbmUgUENJRV9FQ0FN X0ZVTkMoeCkJCQkoKCh4KSAmIDB4NykgPDwgMTIpCi0jZGVmaW5lIFBDSUVfRUNBTV9SRUcoeCkJ CQkoKCh4KSAmIDB4ZmZmKSA8PCAwKQotI2RlZmluZSBQQ0lFX0VDQU1fQUREUihidXMsIGRldiwg ZnVuYywgcmVnKSBcCi0JICAoUENJRV9FQ0FNX0JVUyhidXMpIHwgUENJRV9FQ0FNX0RFVihkZXYp IHwgXAotCSAgIFBDSUVfRUNBTV9GVU5DKGZ1bmMpIHwgUENJRV9FQ0FNX1JFRyhyZWcpKQogI2Rl ZmluZSBQQ0lFX0xJTktfSVNfTDIoeCkgXAogCSgoKHgpICYgUENJRV9DTElFTlRfREVCVUdfTFRT U01fTUFTSykgPT0gUENJRV9DTElFTlRfREVCVUdfTFRTU01fTDIpCiAjZGVmaW5lIFBDSUVfTElO S19VUCh4KSBcCmRpZmYgLS1naXQgYS9kcml2ZXJzL3BjaS9jb250cm9sbGVyL3BjaWUtdGFuZ28u YyBiL2RyaXZlcnMvcGNpL2NvbnRyb2xsZXIvcGNpZS10YW5nby5jCmluZGV4IGQwOTNhOGNlNGJi MS4uNjJhMDYxZjFkNjJlIDEwMDY0NAotLS0gYS9kcml2ZXJzL3BjaS9jb250cm9sbGVyL3BjaWUt dGFuZ28uYworKysgYi9kcml2ZXJzL3BjaS9jb250cm9sbGVyL3BjaWUtdGFuZ28uYwpAQCAtMjA4 LDcgKzIwOCw2IEBAIHN0YXRpYyBpbnQgc21wODc1OV9jb25maWdfd3JpdGUoc3RydWN0IHBjaV9i dXMgKmJ1cywgdW5zaWduZWQgaW50IGRldmZuLAogfQogCiBzdGF0aWMgY29uc3Qgc3RydWN0IHBj aV9lY2FtX29wcyBzbXA4NzU5X2VjYW1fb3BzID0gewotCS5idXNfc2hpZnQJPSAyMCwKIAkucGNp X29wcwk9IHsKIAkJLm1hcF9idXMJPSBwY2lfZWNhbV9tYXBfYnVzLAogCQkucmVhZAkJPSBzbXA4 NzU5X2NvbmZpZ19yZWFkLApkaWZmIC0tZ2l0IGEvZHJpdmVycy9wY2kvY29udHJvbGxlci9wY2ll LXhpbGlueC1ud2wuYyBiL2RyaXZlcnMvcGNpL2NvbnRyb2xsZXIvcGNpZS14aWxpbngtbndsLmMK aW5kZXggZjNjZjdkNjE5MjRmLi43ZjI5YzJmZGNkNTEgMTAwNjQ0Ci0tLSBhL2RyaXZlcnMvcGNp L2NvbnRyb2xsZXIvcGNpZS14aWxpbngtbndsLmMKKysrIGIvZHJpdmVycy9wY2kvY29udHJvbGxl ci9wY2llLXhpbGlueC1ud2wuYwpAQCAtMTgsNiArMTgsNyBAQAogI2luY2x1ZGUgPGxpbnV4L29m X3BsYXRmb3JtLmg+CiAjaW5jbHVkZSA8bGludXgvb2ZfaXJxLmg+CiAjaW5jbHVkZSA8bGludXgv cGNpLmg+CisjaW5jbHVkZSA8bGludXgvcGNpLWVjYW0uaD4KICNpbmNsdWRlIDxsaW51eC9wbGF0 Zm9ybV9kZXZpY2UuaD4KICNpbmNsdWRlIDxsaW51eC9pcnFjaGlwL2NoYWluZWRfaXJxLmg+CiAK QEAgLTEyNCw4ICsxMjUsNiBAQAogI2RlZmluZSBFX0VDQU1fQ1JfRU5BQkxFCQlCSVQoMCkKICNk ZWZpbmUgRV9FQ0FNX1NJWkVfTE9DCQkJR0VOTUFTSygyMCwgMTYpCiAjZGVmaW5lIEVfRUNBTV9T SVpFX1NISUZUCQkxNgotI2RlZmluZSBFQ0FNX0JVU19MT0NfU0hJRlQJCTIwCi0jZGVmaW5lIEVD QU1fREVWX0xPQ19TSElGVAkJMTIKICNkZWZpbmUgTldMX0VDQU1fVkFMVUVfREVGQVVMVAkJMTIK IAogI2RlZmluZSBDRkdfRE1BX1JFR19CQVIJCQlHRU5NQVNLKDIsIDApCkBAIC0yNDAsMTUgKzIz OSwxMSBAQCBzdGF0aWMgdm9pZCBfX2lvbWVtICpud2xfcGNpZV9tYXBfYnVzKHN0cnVjdCBwY2lf YnVzICpidXMsIHVuc2lnbmVkIGludCBkZXZmbiwKIAkJCQkgICAgICBpbnQgd2hlcmUpCiB7CiAJ c3RydWN0IG53bF9wY2llICpwY2llID0gYnVzLT5zeXNkYXRhOwotCWludCByZWxidXM7CiAKIAlp ZiAoIW53bF9wY2llX3ZhbGlkX2RldmljZShidXMsIGRldmZuKSkKIAkJcmV0dXJuIE5VTEw7CiAK LQlyZWxidXMgPSAoYnVzLT5udW1iZXIgPDwgRUNBTV9CVVNfTE9DX1NISUZUKSB8Ci0JCQkoZGV2 Zm4gPDwgRUNBTV9ERVZfTE9DX1NISUZUKTsKLQotCXJldHVybiBwY2llLT5lY2FtX2Jhc2UgKyBy ZWxidXMgKyB3aGVyZTsKKwlyZXR1cm4gcGNpZS0+ZWNhbV9iYXNlICsgUENJRV9FQ0FNX09GRlNF VChidXMtPm51bWJlciwgZGV2Zm4sIHdoZXJlKTsKIH0KIAogLyogUENJZSBvcGVyYXRpb25zICov CmRpZmYgLS1naXQgYS9kcml2ZXJzL3BjaS9jb250cm9sbGVyL3BjaWUteGlsaW54LmMgYi9kcml2 ZXJzL3BjaS9jb250cm9sbGVyL3BjaWUteGlsaW54LmMKaW5kZXggODUyM2JlNjFiYmE1Li5mYTVi YWViODI2NTMgMTAwNjQ0Ci0tLSBhL2RyaXZlcnMvcGNpL2NvbnRyb2xsZXIvcGNpZS14aWxpbngu YworKysgYi9kcml2ZXJzL3BjaS9jb250cm9sbGVyL3BjaWUteGlsaW54LmMKQEAgLTIxLDYgKzIx LDcgQEAKICNpbmNsdWRlIDxsaW51eC9vZl9wbGF0Zm9ybS5oPgogI2luY2x1ZGUgPGxpbnV4L29m X2lycS5oPgogI2luY2x1ZGUgPGxpbnV4L3BjaS5oPgorI2luY2x1ZGUgPGxpbnV4L3BjaS1lY2Ft Lmg+CiAjaW5jbHVkZSA8bGludXgvcGxhdGZvcm1fZGV2aWNlLmg+CiAKICNpbmNsdWRlICIuLi9w Y2kuaCIKQEAgLTg2LDEwICs4Nyw2IEBACiAvKiBQaHkgU3RhdHVzL0NvbnRyb2wgUmVnaXN0ZXIg ZGVmaW5pdGlvbnMgKi8KICNkZWZpbmUgWElMSU5YX1BDSUVfUkVHX1BTQ1JfTE5LVVAJQklUKDEx KQogCi0vKiBFQ0FNIGRlZmluaXRpb25zICovCi0jZGVmaW5lIEVDQU1fQlVTX05VTV9TSElGVAkJ MjAKLSNkZWZpbmUgRUNBTV9ERVZfTlVNX1NISUZUCQkxMgotCiAvKiBOdW1iZXIgb2YgTVNJIElS UXMgKi8KICNkZWZpbmUgWElMSU5YX05VTV9NU0lfSVJRUwkJMTI4CiAKQEAgLTE4MywxNSArMTgw LDExIEBAIHN0YXRpYyB2b2lkIF9faW9tZW0gKnhpbGlueF9wY2llX21hcF9idXMoc3RydWN0IHBj aV9idXMgKmJ1cywKIAkJCQkJIHVuc2lnbmVkIGludCBkZXZmbiwgaW50IHdoZXJlKQogewogCXN0 cnVjdCB4aWxpbnhfcGNpZV9wb3J0ICpwb3J0ID0gYnVzLT5zeXNkYXRhOwotCWludCByZWxidXM7 CiAKIAlpZiAoIXhpbGlueF9wY2llX3ZhbGlkX2RldmljZShidXMsIGRldmZuKSkKIAkJcmV0dXJu IE5VTEw7CiAKLQlyZWxidXMgPSAoYnVzLT5udW1iZXIgPDwgRUNBTV9CVVNfTlVNX1NISUZUKSB8 Ci0JCSAoZGV2Zm4gPDwgRUNBTV9ERVZfTlVNX1NISUZUKTsKLQotCXJldHVybiBwb3J0LT5yZWdf YmFzZSArIHJlbGJ1cyArIHdoZXJlOworCXJldHVybiBwb3J0LT5yZWdfYmFzZSArIFBDSUVfRUNB TV9PRkZTRVQoYnVzLT5udW1iZXIsIGRldmZuLCB3aGVyZSk7CiB9CiAKIC8qIFBDSWUgb3BlcmF0 aW9ucyAqLwpkaWZmIC0tZ2l0IGEvZHJpdmVycy9wY2kvY29udHJvbGxlci92bWQuYyBiL2RyaXZl cnMvcGNpL2NvbnRyb2xsZXIvdm1kLmMKaW5kZXggZjM3NWMyMWNlZWIxLi4xMzYxYTc5YmQxZTcg MTAwNjQ0Ci0tLSBhL2RyaXZlcnMvcGNpL2NvbnRyb2xsZXIvdm1kLmMKKysrIGIvZHJpdmVycy9w Y2kvY29udHJvbGxlci92bWQuYwpAQCAtMTEsNiArMTEsNyBAQAogI2luY2x1ZGUgPGxpbnV4L21v ZHVsZS5oPgogI2luY2x1ZGUgPGxpbnV4L21zaS5oPgogI2luY2x1ZGUgPGxpbnV4L3BjaS5oPgor I2luY2x1ZGUgPGxpbnV4L3BjaS1lY2FtLmg+CiAjaW5jbHVkZSA8bGludXgvc3JjdS5oPgogI2lu Y2x1ZGUgPGxpbnV4L3JjdWxpc3QuaD4KICNpbmNsdWRlIDxsaW51eC9yY3VwZGF0ZS5oPgpAQCAt MzI4LDE1ICszMjksMTMgQEAgc3RhdGljIHZvaWQgdm1kX3JlbW92ZV9pcnFfZG9tYWluKHN0cnVj dCB2bWRfZGV2ICp2bWQpCiBzdGF0aWMgY2hhciBfX2lvbWVtICp2bWRfY2ZnX2FkZHIoc3RydWN0 IHZtZF9kZXYgKnZtZCwgc3RydWN0IHBjaV9idXMgKmJ1cywKIAkJCQkgIHVuc2lnbmVkIGludCBk ZXZmbiwgaW50IHJlZywgaW50IGxlbikKIHsKLQljaGFyIF9faW9tZW0gKmFkZHIgPSB2bWQtPmNm Z2JhciArCi0JCQkgICAgICgoYnVzLT5udW1iZXIgLSB2bWQtPmJ1c25fc3RhcnQpIDw8IDIwKSAr Ci0JCQkgICAgIChkZXZmbiA8PCAxMikgKyByZWc7CisJdW5zaWduZWQgaW50IGJ1c25yX2VjYW0g PSBidXMtPm51bWJlciAtIHZtZC0+YnVzbl9zdGFydDsKKwl1MzIgb2Zmc2V0ID0gUENJRV9FQ0FN X09GRlNFVChidXNucl9lY2FtLCBkZXZmbiwgcmVnKTsKIAotCWlmICgoYWRkciAtIHZtZC0+Y2Zn YmFyKSArIGxlbiA+PQotCSAgICByZXNvdXJjZV9zaXplKCZ2bWQtPmRldi0+cmVzb3VyY2VbVk1E X0NGR0JBUl0pKQorCWlmIChvZmZzZXQgKyBsZW4gPj0gcmVzb3VyY2Vfc2l6ZSgmdm1kLT5kZXYt PnJlc291cmNlW1ZNRF9DRkdCQVJdKSkKIAkJcmV0dXJuIE5VTEw7CiAKLQlyZXR1cm4gYWRkcjsK KwlyZXR1cm4gdm1kLT5jZmdiYXIgKyBvZmZzZXQ7CiB9CiAKIC8qCmRpZmYgLS1naXQgYS9kcml2 ZXJzL3BjaS9lY2FtLmMgYi9kcml2ZXJzL3BjaS9lY2FtLmMKaW5kZXggYjU0ZDMyYTMxNjY5Li41 OWY5MWQ0MzQ4NTkgMTAwNjQ0Ci0tLSBhL2RyaXZlcnMvcGNpL2VjYW0uYworKysgYi9kcml2ZXJz L3BjaS9lY2FtLmMKQEAgLTEzMSwyNSArMTMxLDM2IEBAIHZvaWQgX19pb21lbSAqcGNpX2VjYW1f bWFwX2J1cyhzdHJ1Y3QgcGNpX2J1cyAqYnVzLCB1bnNpZ25lZCBpbnQgZGV2Zm4sCiAJCQkgICAg ICAgaW50IHdoZXJlKQogewogCXN0cnVjdCBwY2lfY29uZmlnX3dpbmRvdyAqY2ZnID0gYnVzLT5z eXNkYXRhOworCXVuc2lnbmVkIGludCBidXNfc2hpZnQgPSBjZmctPm9wcy0+YnVzX3NoaWZ0Owog CXVuc2lnbmVkIGludCBkZXZmbl9zaGlmdCA9IGNmZy0+b3BzLT5idXNfc2hpZnQgLSA4OwogCXVu c2lnbmVkIGludCBidXNuID0gYnVzLT5udW1iZXI7CiAJdm9pZCBfX2lvbWVtICpiYXNlOworCXUz MiBidXNfb2Zmc2V0LCBkZXZmbl9vZmZzZXQ7CiAKIAlpZiAoYnVzbiA8IGNmZy0+YnVzci5zdGFy dCB8fCBidXNuID4gY2ZnLT5idXNyLmVuZCkKIAkJcmV0dXJuIE5VTEw7CiAKIAlidXNuIC09IGNm Zy0+YnVzci5zdGFydDsKLQlpZiAocGVyX2J1c19tYXBwaW5nKQorCWlmIChwZXJfYnVzX21hcHBp bmcpIHsKIAkJYmFzZSA9IGNmZy0+d2lucFtidXNuXTsKLQllbHNlCi0JCWJhc2UgPSBjZmctPndp biArIChidXNuIDw8IGNmZy0+b3BzLT5idXNfc2hpZnQpOwotCXJldHVybiBiYXNlICsgKGRldmZu IDw8IGRldmZuX3NoaWZ0KSArIHdoZXJlOworCQlidXNuID0gMDsKKwl9IGVsc2UKKwkJYmFzZSA9 IGNmZy0+d2luOworCisJaWYgKGNmZy0+b3BzLT5idXNfc2hpZnQpIHsKKwkJYnVzX29mZnNldCA9 IChidXNuICYgUENJRV9FQ0FNX0JVU19NQVNLKSA8PCBidXNfc2hpZnQ7CisJCWRldmZuX29mZnNl dCA9IChkZXZmbiAmIFBDSUVfRUNBTV9ERVZGTl9NQVNLKSA8PCBkZXZmbl9zaGlmdDsKKwkJd2hl cmUgJj0gUENJRV9FQ0FNX1JFR19NQVNLOworCisJCXJldHVybiBiYXNlICsgKGJ1c19vZmZzZXQg fCBkZXZmbl9vZmZzZXQgfCB3aGVyZSk7CisJfQorCisJcmV0dXJuIGJhc2UgKyBQQ0lFX0VDQU1f T0ZGU0VUKGJ1c24sIGRldmZuLCB3aGVyZSk7CiB9CiBFWFBPUlRfU1lNQk9MX0dQTChwY2lfZWNh bV9tYXBfYnVzKTsKIAogLyogRUNBTSBvcHMgKi8KIGNvbnN0IHN0cnVjdCBwY2lfZWNhbV9vcHMg cGNpX2dlbmVyaWNfZWNhbV9vcHMgPSB7Ci0JLmJ1c19zaGlmdAk9IDIwLAogCS5wY2lfb3BzCT0g ewogCQkubWFwX2J1cwk9IHBjaV9lY2FtX21hcF9idXMsCiAJCS5yZWFkCQk9IHBjaV9nZW5lcmlj X2NvbmZpZ19yZWFkLApAQCAtMTYxLDcgKzE3Miw2IEBAIEVYUE9SVF9TWU1CT0xfR1BMKHBjaV9n ZW5lcmljX2VjYW1fb3BzKTsKICNpZiBkZWZpbmVkKENPTkZJR19BQ1BJKSAmJiBkZWZpbmVkKENP TkZJR19QQ0lfUVVJUktTKQogLyogRUNBTSBvcHMgZm9yIDMyLWJpdCBhY2Nlc3Mgb25seSAobm9u LWNvbXBsaWFudCkgKi8KIGNvbnN0IHN0cnVjdCBwY2lfZWNhbV9vcHMgcGNpXzMyYl9vcHMgPSB7 Ci0JLmJ1c19zaGlmdAk9IDIwLAogCS5wY2lfb3BzCT0gewogCQkubWFwX2J1cwk9IHBjaV9lY2Ft X21hcF9idXMsCiAJCS5yZWFkCQk9IHBjaV9nZW5lcmljX2NvbmZpZ19yZWFkMzIsCkBAIC0xNzEs NyArMTgxLDYgQEAgY29uc3Qgc3RydWN0IHBjaV9lY2FtX29wcyBwY2lfMzJiX29wcyA9IHsKIAog LyogRUNBTSBvcHMgZm9yIDMyLWJpdCByZWFkIG9ubHkgKG5vbi1jb21wbGlhbnQpICovCiBjb25z dCBzdHJ1Y3QgcGNpX2VjYW1fb3BzIHBjaV8zMmJfcmVhZF9vcHMgPSB7Ci0JLmJ1c19zaGlmdAk9 IDIwLAogCS5wY2lfb3BzCT0gewogCQkubWFwX2J1cwk9IHBjaV9lY2FtX21hcF9idXMsCiAJCS5y ZWFkCQk9IHBjaV9nZW5lcmljX2NvbmZpZ19yZWFkMzIsCmRpZmYgLS1naXQgYS9pbmNsdWRlL2xp bnV4L3BjaS1lY2FtLmggYi9pbmNsdWRlL2xpbnV4L3BjaS1lY2FtLmgKaW5kZXggMDMzY2U3NGYw MmU4Li42NWQzZDgzMDE1YzMgMTAwNjQ0Ci0tLSBhL2luY2x1ZGUvbGludXgvcGNpLWVjYW0uaAor KysgYi9pbmNsdWRlL2xpbnV4L3BjaS1lY2FtLmgKQEAgLTksNiArOSwzMyBAQAogI2luY2x1ZGUg PGxpbnV4L2tlcm5lbC5oPgogI2luY2x1ZGUgPGxpbnV4L3BsYXRmb3JtX2RldmljZS5oPgogCisv KgorICogTWVtb3J5IGFkZHJlc3Mgc2hpZnQgdmFsdWVzIGZvciB0aGUgYnl0ZS1sZXZlbCBhZGRy ZXNzIHRoYXQKKyAqIGNhbiBiZSB1c2VkIHdoZW4gYWNjZXNzaW5nIHRoZSBQQ0kgRXhwcmVzcyBD b25maWd1cmF0aW9uIFNwYWNlLgorICovCisKKy8qCisgKiBFbmhhbmNlZCBDb25maWd1cmF0aW9u IEFjY2VzcyBNZWNoYW5pc20gKEVDQU0pCisgKgorICogU2VlIFBDSSBFeHByZXNzIEJhc2UgU3Bl Y2lmaWNhdGlvbiwgUmV2aXNpb24gNS4wLCBWZXJzaW9uIDEuMCwKKyAqIFNlY3Rpb24gNy4yLjIs IFRhYmxlIDctMSwgcC4gNjc3LgorICovCisjZGVmaW5lIFBDSUVfRUNBTV9CVVNfU0hJRlQJMjAg LyogQnVzIG51bWJlciAqLworI2RlZmluZSBQQ0lFX0VDQU1fREVWRk5fU0hJRlQJMTIgLyogRGV2 aWNlIGFuZCBGdW5jdGlvbiBudW1iZXIgKi8KKworI2RlZmluZSBQQ0lFX0VDQU1fQlVTX01BU0sJ MHhmZgorI2RlZmluZSBQQ0lFX0VDQU1fREVWRk5fTUFTSwkweGZmCisjZGVmaW5lIFBDSUVfRUNB TV9SRUdfTUFTSwkweGZmZiAvKiBMaW1pdCBvZmZzZXQgdG8gYSBtYXhpbXVtIG9mIDRLICovCisK KyNkZWZpbmUgUENJRV9FQ0FNX0JVUyh4KQkoKCh4KSAmIFBDSUVfRUNBTV9CVVNfTUFTSykgPDwg UENJRV9FQ0FNX0JVU19TSElGVCkKKyNkZWZpbmUgUENJRV9FQ0FNX0RFVkZOKHgpCSgoKHgpICYg UENJRV9FQ0FNX0RFVkZOX01BU0spIDw8IFBDSUVfRUNBTV9ERVZGTl9TSElGVCkKKyNkZWZpbmUg UENJRV9FQ0FNX1JFRyh4KQkoKHgpICYgUENJRV9FQ0FNX1JFR19NQVNLKQorCisjZGVmaW5lIFBD SUVfRUNBTV9PRkZTRVQoYnVzLCBkZXZmbiwgd2hlcmUpIFwKKwkoUENJRV9FQ0FNX0JVUyhidXMp IHwgXAorCSBQQ0lFX0VDQU1fREVWRk4oZGV2Zm4pIHwgXAorCSBQQ0lFX0VDQU1fUkVHKHdoZXJl KSkKKwogLyoKICAqIHN0cnVjdCB0byBob2xkIHBjaSBvcHMgYW5kIGJ1cyBzaGlmdCBvZiB0aGUg Y29uZmlnIHdpbmRvdwogICogZm9yIGEgUENJIGNvbnRyb2xsZXIuCi0tIAoyLjI5LjIKCgpfX19f X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fXwpsaW51eC1hcm0ta2Vy bmVsIG1haWxpbmcgbGlzdApsaW51eC1hcm0ta2VybmVsQGxpc3RzLmluZnJhZGVhZC5vcmcKaHR0 cDovL2xpc3RzLmluZnJhZGVhZC5vcmcvbWFpbG1hbi9saXN0aW5mby9saW51eC1hcm0ta2VybmVs Cg==