From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 68011C64E7B for ; Mon, 30 Nov 2020 14:07:08 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id DEC8D206F9 for ; Mon, 30 Nov 2020 14:07:07 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="oUjYXNhU" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org DEC8D206F9 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=lunn.ch Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References:Message-ID: Subject:To:From:Date:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=+prn3rH2fZy7w7NceU90+wdR2KnjDFb3PrU27LP1rrA=; b=oUjYXNhU3HQx3Lv++lMDND5k9 urhh6JLRHafOEoWWobwFsX0a94IHS1n+QWqh3t7sbRwU4rk47mslnXh3rWAN2KLw9EwywjVA0H2it eI4nLx8Ylq0Ye4BUUY4RP3sN48ZFtTJN+RzovTrPnLDmJhwPGQfRcwQZvSvTEZVJkkFKs2mKnICKE 7hnT56ijc6gUCGYQot4/Keq0Kr0J+Vg157RXIdR773TG+GGgKeTSSqGwtKhsDvKoj4WkE9gyLSYew 46SZekfkGH5qwTEHQlWgfkWEWdEGXMpfypGXbpoAidQU4BDh/Go+EkU0rWHQCNVRLh03sAct2qbbb o3Crsihtw==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kjjo2-0001R3-Tt; Mon, 30 Nov 2020 14:05:30 +0000 Received: from vps0.lunn.ch ([185.16.172.187]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1kjjo0-0001Qd-FS for linux-arm-kernel@lists.infradead.org; Mon, 30 Nov 2020 14:05:29 +0000 Received: from andrew by vps0.lunn.ch with local (Exim 4.94) (envelope-from ) id 1kjjno-009Vq6-RZ; Mon, 30 Nov 2020 15:05:16 +0100 Date: Mon, 30 Nov 2020 15:05:16 +0100 From: Andrew Lunn To: Steen Hegelund Subject: Re: [RFC PATCH 1/3] dt-bindings: net: sparx5: Add sparx5-switch bindings Message-ID: <20201130140516.GC2073444@lunn.ch> References: <20201127133307.2969817-1-steen.hegelund@microchip.com> <20201127133307.2969817-2-steen.hegelund@microchip.com> <20201127170052.GV2073444@lunn.ch> <20201130130934.o47mdjiqidtznm2t@mchp-dev-shegelun> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20201130130934.o47mdjiqidtznm2t@mchp-dev-shegelun> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201130_090528_571391_EFCDD2A9 X-CRM114-Status: GOOD ( 20.38 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bjarni Jonasson , Alexandre Belloni , devicetree@vger.kernel.org, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, Microchip Linux Driver Support , Rob Herring , Microsemi List , linux-arm-kernel@lists.infradead.org, Jakub Kicinski , "David S. Miller" , Lars Povlsen Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Mon, Nov 30, 2020 at 02:09:34PM +0100, Steen Hegelund wrote: > On 27.11.2020 18:00, Andrew Lunn wrote: > > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe > > > > > + reg-names: > > > + minItems: 153 > > > + items: > > > + - const: dev2g5_0 > > > + - const: dev5g_0 > > > + - const: pcs5g_br_0 > > > + - const: dev2g5_1 > > > + - const: dev5g_1 > > ... > > > + - const: ana_ac > > > + - const: vop > > > > > + switch: switch@600000000 { > > > + compatible = "microchip,sparx5-switch"; > > > + reg = <0x10004000 0x4000>, /* dev2g5_0 */ > > > + <0x10008000 0x4000>, /* dev5g_0 */ > > > + <0x1000c000 0x4000>, /* pcs5g_br_0 */ > > > + <0x10010000 0x4000>, /* dev2g5_1 */ > > > + <0x10014000 0x4000>, /* dev5g_1 */ > > > > ... > > > > > + <0x11800000 0x100000>, /* ana_l2 */ > > > + <0x11900000 0x100000>, /* ana_ac */ > > > + <0x11a00000 0x100000>; /* vop */ > > > > This is a pretty unusual binding. > > > > Why is it not > > > > reg = <0x10004000 0x1af8000> > > > > and the driver can then break up the memory into its sub ranges? > > > > Andrew > Hi Andrew, > > Since the targets used by the driver is not always in the natural > address order (e.g. the dev2g5_x targets), I thought it best to let the DT > take care of this since this cannot be probed. I am aware that this causes > extra mappings compared to the one-range strategy, but this layout seems more > transparent to me, also when mapped over PCIe. The question is, do you have a device tree usage for this? Are there devices in the family which have the regions in a different order? You can easily move this table into the driver, and let the driver break the region up. That would be normal. Andrew _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-3.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7AE06C64E8A for ; Mon, 30 Nov 2020 14:06:08 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 1988B20855 for ; Mon, 30 Nov 2020 14:06:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725897AbgK3OGH (ORCPT ); Mon, 30 Nov 2020 09:06:07 -0500 Received: from vps0.lunn.ch ([185.16.172.187]:57300 "EHLO vps0.lunn.ch" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725859AbgK3OGH (ORCPT ); Mon, 30 Nov 2020 09:06:07 -0500 Received: from andrew by vps0.lunn.ch with local (Exim 4.94) (envelope-from ) id 1kjjno-009Vq6-RZ; Mon, 30 Nov 2020 15:05:16 +0100 Date: Mon, 30 Nov 2020 15:05:16 +0100 From: Andrew Lunn To: Steen Hegelund Cc: "David S. Miller" , Jakub Kicinski , Rob Herring , Lars Povlsen , Bjarni Jonasson , Microchip Linux Driver Support , Alexandre Belloni , Microsemi List , netdev@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: Re: [RFC PATCH 1/3] dt-bindings: net: sparx5: Add sparx5-switch bindings Message-ID: <20201130140516.GC2073444@lunn.ch> References: <20201127133307.2969817-1-steen.hegelund@microchip.com> <20201127133307.2969817-2-steen.hegelund@microchip.com> <20201127170052.GV2073444@lunn.ch> <20201130130934.o47mdjiqidtznm2t@mchp-dev-shegelun> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20201130130934.o47mdjiqidtznm2t@mchp-dev-shegelun> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Mon, Nov 30, 2020 at 02:09:34PM +0100, Steen Hegelund wrote: > On 27.11.2020 18:00, Andrew Lunn wrote: > > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe > > > > > + reg-names: > > > + minItems: 153 > > > + items: > > > + - const: dev2g5_0 > > > + - const: dev5g_0 > > > + - const: pcs5g_br_0 > > > + - const: dev2g5_1 > > > + - const: dev5g_1 > > ... > > > + - const: ana_ac > > > + - const: vop > > > > > + switch: switch@600000000 { > > > + compatible = "microchip,sparx5-switch"; > > > + reg = <0x10004000 0x4000>, /* dev2g5_0 */ > > > + <0x10008000 0x4000>, /* dev5g_0 */ > > > + <0x1000c000 0x4000>, /* pcs5g_br_0 */ > > > + <0x10010000 0x4000>, /* dev2g5_1 */ > > > + <0x10014000 0x4000>, /* dev5g_1 */ > > > > ... > > > > > + <0x11800000 0x100000>, /* ana_l2 */ > > > + <0x11900000 0x100000>, /* ana_ac */ > > > + <0x11a00000 0x100000>; /* vop */ > > > > This is a pretty unusual binding. > > > > Why is it not > > > > reg = <0x10004000 0x1af8000> > > > > and the driver can then break up the memory into its sub ranges? > > > > Andrew > Hi Andrew, > > Since the targets used by the driver is not always in the natural > address order (e.g. the dev2g5_x targets), I thought it best to let the DT > take care of this since this cannot be probed. I am aware that this causes > extra mappings compared to the one-range strategy, but this layout seems more > transparent to me, also when mapped over PCIe. The question is, do you have a device tree usage for this? Are there devices in the family which have the regions in a different order? You can easily move this table into the driver, and let the driver break the region up. That would be normal. Andrew