From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.2 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 59E80C4361B for ; Tue, 8 Dec 2020 20:21:55 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id DE44C2388C for ; Tue, 8 Dec 2020 20:21:54 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org DE44C2388C Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 036246E9BC; Tue, 8 Dec 2020 20:21:50 +0000 (UTC) Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by gabe.freedesktop.org (Postfix) with ESMTPS id 1C1FD6E9BA; Tue, 8 Dec 2020 20:21:48 +0000 (UTC) IronPort-SDR: HkQRgDd/qwshV8QjO4yOHEPxhOBHNBR+FhNbDvDL4top0gSRaQ9Hm62TAlTvogSzuCA3e/CJSe vdsQxsdh3uIA== X-IronPort-AV: E=McAfee;i="6000,8403,9829"; a="153203533" X-IronPort-AV: E=Sophos;i="5.78,403,1599548400"; d="scan'208";a="153203533" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Dec 2020 12:21:47 -0800 IronPort-SDR: tkKZu7JFX0upUa1i6V0QRI/qbe6crXuDVJ9rq5lpKeli6ycNk9UGwQg4Li9mzHc2Tp6RA3uxUA ezQmlxL97ZEA== X-IronPort-AV: E=Sophos;i="5.78,403,1599548400"; d="scan'208";a="332656720" Received: from labuser-z97x-ud5h.jf.intel.com (HELO labuser-Z97X-UD5H) ([10.165.21.211]) by orsmga003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Dec 2020 12:21:47 -0800 Date: Tue, 8 Dec 2020 12:24:56 -0800 From: "Navare, Manasi" To: Jani Nikula Message-ID: <20201208202456.GC474@labuser-Z97X-UD5H> References: <6843c4f6958619f7389180aa92fded7b9fdbb4ba.1607429866.git.jani.nikula@intel.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <6843c4f6958619f7389180aa92fded7b9fdbb4ba.1607429866.git.jani.nikula@intel.com> User-Agent: Mutt/1.5.24 (2015-08-30) Subject: Re: [Intel-gfx] [PATCH 3/6] drm/i915/dsc: make rc_model_size an encoder defined value X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On Tue, Dec 08, 2020 at 02:33:52PM +0200, Jani Nikula wrote: > Move the intialization of the rc_model_size from the common code into > encoder code, allowing different encoders to specify the size according > to their needs. Keep using the hard coded value in the encoders for now > to make this a non-functional change. > > Cc: Manasi Navare > Cc: Vandita Kulkarni > Signed-off-by: Jani Nikula So still using the hardcoded value since thats in the DSC C model, Looks good to me Reviewed-by: Manasi Navare Manasi > --- > drivers/gpu/drm/i915/display/icl_dsi.c | 3 +++ > drivers/gpu/drm/i915/display/intel_dp.c | 8 ++++++++ > drivers/gpu/drm/i915/display/intel_vdsc.c | 2 -- > 3 files changed, 11 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c > index a9439b415603..676e40172fe9 100644 > --- a/drivers/gpu/drm/i915/display/icl_dsi.c > +++ b/drivers/gpu/drm/i915/display/icl_dsi.c > @@ -1535,6 +1535,9 @@ static int gen11_dsi_dsc_compute_config(struct intel_encoder *encoder, > > vdsc_cfg->convert_rgb = true; > > + /* FIXME: initialize from VBT */ > + vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST; > + > ret = intel_dsc_compute_params(encoder, crtc_state); > if (ret) > return ret; > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c > index cb5e42c3ecd5..b2bc0c8c39c7 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp.c > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > @@ -2289,6 +2289,14 @@ static int intel_dp_dsc_compute_params(struct intel_encoder *encoder, > u8 line_buf_depth; > int ret; > > + /* > + * RC_MODEL_SIZE is currently a constant across all configurations. > + * > + * FIXME: Look into using sink defined DPCD DP_DSC_RC_BUF_BLK_SIZE and > + * DP_DSC_RC_BUF_SIZE for this. > + */ > + vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST; > + > ret = intel_dsc_compute_params(encoder, crtc_state); > if (ret) > return ret; > diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c > index 22d08679844f..f58cc5700784 100644 > --- a/drivers/gpu/drm/i915/display/intel_vdsc.c > +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c > @@ -454,8 +454,6 @@ int intel_dsc_compute_params(struct intel_encoder *encoder, > else if (vdsc_cfg->bits_per_component == 12) > vdsc_cfg->mux_word_size = DSC_MUX_WORD_SIZE_12_BPC; > > - /* RC_MODEL_SIZE is a constant across all configurations */ > - vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST; > /* InitialScaleValue is a 6 bit value with 3 fractional bits (U3.3) */ > vdsc_cfg->initial_scale_value = (vdsc_cfg->rc_model_size << 3) / > (vdsc_cfg->rc_model_size - vdsc_cfg->initial_offset); > -- > 2.20.1 > > _______________________________________________ > dri-devel mailing list > dri-devel@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/dri-devel _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.2 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 31574C4361B for ; Tue, 8 Dec 2020 20:21:51 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id DB0B12388C for ; Tue, 8 Dec 2020 20:21:50 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org DB0B12388C Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id B3B6D6E9BA; Tue, 8 Dec 2020 20:21:49 +0000 (UTC) Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by gabe.freedesktop.org (Postfix) with ESMTPS id 1C1FD6E9BA; Tue, 8 Dec 2020 20:21:48 +0000 (UTC) IronPort-SDR: HkQRgDd/qwshV8QjO4yOHEPxhOBHNBR+FhNbDvDL4top0gSRaQ9Hm62TAlTvogSzuCA3e/CJSe vdsQxsdh3uIA== X-IronPort-AV: E=McAfee;i="6000,8403,9829"; a="153203533" X-IronPort-AV: E=Sophos;i="5.78,403,1599548400"; d="scan'208";a="153203533" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Dec 2020 12:21:47 -0800 IronPort-SDR: tkKZu7JFX0upUa1i6V0QRI/qbe6crXuDVJ9rq5lpKeli6ycNk9UGwQg4Li9mzHc2Tp6RA3uxUA ezQmlxL97ZEA== X-IronPort-AV: E=Sophos;i="5.78,403,1599548400"; d="scan'208";a="332656720" Received: from labuser-z97x-ud5h.jf.intel.com (HELO labuser-Z97X-UD5H) ([10.165.21.211]) by orsmga003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Dec 2020 12:21:47 -0800 Date: Tue, 8 Dec 2020 12:24:56 -0800 From: "Navare, Manasi" To: Jani Nikula Subject: Re: [PATCH 3/6] drm/i915/dsc: make rc_model_size an encoder defined value Message-ID: <20201208202456.GC474@labuser-Z97X-UD5H> References: <6843c4f6958619f7389180aa92fded7b9fdbb4ba.1607429866.git.jani.nikula@intel.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <6843c4f6958619f7389180aa92fded7b9fdbb4ba.1607429866.git.jani.nikula@intel.com> User-Agent: Mutt/1.5.24 (2015-08-30) X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Vandita Kulkarni , intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" On Tue, Dec 08, 2020 at 02:33:52PM +0200, Jani Nikula wrote: > Move the intialization of the rc_model_size from the common code into > encoder code, allowing different encoders to specify the size according > to their needs. Keep using the hard coded value in the encoders for now > to make this a non-functional change. > > Cc: Manasi Navare > Cc: Vandita Kulkarni > Signed-off-by: Jani Nikula So still using the hardcoded value since thats in the DSC C model, Looks good to me Reviewed-by: Manasi Navare Manasi > --- > drivers/gpu/drm/i915/display/icl_dsi.c | 3 +++ > drivers/gpu/drm/i915/display/intel_dp.c | 8 ++++++++ > drivers/gpu/drm/i915/display/intel_vdsc.c | 2 -- > 3 files changed, 11 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c > index a9439b415603..676e40172fe9 100644 > --- a/drivers/gpu/drm/i915/display/icl_dsi.c > +++ b/drivers/gpu/drm/i915/display/icl_dsi.c > @@ -1535,6 +1535,9 @@ static int gen11_dsi_dsc_compute_config(struct intel_encoder *encoder, > > vdsc_cfg->convert_rgb = true; > > + /* FIXME: initialize from VBT */ > + vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST; > + > ret = intel_dsc_compute_params(encoder, crtc_state); > if (ret) > return ret; > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c > index cb5e42c3ecd5..b2bc0c8c39c7 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp.c > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > @@ -2289,6 +2289,14 @@ static int intel_dp_dsc_compute_params(struct intel_encoder *encoder, > u8 line_buf_depth; > int ret; > > + /* > + * RC_MODEL_SIZE is currently a constant across all configurations. > + * > + * FIXME: Look into using sink defined DPCD DP_DSC_RC_BUF_BLK_SIZE and > + * DP_DSC_RC_BUF_SIZE for this. > + */ > + vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST; > + > ret = intel_dsc_compute_params(encoder, crtc_state); > if (ret) > return ret; > diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c > index 22d08679844f..f58cc5700784 100644 > --- a/drivers/gpu/drm/i915/display/intel_vdsc.c > +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c > @@ -454,8 +454,6 @@ int intel_dsc_compute_params(struct intel_encoder *encoder, > else if (vdsc_cfg->bits_per_component == 12) > vdsc_cfg->mux_word_size = DSC_MUX_WORD_SIZE_12_BPC; > > - /* RC_MODEL_SIZE is a constant across all configurations */ > - vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST; > /* InitialScaleValue is a 6 bit value with 3 fractional bits (U3.3) */ > vdsc_cfg->initial_scale_value = (vdsc_cfg->rc_model_size << 3) / > (vdsc_cfg->rc_model_size - vdsc_cfg->initial_offset); > -- > 2.20.1 > > _______________________________________________ > dri-devel mailing list > dri-devel@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/dri-devel _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel