From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.2 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A9170C433FE for ; Thu, 10 Dec 2020 19:33:54 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 4A2F323340 for ; Thu, 10 Dec 2020 19:33:54 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 4A2F323340 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id C57476EB0D; Thu, 10 Dec 2020 19:33:53 +0000 (UTC) Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTPS id 61FA46EB0D for ; Thu, 10 Dec 2020 19:33:52 +0000 (UTC) IronPort-SDR: mJxQDS9xKzrlB5fdPZkxXxkI/PDj/pTuqTG22bAyoD8G4pznzL2lfjToxagK2uv7LBkEq5oq2X ZwVd6MFn/BKQ== X-IronPort-AV: E=McAfee;i="6000,8403,9831"; a="192648248" X-IronPort-AV: E=Sophos;i="5.78,409,1599548400"; d="scan'208";a="192648248" Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Dec 2020 11:33:51 -0800 IronPort-SDR: jp8kMCWV9ssmSiY/g+2bZFK0I6JIkmb8FWcEZxFJw8gRNJ5hhS9L5xaW/6tTlKCiK4tUvJpK4j MshmW598vjHQ== X-IronPort-AV: E=Sophos;i="5.78,409,1599548400"; d="scan'208";a="378021408" Received: from unknown (HELO sdutt-i7) ([10.165.21.147]) by fmsmga003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Dec 2020 11:33:51 -0800 Date: Thu, 10 Dec 2020 11:28:06 -0800 From: Matthew Brost To: Chris Wilson Message-ID: <20201210192806.GB6255@sdutt-i7> References: <20201210080240.24529-1-chris@chris-wilson.co.uk> <20201210080240.24529-18-chris@chris-wilson.co.uk> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20201210080240.24529-18-chris@chris-wilson.co.uk> User-Agent: Mutt/1.9.4 (2018-02-28) Subject: Re: [Intel-gfx] [PATCH 18/21] drm/i915/gt: Add timeline "mode" X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: intel-gfx@lists.freedesktop.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On Thu, Dec 10, 2020 at 08:02:37AM +0000, Chris Wilson wrote: > Explicitly differentiate between the absolute and relative timelines, > and the global HWSP and ppHWSP relative offsets. When using a timeline > that is relative to a known status page, we can replace the absolute > addressing in the commands with indexed variants. > > Signed-off-by: Chris Wilson > --- > drivers/gpu/drm/i915/gt/intel_timeline.c | 21 ++++++++++++++++--- > drivers/gpu/drm/i915/gt/intel_timeline.h | 2 +- > .../gpu/drm/i915/gt/intel_timeline_types.h | 10 +++++++-- > 3 files changed, 27 insertions(+), 6 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gt/intel_timeline.c b/drivers/gpu/drm/i915/gt/intel_timeline.c > index cb20fcbb326b..da0a9659557a 100644 > --- a/drivers/gpu/drm/i915/gt/intel_timeline.c > +++ b/drivers/gpu/drm/i915/gt/intel_timeline.c > @@ -229,7 +229,6 @@ static int intel_timeline_init(struct intel_timeline *timeline, > > timeline->gt = gt; > > - timeline->has_initial_breadcrumb = !hwsp; > timeline->hwsp_cacheline = NULL; > > if (!hwsp) { > @@ -246,13 +245,29 @@ static int intel_timeline_init(struct intel_timeline *timeline, > return PTR_ERR(cl); > } > > + timeline->mode = INTEL_TIMELINE_ABSOLUTE; > timeline->hwsp_cacheline = cl; > timeline->hwsp_offset = cacheline * CACHELINE_BYTES; > > vaddr = page_mask_bits(cl->vaddr); > } else { > - timeline->hwsp_offset = offset; > - vaddr = i915_gem_object_pin_map(hwsp->obj, I915_MAP_WB); > + int preferred; > + > + if (offset & INTEL_TIMELINE_CONTEXT) { > + timeline->mode = INTEL_TIMELINE_CONTEXT; > + timeline->hwsp_offset = > + offset & ~INTEL_TIMELINE_CONTEXT; > + preferred = i915_coherent_map_type(gt->i915); > + } else { > + timeline->mode = INTEL_TIMELINE_GLOBAL; > + timeline->hwsp_offset = offset; > + preferred = I915_MAP_WB; > + } > + > + vaddr = i915_gem_object_pin_map(hwsp->obj, > + preferred | I915_MAP_OVERRIDE); > + if (IS_ERR(vaddr)) > + vaddr = i915_gem_object_pin_map(hwsp->obj, I915_MAP_WC); > if (IS_ERR(vaddr)) > return PTR_ERR(vaddr); > } > diff --git a/drivers/gpu/drm/i915/gt/intel_timeline.h b/drivers/gpu/drm/i915/gt/intel_timeline.h > index deb71a8dbd43..69250de3a814 100644 > --- a/drivers/gpu/drm/i915/gt/intel_timeline.h > +++ b/drivers/gpu/drm/i915/gt/intel_timeline.h > @@ -76,7 +76,7 @@ static inline void intel_timeline_put(struct intel_timeline *timeline) > static inline bool > intel_timeline_has_initial_breadcrumb(const struct intel_timeline *tl) > { > - return tl->has_initial_breadcrumb; > + return tl->mode == INTEL_TIMELINE_ABSOLUTE; > } > > static inline int __intel_timeline_sync_set(struct intel_timeline *tl, > diff --git a/drivers/gpu/drm/i915/gt/intel_timeline_types.h b/drivers/gpu/drm/i915/gt/intel_timeline_types.h > index f187c5aac11c..32c51425a0c4 100644 > --- a/drivers/gpu/drm/i915/gt/intel_timeline_types.h > +++ b/drivers/gpu/drm/i915/gt/intel_timeline_types.h > @@ -20,6 +20,12 @@ struct i915_syncmap; > struct intel_gt; > struct intel_timeline_hwsp; > > +enum intel_timeline_mode { > + INTEL_TIMELINE_ABSOLUTE = 0, > + INTEL_TIMELINE_CONTEXT = BIT(0), > + INTEL_TIMELINE_GLOBAL = BIT(1), > +}; > + Not sure I like these names. How about: INTEL_TIMELINE_ABSOLUTE_GGTT INTEL_TIMELINE_RELATIVE_PPGTT INTEL_TIMELINE_RELATIVE_GGTT Also not convinced we need the 'RELATIVE' modes. See my comments in 'Use indices for writing into relative'. Matt > struct intel_timeline { > u64 fence_context; > u32 seqno; > @@ -45,6 +51,8 @@ struct intel_timeline { > atomic_t pin_count; > atomic_t active_count; > > + enum intel_timeline_mode mode; > + > const u32 *hwsp_seqno; > struct i915_vma *hwsp_ggtt; > u32 hwsp_offset; > @@ -52,8 +60,6 @@ struct intel_timeline { > > struct intel_timeline_cacheline *hwsp_cacheline; > > - bool has_initial_breadcrumb; > - > /** > * List of breadcrumbs associated with GPU requests currently > * outstanding. > -- > 2.20.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx