From mboxrd@z Thu Jan  1 00:00:00 1970
Content-Type: multipart/mixed; boundary="===============4531713883260685821=="
MIME-Version: 1.0
From: kernel test robot <lkp@intel.com>
Subject: Re: [PATCH v2] drm/amdgpu: Do not change amdgpu framebuffer format during page flip
Date: Wed, 30 Dec 2020 19:32:08 +0800
Message-ID: <202012301901.7aUSbRD1-lkp@intel.com>
List-Id: <oe-kbuild.lists.linux.dev>
To: kbuild@lists.01.org

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CC: kbuild-all(a)lists.01.org
In-Reply-To: <20201229211044.109020-1-zhan.liu@amd.com>
References: <20201229211044.109020-1-zhan.liu@amd.com>
TO: Zhan Liu <zhan.liu@amd.com>
TO: amd-gfx(a)lists.freedesktop.org
TO: zhan.liu(a)amd.com
TO: Nikola.Cornij(a)amd.com
TO: Stylon.Wang(a)amd.com
TO: Chao-kai.Wang(a)amd.com
TO: dri-devel(a)lists.freedesktop.org
TO: Nicholas.Kazlauskas(a)amd.com
TO: bas(a)basnieuwenhuizen.nl

Hi Zhan,

Thank you for the patch! Perhaps something to improve:

[auto build test WARNING on linus/master]
[also build test WARNING on v5.11-rc1 next-20201223]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]

url:    https://github.com/0day-ci/linux/commits/Zhan-Liu/drm-amdgpu-Do-not=
-change-amdgpu-framebuffer-format-during-page-flip/20201230-051134
base:   https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git =
dea8dcf2a9fa8cc540136a6cd885c3beece16ec3
:::::: branch date: 14 hours ago
:::::: commit date: 14 hours ago
config: x86_64-randconfig-m031-20201229 (attached as .config)
compiler: gcc-9 (Debian 9.3.0-15) 9.3.0

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
Reported-by: Dan Carpenter <dan.carpenter@oracle.com>

New smatch warnings:
drivers/gpu/drm/amd/amdgpu/amdgpu_display.c:831 convert_tiling_flags_to_mod=
ifier() warn: variable dereferenced before check 'afb->base.format' (see li=
ne 826)

Old smatch warnings:
include/drm/ttm/ttm_bo_driver.h:467 ttm_bo_reserve() warn: inconsistent ret=
urns '*bo->base.resv'.

vim +831 drivers/gpu/drm/amd/amdgpu/amdgpu_display.c

1331e6304f5d924a Bas Nieuwenhuizen 2020-11-11  677  =

08d769151dc9690a Bas Nieuwenhuizen 2020-09-02  678  static int convert_tili=
ng_flags_to_modifier(struct amdgpu_framebuffer *afb)
08d769151dc9690a Bas Nieuwenhuizen 2020-09-02  679  {
08d769151dc9690a Bas Nieuwenhuizen 2020-09-02  680  	struct amdgpu_device *=
adev =3D drm_to_adev(afb->base.dev);
08d769151dc9690a Bas Nieuwenhuizen 2020-09-02  681  	uint64_t modifier =3D =
0;
08d769151dc9690a Bas Nieuwenhuizen 2020-09-02  682  =

08d769151dc9690a Bas Nieuwenhuizen 2020-09-02  683  	if (!afb->tiling_flags=
 || !AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE)) {
08d769151dc9690a Bas Nieuwenhuizen 2020-09-02  684  		modifier =3D DRM_FORM=
AT_MOD_LINEAR;
08d769151dc9690a Bas Nieuwenhuizen 2020-09-02  685  	} else {
08d769151dc9690a Bas Nieuwenhuizen 2020-09-02  686  		int swizzle =3D AMDGP=
U_TILING_GET(afb->tiling_flags, SWIZZLE_MODE);
08d769151dc9690a Bas Nieuwenhuizen 2020-09-02  687  		bool has_xor =3D swiz=
zle >=3D 16;
08d769151dc9690a Bas Nieuwenhuizen 2020-09-02  688  		int block_size_bits;
08d769151dc9690a Bas Nieuwenhuizen 2020-09-02  689  		int version;
08d769151dc9690a Bas Nieuwenhuizen 2020-09-02  690  		int pipe_xor_bits =3D=
 0;
08d769151dc9690a Bas Nieuwenhuizen 2020-09-02  691  		int bank_xor_bits =3D=
 0;
08d769151dc9690a Bas Nieuwenhuizen 2020-09-02  692  		int packers =3D 0;
1331e6304f5d924a Bas Nieuwenhuizen 2020-11-11  693  		int rb =3D 0;
1331e6304f5d924a Bas Nieuwenhuizen 2020-11-11  694  		int pipes =3D ilog2(a=
dev->gfx.config.gb_addr_config_fields.num_pipes);
08d769151dc9690a Bas Nieuwenhuizen 2020-09-02  695  		uint32_t dcc_offset =
=3D AMDGPU_TILING_GET(afb->tiling_flags, DCC_OFFSET_256B);
08d769151dc9690a Bas Nieuwenhuizen 2020-09-02  696  =

08d769151dc9690a Bas Nieuwenhuizen 2020-09-02  697  		switch (swizzle >> 2)=
 {
08d769151dc9690a Bas Nieuwenhuizen 2020-09-02  698  		case 0: /* 256B */
08d769151dc9690a Bas Nieuwenhuizen 2020-09-02  699  			block_size_bits =3D =
8;
08d769151dc9690a Bas Nieuwenhuizen 2020-09-02  700  			break;
08d769151dc9690a Bas Nieuwenhuizen 2020-09-02  701  		case 1: /* 4KiB */
08d769151dc9690a Bas Nieuwenhuizen 2020-09-02  702  		case 5: /* 4KiB _X */
08d769151dc9690a Bas Nieuwenhuizen 2020-09-02  703  			block_size_bits =3D =
12;
08d769151dc9690a Bas Nieuwenhuizen 2020-09-02  704  			break;
08d769151dc9690a Bas Nieuwenhuizen 2020-09-02  705  		case 2: /* 64KiB */
08d769151dc9690a Bas Nieuwenhuizen 2020-09-02  706  		case 4: /* 64 KiB _T =
*/
08d769151dc9690a Bas Nieuwenhuizen 2020-09-02  707  		case 6: /* 64 KiB _X =
*/
08d769151dc9690a Bas Nieuwenhuizen 2020-09-02  708  			block_size_bits =3D =
16;
08d769151dc9690a Bas Nieuwenhuizen 2020-09-02  709  			break;
08d769151dc9690a Bas Nieuwenhuizen 2020-09-02  710  		default:
08d769151dc9690a Bas Nieuwenhuizen 2020-09-02  711  			/* RESERVED or VAR */
08d769151dc9690a Bas Nieuwenhuizen 2020-09-02  712  			return -EINVAL;
08d769151dc9690a Bas Nieuwenhuizen 2020-09-02  713  		}
08d769151dc9690a Bas Nieuwenhuizen 2020-09-02  714  =

08d769151dc9690a Bas Nieuwenhuizen 2020-09-02  715  		if (adev->asic_type >=
=3D CHIP_SIENNA_CICHLID)
08d769151dc9690a Bas Nieuwenhuizen 2020-09-02  716  			version =3D AMD_FMT_=
MOD_TILE_VER_GFX10_RBPLUS;
08d769151dc9690a Bas Nieuwenhuizen 2020-09-02  717  		else if (adev->family=
 =3D=3D AMDGPU_FAMILY_NV)
08d769151dc9690a Bas Nieuwenhuizen 2020-09-02  718  			version =3D AMD_FMT_=
MOD_TILE_VER_GFX10;
08d769151dc9690a Bas Nieuwenhuizen 2020-09-02  719  		else
08d769151dc9690a Bas Nieuwenhuizen 2020-09-02  720  			version =3D AMD_FMT_=
MOD_TILE_VER_GFX9;
08d769151dc9690a Bas Nieuwenhuizen 2020-09-02  721  =

08d769151dc9690a Bas Nieuwenhuizen 2020-09-02  722  		switch (swizzle & 3) {
08d769151dc9690a Bas Nieuwenhuizen 2020-09-02  723  		case 0: /* Z microtil=
ing */
08d769151dc9690a Bas Nieuwenhuizen 2020-09-02  724  			return -EINVAL;
08d769151dc9690a Bas Nieuwenhuizen 2020-09-02  725  		case 1: /* S microtil=
ing */
08d769151dc9690a Bas Nieuwenhuizen 2020-09-02  726  			if (!has_xor)
08d769151dc9690a Bas Nieuwenhuizen 2020-09-02  727  				version =3D AMD_FMT=
_MOD_TILE_VER_GFX9;
08d769151dc9690a Bas Nieuwenhuizen 2020-09-02  728  			break;
08d769151dc9690a Bas Nieuwenhuizen 2020-09-02  729  		case 2:
08d769151dc9690a Bas Nieuwenhuizen 2020-09-02  730  			if (!has_xor && afb-=
>base.format->cpp[0] !=3D 4)
08d769151dc9690a Bas Nieuwenhuizen 2020-09-02  731  				version =3D AMD_FMT=
_MOD_TILE_VER_GFX9;
08d769151dc9690a Bas Nieuwenhuizen 2020-09-02  732  			break;
08d769151dc9690a Bas Nieuwenhuizen 2020-09-02  733  		case 3:
08d769151dc9690a Bas Nieuwenhuizen 2020-09-02  734  			break;
08d769151dc9690a Bas Nieuwenhuizen 2020-09-02  735  		}
08d769151dc9690a Bas Nieuwenhuizen 2020-09-02  736  =

08d769151dc9690a Bas Nieuwenhuizen 2020-09-02  737  		if (has_xor) {
08d769151dc9690a Bas Nieuwenhuizen 2020-09-02  738  			switch (version) {
08d769151dc9690a Bas Nieuwenhuizen 2020-09-02  739  			case AMD_FMT_MOD_TIL=
E_VER_GFX10_RBPLUS:
1331e6304f5d924a Bas Nieuwenhuizen 2020-11-11  740  				pipe_xor_bits =3D m=
in(block_size_bits - 8, pipes);
08d769151dc9690a Bas Nieuwenhuizen 2020-09-02  741  				packers =3D min(blo=
ck_size_bits - 8 - pipe_xor_bits,
08d769151dc9690a Bas Nieuwenhuizen 2020-09-02  742  					      ilog2(adev->=
gfx.config.gb_addr_config_fields.num_pkrs));
08d769151dc9690a Bas Nieuwenhuizen 2020-09-02  743  				break;
08d769151dc9690a Bas Nieuwenhuizen 2020-09-02  744  			case AMD_FMT_MOD_TIL=
E_VER_GFX10:
1331e6304f5d924a Bas Nieuwenhuizen 2020-11-11  745  				pipe_xor_bits =3D m=
in(block_size_bits - 8, pipes);
08d769151dc9690a Bas Nieuwenhuizen 2020-09-02  746  				break;
08d769151dc9690a Bas Nieuwenhuizen 2020-09-02  747  			case AMD_FMT_MOD_TIL=
E_VER_GFX9:
1331e6304f5d924a Bas Nieuwenhuizen 2020-11-11  748  				rb =3D ilog2(adev->=
gfx.config.gb_addr_config_fields.num_se) +
1331e6304f5d924a Bas Nieuwenhuizen 2020-11-11  749  				     ilog2(adev->gf=
x.config.gb_addr_config_fields.num_rb_per_se);
1331e6304f5d924a Bas Nieuwenhuizen 2020-11-11  750  				pipe_xor_bits =3D m=
in(block_size_bits - 8, pipes +
08d769151dc9690a Bas Nieuwenhuizen 2020-09-02  751  						    ilog2(adev->g=
fx.config.gb_addr_config_fields.num_se));
08d769151dc9690a Bas Nieuwenhuizen 2020-09-02  752  				bank_xor_bits =3D m=
in(block_size_bits - 8 - pipe_xor_bits,
08d769151dc9690a Bas Nieuwenhuizen 2020-09-02  753  						    ilog2(adev->g=
fx.config.gb_addr_config_fields.num_banks));
08d769151dc9690a Bas Nieuwenhuizen 2020-09-02  754  				break;
08d769151dc9690a Bas Nieuwenhuizen 2020-09-02  755  			}
08d769151dc9690a Bas Nieuwenhuizen 2020-09-02  756  		}
08d769151dc9690a Bas Nieuwenhuizen 2020-09-02  757  =

08d769151dc9690a Bas Nieuwenhuizen 2020-09-02  758  		modifier =3D AMD_FMT_=
MOD |
08d769151dc9690a Bas Nieuwenhuizen 2020-09-02  759  			   AMD_FMT_MOD_SET(T=
ILE, AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE)) |
08d769151dc9690a Bas Nieuwenhuizen 2020-09-02  760  			   AMD_FMT_MOD_SET(T=
ILE_VERSION, version) |
08d769151dc9690a Bas Nieuwenhuizen 2020-09-02  761  			   AMD_FMT_MOD_SET(P=
IPE_XOR_BITS, pipe_xor_bits) |
08d769151dc9690a Bas Nieuwenhuizen 2020-09-02  762  			   AMD_FMT_MOD_SET(B=
ANK_XOR_BITS, bank_xor_bits) |
08d769151dc9690a Bas Nieuwenhuizen 2020-09-02  763  			   AMD_FMT_MOD_SET(P=
ACKERS, packers);
08d769151dc9690a Bas Nieuwenhuizen 2020-09-02  764  =

08d769151dc9690a Bas Nieuwenhuizen 2020-09-02  765  		if (dcc_offset !=3D 0=
) {
08d769151dc9690a Bas Nieuwenhuizen 2020-09-02  766  			bool dcc_i64b =3D AM=
DGPU_TILING_GET(afb->tiling_flags, DCC_INDEPENDENT_64B) !=3D 0;
08d769151dc9690a Bas Nieuwenhuizen 2020-09-02  767  			bool dcc_i128b =3D v=
ersion >=3D AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS;
816853f9dc4057b6 Bas Nieuwenhuizen 2020-11-11  768  			const struct drm_for=
mat_info *format_info;
1331e6304f5d924a Bas Nieuwenhuizen 2020-11-11  769  			u64 render_dcc_offse=
t;
08d769151dc9690a Bas Nieuwenhuizen 2020-09-02  770  =

08d769151dc9690a Bas Nieuwenhuizen 2020-09-02  771  			/* Enable constant e=
ncode on RAVEN2 and later. */
08d769151dc9690a Bas Nieuwenhuizen 2020-09-02  772  			bool dcc_constant_en=
code =3D adev->asic_type > CHIP_RAVEN ||
08d769151dc9690a Bas Nieuwenhuizen 2020-09-02  773  						   (adev->asic_ty=
pe =3D=3D CHIP_RAVEN &&
08d769151dc9690a Bas Nieuwenhuizen 2020-09-02  774  						    adev->externa=
l_rev_id >=3D 0x81);
08d769151dc9690a Bas Nieuwenhuizen 2020-09-02  775  =

08d769151dc9690a Bas Nieuwenhuizen 2020-09-02  776  			int max_cblock_size =
=3D dcc_i64b ? AMD_FMT_MOD_DCC_BLOCK_64B :
08d769151dc9690a Bas Nieuwenhuizen 2020-09-02  777  					      dcc_i128b ? =
AMD_FMT_MOD_DCC_BLOCK_128B :
08d769151dc9690a Bas Nieuwenhuizen 2020-09-02  778  					      AMD_FMT_MOD_=
DCC_BLOCK_256B;
08d769151dc9690a Bas Nieuwenhuizen 2020-09-02  779  =

08d769151dc9690a Bas Nieuwenhuizen 2020-09-02  780  			modifier |=3D AMD_FM=
T_MOD_SET(DCC, 1) |
08d769151dc9690a Bas Nieuwenhuizen 2020-09-02  781  				    AMD_FMT_MOD_SET=
(DCC_CONSTANT_ENCODE, dcc_constant_encode) |
08d769151dc9690a Bas Nieuwenhuizen 2020-09-02  782  				    AMD_FMT_MOD_SET=
(DCC_INDEPENDENT_64B, dcc_i64b) |
08d769151dc9690a Bas Nieuwenhuizen 2020-09-02  783  				    AMD_FMT_MOD_SET=
(DCC_INDEPENDENT_128B, dcc_i128b) |
08d769151dc9690a Bas Nieuwenhuizen 2020-09-02  784  				    AMD_FMT_MOD_SET=
(DCC_MAX_COMPRESSED_BLOCK, max_cblock_size);
08d769151dc9690a Bas Nieuwenhuizen 2020-09-02  785  =

08d769151dc9690a Bas Nieuwenhuizen 2020-09-02  786  			afb->base.offsets[1]=
 =3D dcc_offset * 256 + afb->base.offsets[0];
1331e6304f5d924a Bas Nieuwenhuizen 2020-11-11  787  			afb->base.pitches[1]=
 =3D
1331e6304f5d924a Bas Nieuwenhuizen 2020-11-11  788  				AMDGPU_TILING_GET(a=
fb->tiling_flags, DCC_PITCH_MAX) + 1;
1331e6304f5d924a Bas Nieuwenhuizen 2020-11-11  789  =

1331e6304f5d924a Bas Nieuwenhuizen 2020-11-11  790  			/*
1331e6304f5d924a Bas Nieuwenhuizen 2020-11-11  791  			 * If the userspace =
driver uses retiling the tiling flags do not contain
1331e6304f5d924a Bas Nieuwenhuizen 2020-11-11  792  			 * info on the rende=
rable DCC buffer. Luckily the opaque metadata contains
1331e6304f5d924a Bas Nieuwenhuizen 2020-11-11  793  			 * the info so we ca=
n try to extract it. The kernel does not use this info
1331e6304f5d924a Bas Nieuwenhuizen 2020-11-11  794  			 * but we should con=
vert it to a modifier plane for getfb2, so the
1331e6304f5d924a Bas Nieuwenhuizen 2020-11-11  795  			 * userspace driver =
that gets it doesn't have to juggle around another DCC
1331e6304f5d924a Bas Nieuwenhuizen 2020-11-11  796  			 * plane internally.
1331e6304f5d924a Bas Nieuwenhuizen 2020-11-11  797  			 */
1331e6304f5d924a Bas Nieuwenhuizen 2020-11-11  798  			if (extract_render_d=
cc_offset(adev, afb->base.obj[0],
1331e6304f5d924a Bas Nieuwenhuizen 2020-11-11  799  						      &render_dcc=
_offset) =3D=3D 0 &&
1331e6304f5d924a Bas Nieuwenhuizen 2020-11-11  800  			    render_dcc_offse=
t !=3D 0 &&
1331e6304f5d924a Bas Nieuwenhuizen 2020-11-11  801  			    render_dcc_offse=
t !=3D afb->base.offsets[1] &&
1331e6304f5d924a Bas Nieuwenhuizen 2020-11-11  802  			    render_dcc_offse=
t < UINT_MAX) {
1331e6304f5d924a Bas Nieuwenhuizen 2020-11-11  803  				uint32_t dcc_block_=
bits;  /* of base surface data */
816853f9dc4057b6 Bas Nieuwenhuizen 2020-11-11  804  =

1331e6304f5d924a Bas Nieuwenhuizen 2020-11-11  805  				modifier |=3D AMD_F=
MT_MOD_SET(DCC_RETILE, 1);
1331e6304f5d924a Bas Nieuwenhuizen 2020-11-11  806  				afb->base.offsets[2=
] =3D render_dcc_offset;
1331e6304f5d924a Bas Nieuwenhuizen 2020-11-11  807  =

1331e6304f5d924a Bas Nieuwenhuizen 2020-11-11  808  				if (adev->family >=
=3D AMDGPU_FAMILY_NV) {
1331e6304f5d924a Bas Nieuwenhuizen 2020-11-11  809  					int extra_pipe =3D=
 0;
1331e6304f5d924a Bas Nieuwenhuizen 2020-11-11  810  =

1331e6304f5d924a Bas Nieuwenhuizen 2020-11-11  811  					if (adev->asic_typ=
e >=3D CHIP_SIENNA_CICHLID &&
1331e6304f5d924a Bas Nieuwenhuizen 2020-11-11  812  					    pipes =3D=3D p=
ackers && pipes > 1)
1331e6304f5d924a Bas Nieuwenhuizen 2020-11-11  813  						extra_pipe =3D 1;
1331e6304f5d924a Bas Nieuwenhuizen 2020-11-11  814  =

1331e6304f5d924a Bas Nieuwenhuizen 2020-11-11  815  					dcc_block_bits =3D=
 max(20, 16 + pipes + extra_pipe);
1331e6304f5d924a Bas Nieuwenhuizen 2020-11-11  816  				} else {
1331e6304f5d924a Bas Nieuwenhuizen 2020-11-11  817  					modifier |=3D AMD_=
FMT_MOD_SET(RB, rb) |
1331e6304f5d924a Bas Nieuwenhuizen 2020-11-11  818  						    AMD_FMT_MOD_S=
ET(PIPE, pipes);
1331e6304f5d924a Bas Nieuwenhuizen 2020-11-11  819  					dcc_block_bits =3D=
 max(20, 18 + rb);
1331e6304f5d924a Bas Nieuwenhuizen 2020-11-11  820  				}
1331e6304f5d924a Bas Nieuwenhuizen 2020-11-11  821  =

1331e6304f5d924a Bas Nieuwenhuizen 2020-11-11  822  				dcc_block_bits -=3D=
 ilog2(afb->base.format->cpp[0]);
1331e6304f5d924a Bas Nieuwenhuizen 2020-11-11  823  				afb->base.pitches[2=
] =3D ALIGN(afb->base.width,
1331e6304f5d924a Bas Nieuwenhuizen 2020-11-11  824  							     1u << ((dcc=
_block_bits + 1) / 2));
1331e6304f5d924a Bas Nieuwenhuizen 2020-11-11  825  			}
816853f9dc4057b6 Bas Nieuwenhuizen 2020-11-11 @826  			format_info =3D amdg=
pu_lookup_format_info(afb->base.format->format,
816853f9dc4057b6 Bas Nieuwenhuizen 2020-11-11  827  								modifier);
816853f9dc4057b6 Bas Nieuwenhuizen 2020-11-11  828  			if (!format_info)
816853f9dc4057b6 Bas Nieuwenhuizen 2020-11-11  829  				return -EINVAL;
816853f9dc4057b6 Bas Nieuwenhuizen 2020-11-11  830  =

0a6703fd10d106b3 Zhan Liu          2020-12-29 @831  			if (!afb->base.forma=
t)
816853f9dc4057b6 Bas Nieuwenhuizen 2020-11-11  832  				afb->base.format =
=3D format_info;
08d769151dc9690a Bas Nieuwenhuizen 2020-09-02  833  		}
08d769151dc9690a Bas Nieuwenhuizen 2020-09-02  834  	}
08d769151dc9690a Bas Nieuwenhuizen 2020-09-02  835  =

08d769151dc9690a Bas Nieuwenhuizen 2020-09-02  836  	afb->base.modifier =3D=
 modifier;
08d769151dc9690a Bas Nieuwenhuizen 2020-09-02  837  	afb->base.flags |=3D D=
RM_MODE_FB_MODIFIERS;
08d769151dc9690a Bas Nieuwenhuizen 2020-09-02  838  	return 0;
08d769151dc9690a Bas Nieuwenhuizen 2020-09-02  839  }
08d769151dc9690a Bas Nieuwenhuizen 2020-09-02  840  =


---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org

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--===============4531713883260685821==--