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Thu, 31 Dec 2020 07:57:17 -0800 (PST) Received: from robh.at.kernel.org ([64.188.179.253]) by smtp.gmail.com with ESMTPSA id l5sm11198656otj.57.2020.12.31.07.57.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 31 Dec 2020 07:57:17 -0800 (PST) Received: (nullmailer pid 1863518 invoked by uid 1000); Thu, 31 Dec 2020 15:57:15 -0000 Date: Thu, 31 Dec 2020 08:57:15 -0700 From: Rob Herring To: Nick Fan Subject: Re: [PATCH 1/2] dt-bindings: Convert Arm Mali Valhall GPU to DT schema Message-ID: <20201231155715.GA1852831@robh.at.kernel.org> References: <20201224123119.26504-1-Nick.Fan@mediatek.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20201224123119.26504-1-Nick.Fan@mediatek.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201231_105722_573105_015A164E X-CRM114-Status: GOOD ( 19.96 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, srv_heupstream@mediatek.com, David Airlie , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Project_Global_Chrome_Upstream_Group@mediatek.com, linux-mediatek@lists.infradead.org, Daniel Vetter , Matthias Brugger , linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org On Thu, Dec 24, 2020 at 08:31:18PM +0800, Nick Fan wrote: > Convert the Arm Valhall GPU binding to DT schema format. Convert? There's no existing binding. > > Define a compatible string for the Mali Valhall GPU > for Mediatek's SoC platform. > > Signed-off-by: Nick Fan > --- > .../bindings/gpu/arm,mali-valhall.yaml | 252 ++++++++++++++++++ > 1 file changed, 252 insertions(+) > create mode 100644 Documentation/devicetree/bindings/gpu/arm,mali-valhall.yaml > > diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-valhall.yaml b/Documentation/devicetree/bindings/gpu/arm,mali-valhall.yaml > new file mode 100644 > index 000000000000..3dba202bec95 > --- /dev/null > +++ b/Documentation/devicetree/bindings/gpu/arm,mali-valhall.yaml > @@ -0,0 +1,252 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +# Copyright (c) 2020 MediaTek Inc. > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/gpu/arm,mali-vallhall.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: ARM Mali Valhall GPU > + > +maintainers: > + - Rob Herring > + > +properties: > + $nodename: > + pattern: '^gpu@[a-f0-9]+$' > + > + compatible: > + items: > + - enum: > + - mediatek,mt8192-mali > + - const: arm,mali-valhall # Mali Valhall GPU model/revision is fully discoverable > + > + reg: > + maxItems: 1 > + > + interrupts: > + items: > + - description: GPU interrupt > + - description: MMU interrupt > + - description: Job interrupt > + > + interrupt-names: > + items: > + - const: gpu > + - const: mmu > + - const: job > + > + clocks: > + minItems: 1 > + > + power-domains: > + minItems: 1 > + maxItems: 5 > + > + mali-supply: true > + sram-supply: true > + > + operating-points-v2: true > + > + "#cooling-cells": > + const: 2 > + > +required: > + - compatible > + - reg > + - interrupts > + - interrupt-names > + - clocks > + > +additionalProperties: false > + > +allOf: > + - if: > + properties: > + compatible: > + contains: > + const: mediatek,mt8192-mali > + then: > + properties: > + sram-supply: true No need for this line. > + power-domains: > + description: > + List of phandle and PM domain specifier as documented in > + Documentation/devicetree/bindings/power/power_domain.txt No need re-describe a common property. > + minItems: 5 > + maxItems: 5 blank line between DT properties. > + power-domain-names: > + items: > + - const: core0 > + - const: core1 > + - const: core2 > + - const: core3 > + - const: core4 > + > + required: > + - sram-supply > + - power-domains > + > +examples: > + - | > + #include > + #include > + > + gpu@13000000 { > + compatible = "mediatek,mt8192-mali", "arm,mali-valhall"; > + reg = <0x13000000 0x4000>; > + interrupts = > + , > + , > + ; > + interrupt-names = > + "gpu", > + "mmu", > + "job"; > + > + clocks = <&mfgcfg 0>; > + > + power-domains = > + <&scpsys 4>, > + <&scpsys 5>, > + <&scpsys 6>, > + <&scpsys 7>, > + <&scpsys 8>; > + > + operating-points-v2 = <&gpu_opp_table>; > + mali-supply = <&mt6315_7_vbuck1>; > + sram-supply = <&mt6359_vsram_others_ldo_reg>; > + }; > + > + gpu_opp_table: opp_table0 { Make this a child of the gpu node. Node name should be just 'opp-table'. > + compatible = "operating-points-v2"; > + opp-shared; > + > + opp-358000000 { > + opp-hz = /bits/ 64 <358000000>; > + opp-hz-real = /bits/ 64 <358000000>, I don't recall this being an OPP property. > + /bits/ 64 <358000000>; > + opp-microvolt = <606250>, > + <750000>; > + }; > + > + opp-399000000 { > + opp-hz = /bits/ 64 <399000000>; > + opp-hz-real = /bits/ 64 <399000000>, > + /bits/ 64 <399000000>; > + opp-microvolt = <618750>, > + <750000>; > + }; > + > + opp-440000000 { > + opp-hz = /bits/ 64 <440000000>; > + opp-hz-real = /bits/ 64 <440000000>, > + /bits/ 64 <440000000>; > + opp-microvolt = <631250>, > + <750000>; > + }; > + > + opp-482000000 { > + opp-hz = /bits/ 64 <482000000>; > + opp-hz-real = /bits/ 64 <482000000>, > + /bits/ 64 <482000000>; > + opp-microvolt = <643750>, > + <750000>; > + }; > + > + opp-523000000 { > + opp-hz = /bits/ 64 <523000000>; > + opp-hz-real = /bits/ 64 <523000000>, > + /bits/ 64 <523000000>; > + opp-microvolt = <656250>, > + <750000>; > + }; > + > + opp-564000000 { > + opp-hz = /bits/ 64 <564000000>; > + opp-hz-real = /bits/ 64 <564000000>, > + /bits/ 64 <564000000>; > + opp-microvolt = <668750>, > + <750000>; > + }; > + > + opp-605000000 { > + opp-hz = /bits/ 64 <605000000>; > + opp-hz-real = /bits/ 64 <605000000>, > + /bits/ 64 <605000000>; > + opp-microvolt = <681250>, > + <750000>; > + }; > + > + opp-647000000 { > + opp-hz = /bits/ 64 <647000000>; > + opp-hz-real = /bits/ 64 <647000000>, > + /bits/ 64 <647000000>; > + opp-microvolt = <693750>, > + <750000>; > + }; > + > + opp-688000000 { > + opp-hz = /bits/ 64 <688000000>; > + opp-hz-real = /bits/ 64 <688000000>, > + /bits/ 64 <688000000>; > + opp-microvolt = <706250>, > + <750000>; > + }; > + > + opp-724000000 { > + opp-hz = /bits/ 64 <724000000>; > + opp-hz-real = /bits/ 64 <724000000>, > + /bits/ 64 <724000000>; > + opp-microvolt = <725000>, > + <750000>; > + }; > + > + opp-760000000 { > + opp-hz = /bits/ 64 <760000000>; > + opp-hz-real = /bits/ 64 <760000000>, > + /bits/ 64 <760000000>; > + opp-microvolt = <743750>, > + <750000>; > + }; > + > + opp-795000000 { > + opp-hz = /bits/ 64 <795000000>; > + opp-hz-real = /bits/ 64 <795000000>, > + /bits/ 64 <795000000>; > + opp-microvolt = <762500>, > + <762500>; > + }; > + > + opp-831000000 { > + opp-hz = /bits/ 64 <831000000>; > + opp-hz-real = /bits/ 64 <831000000>, > + /bits/ 64 <831000000>; > + opp-microvolt = <781250>, > + <781250>; > + }; > + > + opp-855000000 { > + opp-hz = /bits/ 64 <855000000>; > + opp-hz-real = /bits/ 64 <855000000>, > + /bits/ 64 <855000000>; > + opp-microvolt = <793750>, > + <793750>; > + }; > + > + opp-902000000 { > + opp-hz = /bits/ 64 <902000000>; > + opp-hz-real = /bits/ 64 <902000000>, > + /bits/ 64 <902000000>; > + opp-microvolt = <818750>, > + <818750>; > + }; > + > + opp-950000000 { > + opp-hz = /bits/ 64 <950000000>; > + opp-hz-real = /bits/ 64 <950000000>, > + /bits/ 64 <950000000>; > + opp-microvolt = <843750>, > + <843750>; > + }; > + }; > +... > -- > 2.18.0 > _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.0 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6BD34C433DB for ; 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Thu, 31 Dec 2020 15:57:15 -0000 Date: Thu, 31 Dec 2020 08:57:15 -0700 From: Rob Herring To: Nick Fan Subject: Re: [PATCH 1/2] dt-bindings: Convert Arm Mali Valhall GPU to DT schema Message-ID: <20201231155715.GA1852831@robh.at.kernel.org> References: <20201224123119.26504-1-Nick.Fan@mediatek.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20201224123119.26504-1-Nick.Fan@mediatek.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201231_105722_573105_015A164E X-CRM114-Status: GOOD ( 19.96 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, srv_heupstream@mediatek.com, David Airlie , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Project_Global_Chrome_Upstream_Group@mediatek.com, linux-mediatek@lists.infradead.org, Daniel Vetter , Matthias Brugger , linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu, Dec 24, 2020 at 08:31:18PM +0800, Nick Fan wrote: > Convert the Arm Valhall GPU binding to DT schema format. Convert? There's no existing binding. > > Define a compatible string for the Mali Valhall GPU > for Mediatek's SoC platform. > > Signed-off-by: Nick Fan > --- > .../bindings/gpu/arm,mali-valhall.yaml | 252 ++++++++++++++++++ > 1 file changed, 252 insertions(+) > create mode 100644 Documentation/devicetree/bindings/gpu/arm,mali-valhall.yaml > > diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-valhall.yaml b/Documentation/devicetree/bindings/gpu/arm,mali-valhall.yaml > new file mode 100644 > index 000000000000..3dba202bec95 > --- /dev/null > +++ b/Documentation/devicetree/bindings/gpu/arm,mali-valhall.yaml > @@ -0,0 +1,252 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +# Copyright (c) 2020 MediaTek Inc. > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/gpu/arm,mali-vallhall.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: ARM Mali Valhall GPU > + > +maintainers: > + - Rob Herring > + > +properties: > + $nodename: > + pattern: '^gpu@[a-f0-9]+$' > + > + compatible: > + items: > + - enum: > + - mediatek,mt8192-mali > + - const: arm,mali-valhall # Mali Valhall GPU model/revision is fully discoverable > + > + reg: > + maxItems: 1 > + > + interrupts: > + items: > + - description: GPU interrupt > + - description: MMU interrupt > + - description: Job interrupt > + > + interrupt-names: > + items: > + - const: gpu > + - const: mmu > + - const: job > + > + clocks: > + minItems: 1 > + > + power-domains: > + minItems: 1 > + maxItems: 5 > + > + mali-supply: true > + sram-supply: true > + > + operating-points-v2: true > + > + "#cooling-cells": > + const: 2 > + > +required: > + - compatible > + - reg > + - interrupts > + - interrupt-names > + - clocks > + > +additionalProperties: false > + > +allOf: > + - if: > + properties: > + compatible: > + contains: > + const: mediatek,mt8192-mali > + then: > + properties: > + sram-supply: true No need for this line. > + power-domains: > + description: > + List of phandle and PM domain specifier as documented in > + Documentation/devicetree/bindings/power/power_domain.txt No need re-describe a common property. > + minItems: 5 > + maxItems: 5 blank line between DT properties. > + power-domain-names: > + items: > + - const: core0 > + - const: core1 > + - const: core2 > + - const: core3 > + - const: core4 > + > + required: > + - sram-supply > + - power-domains > + > +examples: > + - | > + #include > + #include > + > + gpu@13000000 { > + compatible = "mediatek,mt8192-mali", "arm,mali-valhall"; > + reg = <0x13000000 0x4000>; > + interrupts = > + , > + , > + ; > + interrupt-names = > + "gpu", > + "mmu", > + "job"; > + > + clocks = <&mfgcfg 0>; > + > + power-domains = > + <&scpsys 4>, > + <&scpsys 5>, > + <&scpsys 6>, > + <&scpsys 7>, > + <&scpsys 8>; > + > + operating-points-v2 = <&gpu_opp_table>; > + mali-supply = <&mt6315_7_vbuck1>; > + sram-supply = <&mt6359_vsram_others_ldo_reg>; > + }; > + > + gpu_opp_table: opp_table0 { Make this a child of the gpu node. Node name should be just 'opp-table'. > + compatible = "operating-points-v2"; > + opp-shared; > + > + opp-358000000 { > + opp-hz = /bits/ 64 <358000000>; > + opp-hz-real = /bits/ 64 <358000000>, I don't recall this being an OPP property. > + /bits/ 64 <358000000>; > + opp-microvolt = <606250>, > + <750000>; > + }; > + > + opp-399000000 { > + opp-hz = /bits/ 64 <399000000>; > + opp-hz-real = /bits/ 64 <399000000>, > + /bits/ 64 <399000000>; > + opp-microvolt = <618750>, > + <750000>; > + }; > + > + opp-440000000 { > + opp-hz = /bits/ 64 <440000000>; > + opp-hz-real = /bits/ 64 <440000000>, > + /bits/ 64 <440000000>; > + opp-microvolt = <631250>, > + <750000>; > + }; > + > + opp-482000000 { > + opp-hz = /bits/ 64 <482000000>; > + opp-hz-real = /bits/ 64 <482000000>, > + /bits/ 64 <482000000>; > + opp-microvolt = <643750>, > + <750000>; > + }; > + > + opp-523000000 { > + opp-hz = /bits/ 64 <523000000>; > + opp-hz-real = /bits/ 64 <523000000>, > + /bits/ 64 <523000000>; > + opp-microvolt = <656250>, > + <750000>; > + }; > + > + opp-564000000 { > + opp-hz = /bits/ 64 <564000000>; > + opp-hz-real = /bits/ 64 <564000000>, > + /bits/ 64 <564000000>; > + opp-microvolt = <668750>, > + <750000>; > + }; > + > + opp-605000000 { > + opp-hz = /bits/ 64 <605000000>; > + opp-hz-real = /bits/ 64 <605000000>, > + /bits/ 64 <605000000>; > + opp-microvolt = <681250>, > + <750000>; > + }; > + > + opp-647000000 { > + opp-hz = /bits/ 64 <647000000>; > + opp-hz-real = /bits/ 64 <647000000>, > + /bits/ 64 <647000000>; > + opp-microvolt = <693750>, > + <750000>; > + }; > + > + opp-688000000 { > + opp-hz = /bits/ 64 <688000000>; > + opp-hz-real = /bits/ 64 <688000000>, > + /bits/ 64 <688000000>; > + opp-microvolt = <706250>, > + <750000>; > + }; > + > + opp-724000000 { > + opp-hz = /bits/ 64 <724000000>; > + opp-hz-real = /bits/ 64 <724000000>, > + /bits/ 64 <724000000>; > + opp-microvolt = <725000>, > + <750000>; > + }; > + > + opp-760000000 { > + opp-hz = /bits/ 64 <760000000>; > + opp-hz-real = /bits/ 64 <760000000>, > + /bits/ 64 <760000000>; > + opp-microvolt = <743750>, > + <750000>; > + }; > + > + opp-795000000 { > + opp-hz = /bits/ 64 <795000000>; > + opp-hz-real = /bits/ 64 <795000000>, > + /bits/ 64 <795000000>; > + opp-microvolt = <762500>, > + <762500>; > + }; > + > + opp-831000000 { > + opp-hz = /bits/ 64 <831000000>; > + opp-hz-real = /bits/ 64 <831000000>, > + /bits/ 64 <831000000>; > + opp-microvolt = <781250>, > + <781250>; > + }; > + > + opp-855000000 { > + opp-hz = /bits/ 64 <855000000>; > + opp-hz-real = /bits/ 64 <855000000>, > + /bits/ 64 <855000000>; > + opp-microvolt = <793750>, > + <793750>; > + }; > + > + opp-902000000 { > + opp-hz = /bits/ 64 <902000000>; > + opp-hz-real = /bits/ 64 <902000000>, > + /bits/ 64 <902000000>; > + opp-microvolt = <818750>, > + <818750>; > + }; > + > + opp-950000000 { > + opp-hz = /bits/ 64 <950000000>; > + opp-hz-real = /bits/ 64 <950000000>, > + /bits/ 64 <950000000>; > + opp-microvolt = <843750>, > + <843750>; > + }; > + }; > +... > -- > 2.18.0 > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.0 required=3.0 tests=BAYES_00,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 37ADAC433E0 for ; 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Thu, 31 Dec 2020 07:57:17 -0800 (PST) Received: from robh.at.kernel.org ([64.188.179.253]) by smtp.gmail.com with ESMTPSA id l5sm11198656otj.57.2020.12.31.07.57.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 31 Dec 2020 07:57:17 -0800 (PST) Received: (nullmailer pid 1863518 invoked by uid 1000); Thu, 31 Dec 2020 15:57:15 -0000 Date: Thu, 31 Dec 2020 08:57:15 -0700 From: Rob Herring To: Nick Fan Cc: Matthias Brugger , David Airlie , Daniel Vetter , dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, srv_heupstream@mediatek.com, linux-mediatek@lists.infradead.org, Project_Global_Chrome_Upstream_Group@mediatek.com, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org Subject: Re: [PATCH 1/2] dt-bindings: Convert Arm Mali Valhall GPU to DT schema Message-ID: <20201231155715.GA1852831@robh.at.kernel.org> References: <20201224123119.26504-1-Nick.Fan@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20201224123119.26504-1-Nick.Fan@mediatek.com> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Thu, Dec 24, 2020 at 08:31:18PM +0800, Nick Fan wrote: > Convert the Arm Valhall GPU binding to DT schema format. Convert? There's no existing binding. > > Define a compatible string for the Mali Valhall GPU > for Mediatek's SoC platform. > > Signed-off-by: Nick Fan > --- > .../bindings/gpu/arm,mali-valhall.yaml | 252 ++++++++++++++++++ > 1 file changed, 252 insertions(+) > create mode 100644 Documentation/devicetree/bindings/gpu/arm,mali-valhall.yaml > > diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-valhall.yaml b/Documentation/devicetree/bindings/gpu/arm,mali-valhall.yaml > new file mode 100644 > index 000000000000..3dba202bec95 > --- /dev/null > +++ b/Documentation/devicetree/bindings/gpu/arm,mali-valhall.yaml > @@ -0,0 +1,252 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +# Copyright (c) 2020 MediaTek Inc. > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/gpu/arm,mali-vallhall.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: ARM Mali Valhall GPU > + > +maintainers: > + - Rob Herring > + > +properties: > + $nodename: > + pattern: '^gpu@[a-f0-9]+$' > + > + compatible: > + items: > + - enum: > + - mediatek,mt8192-mali > + - const: arm,mali-valhall # Mali Valhall GPU model/revision is fully discoverable > + > + reg: > + maxItems: 1 > + > + interrupts: > + items: > + - description: GPU interrupt > + - description: MMU interrupt > + - description: Job interrupt > + > + interrupt-names: > + items: > + - const: gpu > + - const: mmu > + - const: job > + > + clocks: > + minItems: 1 > + > + power-domains: > + minItems: 1 > + maxItems: 5 > + > + mali-supply: true > + sram-supply: true > + > + operating-points-v2: true > + > + "#cooling-cells": > + const: 2 > + > +required: > + - compatible > + - reg > + - interrupts > + - interrupt-names > + - clocks > + > +additionalProperties: false > + > +allOf: > + - if: > + properties: > + compatible: > + contains: > + const: mediatek,mt8192-mali > + then: > + properties: > + sram-supply: true No need for this line. > + power-domains: > + description: > + List of phandle and PM domain specifier as documented in > + Documentation/devicetree/bindings/power/power_domain.txt No need re-describe a common property. > + minItems: 5 > + maxItems: 5 blank line between DT properties. > + power-domain-names: > + items: > + - const: core0 > + - const: core1 > + - const: core2 > + - const: core3 > + - const: core4 > + > + required: > + - sram-supply > + - power-domains > + > +examples: > + - | > + #include > + #include > + > + gpu@13000000 { > + compatible = "mediatek,mt8192-mali", "arm,mali-valhall"; > + reg = <0x13000000 0x4000>; > + interrupts = > + , > + , > + ; > + interrupt-names = > + "gpu", > + "mmu", > + "job"; > + > + clocks = <&mfgcfg 0>; > + > + power-domains = > + <&scpsys 4>, > + <&scpsys 5>, > + <&scpsys 6>, > + <&scpsys 7>, > + <&scpsys 8>; > + > + operating-points-v2 = <&gpu_opp_table>; > + mali-supply = <&mt6315_7_vbuck1>; > + sram-supply = <&mt6359_vsram_others_ldo_reg>; > + }; > + > + gpu_opp_table: opp_table0 { Make this a child of the gpu node. Node name should be just 'opp-table'. > + compatible = "operating-points-v2"; > + opp-shared; > + > + opp-358000000 { > + opp-hz = /bits/ 64 <358000000>; > + opp-hz-real = /bits/ 64 <358000000>, I don't recall this being an OPP property. > + /bits/ 64 <358000000>; > + opp-microvolt = <606250>, > + <750000>; > + }; > + > + opp-399000000 { > + opp-hz = /bits/ 64 <399000000>; > + opp-hz-real = /bits/ 64 <399000000>, > + /bits/ 64 <399000000>; > + opp-microvolt = <618750>, > + <750000>; > + }; > + > + opp-440000000 { > + opp-hz = /bits/ 64 <440000000>; > + opp-hz-real = /bits/ 64 <440000000>, > + /bits/ 64 <440000000>; > + opp-microvolt = <631250>, > + <750000>; > + }; > + > + opp-482000000 { > + opp-hz = /bits/ 64 <482000000>; > + opp-hz-real = /bits/ 64 <482000000>, > + /bits/ 64 <482000000>; > + opp-microvolt = <643750>, > + <750000>; > + }; > + > + opp-523000000 { > + opp-hz = /bits/ 64 <523000000>; > + opp-hz-real = /bits/ 64 <523000000>, > + /bits/ 64 <523000000>; > + opp-microvolt = <656250>, > + <750000>; > + }; > + > + opp-564000000 { > + opp-hz = /bits/ 64 <564000000>; > + opp-hz-real = /bits/ 64 <564000000>, > + /bits/ 64 <564000000>; > + opp-microvolt = <668750>, > + <750000>; > + }; > + > + opp-605000000 { > + opp-hz = /bits/ 64 <605000000>; > + opp-hz-real = /bits/ 64 <605000000>, > + /bits/ 64 <605000000>; > + opp-microvolt = <681250>, > + <750000>; > + }; > + > + opp-647000000 { > + opp-hz = /bits/ 64 <647000000>; > + opp-hz-real = /bits/ 64 <647000000>, > + /bits/ 64 <647000000>; > + opp-microvolt = <693750>, > + <750000>; > + }; > + > + opp-688000000 { > + opp-hz = /bits/ 64 <688000000>; > + opp-hz-real = /bits/ 64 <688000000>, > + /bits/ 64 <688000000>; > + opp-microvolt = <706250>, > + <750000>; > + }; > + > + opp-724000000 { > + opp-hz = /bits/ 64 <724000000>; > + opp-hz-real = /bits/ 64 <724000000>, > + /bits/ 64 <724000000>; > + opp-microvolt = <725000>, > + <750000>; > + }; > + > + opp-760000000 { > + opp-hz = /bits/ 64 <760000000>; > + opp-hz-real = /bits/ 64 <760000000>, > + /bits/ 64 <760000000>; > + opp-microvolt = <743750>, > + <750000>; > + }; > + > + opp-795000000 { > + opp-hz = /bits/ 64 <795000000>; > + opp-hz-real = /bits/ 64 <795000000>, > + /bits/ 64 <795000000>; > + opp-microvolt = <762500>, > + <762500>; > + }; > + > + opp-831000000 { > + opp-hz = /bits/ 64 <831000000>; > + opp-hz-real = /bits/ 64 <831000000>, > + /bits/ 64 <831000000>; > + opp-microvolt = <781250>, > + <781250>; > + }; > + > + opp-855000000 { > + opp-hz = /bits/ 64 <855000000>; > + opp-hz-real = /bits/ 64 <855000000>, > + /bits/ 64 <855000000>; > + opp-microvolt = <793750>, > + <793750>; > + }; > + > + opp-902000000 { > + opp-hz = /bits/ 64 <902000000>; > + opp-hz-real = /bits/ 64 <902000000>, > + /bits/ 64 <902000000>; > + opp-microvolt = <818750>, > + <818750>; > + }; > + > + opp-950000000 { > + opp-hz = /bits/ 64 <950000000>; > + opp-hz-real = /bits/ 64 <950000000>, > + /bits/ 64 <950000000>; > + opp-microvolt = <843750>, > + <843750>; > + }; > + }; > +... > -- > 2.18.0 > From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.0 required=3.0 tests=BAYES_00,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 449FDC433E0 for ; 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Thu, 31 Dec 2020 07:57:17 -0800 (PST) Received: (nullmailer pid 1863518 invoked by uid 1000); Thu, 31 Dec 2020 15:57:15 -0000 Date: Thu, 31 Dec 2020 08:57:15 -0700 From: Rob Herring To: Nick Fan Subject: Re: [PATCH 1/2] dt-bindings: Convert Arm Mali Valhall GPU to DT schema Message-ID: <20201231155715.GA1852831@robh.at.kernel.org> References: <20201224123119.26504-1-Nick.Fan@mediatek.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20201224123119.26504-1-Nick.Fan@mediatek.com> X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, srv_heupstream@mediatek.com, David Airlie , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Project_Global_Chrome_Upstream_Group@mediatek.com, linux-mediatek@lists.infradead.org, Matthias Brugger , linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" On Thu, Dec 24, 2020 at 08:31:18PM +0800, Nick Fan wrote: > Convert the Arm Valhall GPU binding to DT schema format. Convert? There's no existing binding. > > Define a compatible string for the Mali Valhall GPU > for Mediatek's SoC platform. > > Signed-off-by: Nick Fan > --- > .../bindings/gpu/arm,mali-valhall.yaml | 252 ++++++++++++++++++ > 1 file changed, 252 insertions(+) > create mode 100644 Documentation/devicetree/bindings/gpu/arm,mali-valhall.yaml > > diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-valhall.yaml b/Documentation/devicetree/bindings/gpu/arm,mali-valhall.yaml > new file mode 100644 > index 000000000000..3dba202bec95 > --- /dev/null > +++ b/Documentation/devicetree/bindings/gpu/arm,mali-valhall.yaml > @@ -0,0 +1,252 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +# Copyright (c) 2020 MediaTek Inc. > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/gpu/arm,mali-vallhall.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: ARM Mali Valhall GPU > + > +maintainers: > + - Rob Herring > + > +properties: > + $nodename: > + pattern: '^gpu@[a-f0-9]+$' > + > + compatible: > + items: > + - enum: > + - mediatek,mt8192-mali > + - const: arm,mali-valhall # Mali Valhall GPU model/revision is fully discoverable > + > + reg: > + maxItems: 1 > + > + interrupts: > + items: > + - description: GPU interrupt > + - description: MMU interrupt > + - description: Job interrupt > + > + interrupt-names: > + items: > + - const: gpu > + - const: mmu > + - const: job > + > + clocks: > + minItems: 1 > + > + power-domains: > + minItems: 1 > + maxItems: 5 > + > + mali-supply: true > + sram-supply: true > + > + operating-points-v2: true > + > + "#cooling-cells": > + const: 2 > + > +required: > + - compatible > + - reg > + - interrupts > + - interrupt-names > + - clocks > + > +additionalProperties: false > + > +allOf: > + - if: > + properties: > + compatible: > + contains: > + const: mediatek,mt8192-mali > + then: > + properties: > + sram-supply: true No need for this line. > + power-domains: > + description: > + List of phandle and PM domain specifier as documented in > + Documentation/devicetree/bindings/power/power_domain.txt No need re-describe a common property. > + minItems: 5 > + maxItems: 5 blank line between DT properties. > + power-domain-names: > + items: > + - const: core0 > + - const: core1 > + - const: core2 > + - const: core3 > + - const: core4 > + > + required: > + - sram-supply > + - power-domains > + > +examples: > + - | > + #include > + #include > + > + gpu@13000000 { > + compatible = "mediatek,mt8192-mali", "arm,mali-valhall"; > + reg = <0x13000000 0x4000>; > + interrupts = > + , > + , > + ; > + interrupt-names = > + "gpu", > + "mmu", > + "job"; > + > + clocks = <&mfgcfg 0>; > + > + power-domains = > + <&scpsys 4>, > + <&scpsys 5>, > + <&scpsys 6>, > + <&scpsys 7>, > + <&scpsys 8>; > + > + operating-points-v2 = <&gpu_opp_table>; > + mali-supply = <&mt6315_7_vbuck1>; > + sram-supply = <&mt6359_vsram_others_ldo_reg>; > + }; > + > + gpu_opp_table: opp_table0 { Make this a child of the gpu node. Node name should be just 'opp-table'. > + compatible = "operating-points-v2"; > + opp-shared; > + > + opp-358000000 { > + opp-hz = /bits/ 64 <358000000>; > + opp-hz-real = /bits/ 64 <358000000>, I don't recall this being an OPP property. > + /bits/ 64 <358000000>; > + opp-microvolt = <606250>, > + <750000>; > + }; > + > + opp-399000000 { > + opp-hz = /bits/ 64 <399000000>; > + opp-hz-real = /bits/ 64 <399000000>, > + /bits/ 64 <399000000>; > + opp-microvolt = <618750>, > + <750000>; > + }; > + > + opp-440000000 { > + opp-hz = /bits/ 64 <440000000>; > + opp-hz-real = /bits/ 64 <440000000>, > + /bits/ 64 <440000000>; > + opp-microvolt = <631250>, > + <750000>; > + }; > + > + opp-482000000 { > + opp-hz = /bits/ 64 <482000000>; > + opp-hz-real = /bits/ 64 <482000000>, > + /bits/ 64 <482000000>; > + opp-microvolt = <643750>, > + <750000>; > + }; > + > + opp-523000000 { > + opp-hz = /bits/ 64 <523000000>; > + opp-hz-real = /bits/ 64 <523000000>, > + /bits/ 64 <523000000>; > + opp-microvolt = <656250>, > + <750000>; > + }; > + > + opp-564000000 { > + opp-hz = /bits/ 64 <564000000>; > + opp-hz-real = /bits/ 64 <564000000>, > + /bits/ 64 <564000000>; > + opp-microvolt = <668750>, > + <750000>; > + }; > + > + opp-605000000 { > + opp-hz = /bits/ 64 <605000000>; > + opp-hz-real = /bits/ 64 <605000000>, > + /bits/ 64 <605000000>; > + opp-microvolt = <681250>, > + <750000>; > + }; > + > + opp-647000000 { > + opp-hz = /bits/ 64 <647000000>; > + opp-hz-real = /bits/ 64 <647000000>, > + /bits/ 64 <647000000>; > + opp-microvolt = <693750>, > + <750000>; > + }; > + > + opp-688000000 { > + opp-hz = /bits/ 64 <688000000>; > + opp-hz-real = /bits/ 64 <688000000>, > + /bits/ 64 <688000000>; > + opp-microvolt = <706250>, > + <750000>; > + }; > + > + opp-724000000 { > + opp-hz = /bits/ 64 <724000000>; > + opp-hz-real = /bits/ 64 <724000000>, > + /bits/ 64 <724000000>; > + opp-microvolt = <725000>, > + <750000>; > + }; > + > + opp-760000000 { > + opp-hz = /bits/ 64 <760000000>; > + opp-hz-real = /bits/ 64 <760000000>, > + /bits/ 64 <760000000>; > + opp-microvolt = <743750>, > + <750000>; > + }; > + > + opp-795000000 { > + opp-hz = /bits/ 64 <795000000>; > + opp-hz-real = /bits/ 64 <795000000>, > + /bits/ 64 <795000000>; > + opp-microvolt = <762500>, > + <762500>; > + }; > + > + opp-831000000 { > + opp-hz = /bits/ 64 <831000000>; > + opp-hz-real = /bits/ 64 <831000000>, > + /bits/ 64 <831000000>; > + opp-microvolt = <781250>, > + <781250>; > + }; > + > + opp-855000000 { > + opp-hz = /bits/ 64 <855000000>; > + opp-hz-real = /bits/ 64 <855000000>, > + /bits/ 64 <855000000>; > + opp-microvolt = <793750>, > + <793750>; > + }; > + > + opp-902000000 { > + opp-hz = /bits/ 64 <902000000>; > + opp-hz-real = /bits/ 64 <902000000>, > + /bits/ 64 <902000000>; > + opp-microvolt = <818750>, > + <818750>; > + }; > + > + opp-950000000 { > + opp-hz = /bits/ 64 <950000000>; > + opp-hz-real = /bits/ 64 <950000000>, > + /bits/ 64 <950000000>; > + opp-microvolt = <843750>, > + <843750>; > + }; > + }; > +... > -- > 2.18.0 > _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel