Re: [PATCH v2 2/2] clk: mvebu: use firmware SiP service for accessing dfx register set

[kernel test robot <lkp@intel.com>]

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Hi,

Thank you for the patch! Yet something to improve:

[auto build test ERROR on clk/clk-next]
[also build test ERROR on linus/master v5.11-rc3 next-20210114]
[cannot apply to thermal/next soc-thermal/next]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]

url:    https://github.com/0day-ci/linux/commits/kostap-marvell-com/Enable-usage-of-Marvell-FW-SIP-services/20210114-183207
base:   https://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git clk-next
config: arm64-allyesconfig (attached as .config)
compiler: aarch64-linux-gcc (GCC) 9.3.0
reproduce (this is a W=1 build):
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # https://github.com/0day-ci/linux/commit/8dc917b26b54d723831b58c1f166a15a1b7d28e2
        git remote add linux-review https://github.com/0day-ci/linux
        git fetch --no-tags linux-review kostap-marvell-com/Enable-usage-of-Marvell-FW-SIP-services/20210114-183207
        git checkout 8dc917b26b54d723831b58c1f166a15a1b7d28e2
        # save the attached .config to linux build tree
        COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross ARCH=arm64 

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>

All errors (new ones prefixed by >>):

   In file included from include/linux/regmap.h:20,
                    from drivers/clk/mvebu/ap-cpu-clk.c:21:
   drivers/clk/mvebu/ap-cpu-clk.c: In function 'legacy_regmap_read_poll_timeout':
>> drivers/clk/mvebu/ap-cpu-clk.c:252:11: error: 'val' undeclared (first use in this function)
     252 |      reg, val,
         |           ^~~
   include/linux/iopoll.h:46:14: note: in definition of macro 'read_poll_timeout'
      46 |   (val) = op(args); \
         |              ^~~~
   drivers/clk/mvebu/ap-cpu-clk.c:251:9: note: in expansion of macro 'regmap_read_poll_timeout'
     251 |  return regmap_read_poll_timeout(clk->pll_cr_base,
         |         ^~~~~~~~~~~~~~~~~~~~~~~~
   drivers/clk/mvebu/ap-cpu-clk.c:252:11: note: each undeclared identifier is reported only once for each function it appears in
     252 |      reg, val,
         |           ^~~
   include/linux/iopoll.h:46:14: note: in definition of macro 'read_poll_timeout'
      46 |   (val) = op(args); \
         |              ^~~~
   drivers/clk/mvebu/ap-cpu-clk.c:251:9: note: in expansion of macro 'regmap_read_poll_timeout'
     251 |  return regmap_read_poll_timeout(clk->pll_cr_base,
         |         ^~~~~~~~~~~~~~~~~~~~~~~~
   drivers/clk/mvebu/ap-cpu-clk.c: In function 'ap_cpu_clk_set_rate':
>> drivers/clk/mvebu/ap-cpu-clk.c:313:20: error: macro "regmap_read_poll_timeout" requires 6 arguments, but only 3 given
     313 |          stable_bit);
         |                    ^
   In file included from drivers/clk/mvebu/ap-cpu-clk.c:21:
   include/linux/regmap.h:103: note: macro "regmap_read_poll_timeout" defined here
     103 | #define regmap_read_poll_timeout(map, addr, val, cond, sleep_us, timeout_us) \
         | 
   drivers/clk/mvebu/ap-cpu-clk.c:311:6: warning: assignment to 'int' from 'int (*)(struct ap_cpu_clk *, unsigned int,  unsigned int)' makes integer from pointer without a cast [-Wint-conversion]
     311 |  ret = clk->regmap_read_poll_timeout(clk,
         |      ^
   drivers/clk/mvebu/ap-cpu-clk.c:277:61: warning: variable 'stable_bit' set but not used [-Wunused-but-set-variable]
     277 |  unsigned int cpu_clkdiv_reg, cpu_force_reg, cpu_ratio_reg, stable_bit;
         |                                                             ^~~~~~~~~~
   drivers/clk/mvebu/ap-cpu-clk.c: In function 'ap_cpu_clock_probe':
>> drivers/clk/mvebu/ap-cpu-clk.c:440:30: error: 'struct ap_cpu_clk' has no member named 'regmap_wriite'; did you mean 'regmap_write'?
     440 |    ap_cpu_clk[cluster_index].regmap_wriite = smc_regmap_write;
         |                              ^~~~~~~~~~~~~
         |                              regmap_write
   drivers/clk/mvebu/ap-cpu-clk.c:446:30: error: 'struct ap_cpu_clk' has no member named 'regmap_wriite'; did you mean 'regmap_write'?
     446 |    ap_cpu_clk[cluster_index].regmap_wriite = legacy_regmap_write;
         |                              ^~~~~~~~~~~~~
         |                              regmap_write
   drivers/clk/mvebu/ap-cpu-clk.c: In function 'smc_regmap_read_poll_timeout':
   drivers/clk/mvebu/ap-cpu-clk.c:245:1: error: control reaches end of non-void function [-Werror=return-type]
     245 | }
         | ^
   cc1: some warnings being treated as errors


vim +/val +252 drivers/clk/mvebu/ap-cpu-clk.c

   246	
   247	static int legacy_regmap_read_poll_timeout(struct ap_cpu_clk *clk,
   248						   unsigned int reg,
   249						   unsigned int stable_bit)
   250	{
 > 251		return regmap_read_poll_timeout(clk->pll_cr_base,
 > 252						reg, val,
   253						val & stable_bit, STATUS_POLL_PERIOD_US,
   254						STATUS_POLL_TIMEOUT_US);
   255	}
   256	static unsigned long ap_cpu_clk_recalc_rate(struct clk_hw *hw,
   257						    unsigned long parent_rate)
   258	{
   259		struct ap_cpu_clk *clk = to_ap_cpu_clk(hw);
   260		unsigned int cpu_clkdiv_reg;
   261		int cpu_clkdiv_ratio;
   262	
   263		cpu_clkdiv_reg = clk->pll_regs->divider_reg +
   264			(clk->cluster * clk->pll_regs->cluster_offset);
   265		clk->regmap_read(clk, cpu_clkdiv_reg, &cpu_clkdiv_ratio);
   266		cpu_clkdiv_ratio &= clk->pll_regs->divider_mask;
   267		cpu_clkdiv_ratio >>= clk->pll_regs->divider_offset;
   268	
   269		return parent_rate / cpu_clkdiv_ratio;
   270	}
   271	
   272	static int ap_cpu_clk_set_rate(struct clk_hw *hw, unsigned long rate,
   273				       unsigned long parent_rate)
   274	{
   275		struct ap_cpu_clk *clk = to_ap_cpu_clk(hw);
   276		int ret, reg, divider = parent_rate / rate;
   277		unsigned int cpu_clkdiv_reg, cpu_force_reg, cpu_ratio_reg, stable_bit;
   278	
   279		cpu_clkdiv_reg = clk->pll_regs->divider_reg +
   280			(clk->cluster * clk->pll_regs->cluster_offset);
   281		cpu_force_reg = clk->pll_regs->force_reg +
   282			(clk->cluster * clk->pll_regs->cluster_offset);
   283		cpu_ratio_reg = clk->pll_regs->ratio_reg +
   284			(clk->cluster * clk->pll_regs->cluster_offset);
   285	
   286		clk->regmap_read(clk, cpu_clkdiv_reg, &reg);
   287		reg &= ~(clk->pll_regs->divider_mask);
   288		reg |= (divider << clk->pll_regs->divider_offset);
   289	
   290		/*
   291		 * AP807 CPU divider has two channels with ratio 1:3 and divider_ratio
   292		 * is 1. Otherwise, in the case of the AP806, divider_ratio is 0.
   293		 */
   294		if (clk->pll_regs->divider_ratio) {
   295			reg &= ~(AP807_PLL_CR_1_CPU_CLK_DIV_RATIO_MASK);
   296			reg |= ((divider * clk->pll_regs->divider_ratio) <<
   297					AP807_PLL_CR_1_CPU_CLK_DIV_RATIO_OFFSET);
   298		}
   299		clk->regmap_write(clk, cpu_clkdiv_reg, reg);
   300	
   301		clk->regmap_update_bits(clk, cpu_force_reg, clk->pll_regs->force_mask,
   302					clk->pll_regs->force_mask);
   303	
   304		clk->regmap_update_bits(clk, cpu_ratio_reg,
   305					BIT(clk->pll_regs->ratio_offset),
   306					BIT(clk->pll_regs->ratio_offset));
   307	
   308		stable_bit = BIT(clk->pll_regs->ratio_state_offset +
   309				 clk->cluster *
   310				 clk->pll_regs->ratio_state_cluster_offset);
 > 311		ret = clk->regmap_read_poll_timeout(clk,
   312						    clk->pll_regs->ratio_state_reg,
 > 313						    stable_bit);
   314		if (ret)
   315			return ret;
   316	
   317		clk->regmap_update_bits(clk, cpu_ratio_reg,
   318					BIT(clk->pll_regs->ratio_offset), 0);
   319	
   320		return 0;
   321	}
   322	
   323	static long ap_cpu_clk_round_rate(struct clk_hw *hw, unsigned long rate,
   324					  unsigned long *parent_rate)
   325	{
   326		int divider = *parent_rate / rate;
   327	
   328		divider = min(divider, APN806_MAX_DIVIDER);
   329	
   330		return *parent_rate / divider;
   331	}
   332	
   333	static const struct clk_ops ap_cpu_clk_ops = {
   334		.recalc_rate	= ap_cpu_clk_recalc_rate,
   335		.round_rate	= ap_cpu_clk_round_rate,
   336		.set_rate	= ap_cpu_clk_set_rate,
   337	};
   338	
   339	static int ap_cpu_clock_probe(struct platform_device *pdev)
   340	{
   341		int ret, nclusters = 0, cluster_index = 0;
   342		struct device *dev = &pdev->dev;
   343		struct device_node *dn, *np = dev->of_node;
   344		struct clk_hw_onecell_data *ap_cpu_data;
   345		struct ap_cpu_clk *ap_cpu_clk;
   346		struct regmap *regmap;
   347		struct resource res;
   348	
   349		ret = of_address_to_resource(np->parent, 0, &res);
   350		if (ret)
   351			return ret;
   352	
   353		regmap = syscon_node_to_regmap(np->parent);
   354		if (IS_ERR(regmap)) {
   355			pr_err("cannot get pll_cr_base regmap\n");
   356			return PTR_ERR(regmap);
   357		}
   358	
   359		/*
   360		 * AP806 has 4 cpus and DFS for AP806 is controlled per
   361		 * cluster (2 CPUs per cluster), cpu0 and cpu1 are fixed to
   362		 * cluster0 while cpu2 and cpu3 are fixed to cluster1 whether
   363		 * they are enabled or not.  Since cpu0 is the boot cpu, then
   364		 * cluster0 must exist.  If cpu2 or cpu3 is enabled, cluster1
   365		 * will exist and the cluster number is 2; otherwise the
   366		 * cluster number is 1.
   367		 */
   368		nclusters = 1;
   369		for_each_of_cpu_node(dn) {
   370			int cpu, err;
   371	
   372			err = of_property_read_u32(dn, "reg", &cpu);
   373			if (WARN_ON(err))
   374				return err;
   375	
   376			/* If cpu2 or cpu3 is enabled */
   377			if (cpu & APN806_CLUSTER_NUM_MASK) {
   378				nclusters = 2;
   379				break;
   380			}
   381		}
   382		/*
   383		 * DFS for AP806 is controlled per cluster (2 CPUs per cluster),
   384		 * so allocate structs per cluster
   385		 */
   386		ap_cpu_clk = devm_kcalloc(dev, nclusters, sizeof(*ap_cpu_clk),
   387					  GFP_KERNEL);
   388		if (!ap_cpu_clk)
   389			return -ENOMEM;
   390	
   391		ap_cpu_data = devm_kzalloc(dev, struct_size(ap_cpu_data, hws,
   392							    nclusters),
   393					GFP_KERNEL);
   394		if (!ap_cpu_data)
   395			return -ENOMEM;
   396	
   397		for_each_of_cpu_node(dn) {
   398			char *clk_name = "cpu-cluster-0";
   399			struct clk_init_data init;
   400			const char *parent_name;
   401			struct clk *parent;
   402			int cpu, err;
   403			unsigned int tmp;
   404	
   405			err = of_property_read_u32(dn, "reg", &cpu);
   406			if (WARN_ON(err))
   407				return err;
   408	
   409			cluster_index = cpu & APN806_CLUSTER_NUM_MASK;
   410			cluster_index >>= APN806_CLUSTER_NUM_OFFSET;
   411	
   412			/* Initialize once for one cluster */
   413			if (ap_cpu_data->hws[cluster_index])
   414				continue;
   415	
   416			parent = of_clk_get(np, cluster_index);
   417			if (IS_ERR(parent)) {
   418				dev_err(dev, "Could not get the clock parent\n");
   419				return -EINVAL;
   420			}
   421			parent_name =  __clk_get_name(parent);
   422			clk_name[12] += cluster_index;
   423			ap_cpu_clk[cluster_index].clk_name =
   424				ap_cp_unique_name(dev, np->parent, clk_name);
   425			ap_cpu_clk[cluster_index].cluster = cluster_index;
   426			ap_cpu_clk[cluster_index].pll_cr_base = regmap;
   427			ap_cpu_clk[cluster_index].hw.init = &init;
   428			ap_cpu_clk[cluster_index].dev = dev;
   429			ap_cpu_clk[cluster_index].pll_regs = of_device_get_match_data(&pdev->dev);
   430	
   431			/* Get the physical address to hand to the firmware. */
   432			ap_cpu_clk[cluster_index].phys = res.start;
   433	
   434			/* Try to read a register using SMC and setup DFX access APIs accordingly */
   435			ret = smc_regmap_read(&ap_cpu_clk[cluster_index],
   436					      ap_cpu_clk[cluster_index].pll_regs->divider_reg,
   437					      &tmp);
   438			if (ret == SMCCC_RET_SUCCESS) {
   439				ap_cpu_clk[cluster_index].regmap_read = smc_regmap_read;
 > 440				ap_cpu_clk[cluster_index].regmap_wriite = smc_regmap_write;
   441				ap_cpu_clk[cluster_index].regmap_update_bits = smc_regmap_update_bits;
   442				ap_cpu_clk[cluster_index].regmap_read_poll_timeout =
   443									smc_regmap_read_poll_timeout;
   444			} else {
   445				ap_cpu_clk[cluster_index].regmap_read = legacy_regmap_read;
   446				ap_cpu_clk[cluster_index].regmap_wriite = legacy_regmap_write;
   447				ap_cpu_clk[cluster_index].regmap_update_bits = legacy_regmap_update_bits;
   448				ap_cpu_clk[cluster_index].regmap_read_poll_timeout =
   449									legacy_regmap_read_poll_timeout;
   450			}
   451	
   452			init.name = ap_cpu_clk[cluster_index].clk_name;
   453			init.ops = &ap_cpu_clk_ops;
   454			init.num_parents = 1;
   455			init.parent_names = &parent_name;
   456	
   457			ret = devm_clk_hw_register(dev, &ap_cpu_clk[cluster_index].hw);
   458			if (ret)
   459				return ret;
   460			ap_cpu_data->hws[cluster_index] = &ap_cpu_clk[cluster_index].hw;
   461		}
   462	
   463		ap_cpu_data->num = cluster_index + 1;
   464	
   465		ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, ap_cpu_data);
   466		if (ret)
   467			dev_err(dev, "failed to register OF clock provider\n");
   468	
   469		return ret;
   470	}
   471	

---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org

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