From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.3 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id ABD58C433DB for ; Mon, 25 Jan 2021 18:46:55 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 632F0207B3 for ; Mon, 25 Jan 2021 18:46:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730443AbhAYSqq (ORCPT ); Mon, 25 Jan 2021 13:46:46 -0500 Received: from mail.kernel.org ([198.145.29.99]:33350 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730064AbhAYSqS (ORCPT ); Mon, 25 Jan 2021 13:46:18 -0500 Received: by mail.kernel.org (Postfix) with ESMTPSA id 2320522DFB; Mon, 25 Jan 2021 18:45:43 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1611600344; bh=Z0PYkD5c8k6V+L+B6WcLlwfL+2n9gR6KhmRw0jJXIlE=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=iAjAaIRatmibVWZrqxhrA/wafXH0y9jZSaTxrxsPjuYzcBqELg5GSXY/hHJIfeT0n Ow0qoLYVHRIBadT7JqOv3CmqlQLEBWbX00eZ1wf97Fk03eH2PQA0mmtWpWDXnRZZGM nKYAjbF7HG07gMlCOTP5ErrdEfu6+ot8H4ENWqpnN3F95f2W0vpGREmkcRZ8PnXH5E mVNlXIQ2a9FOCq+2Hp4DvsfJLiRfya8VaUwmOgb7ZE0XG/EkqgEG9u8Ll/8KJtwTyA uSXarDER2z+3KIBFVz97OL9klmlWeb83MNwemtU3yDkOvTZrxKLgcCwpafRE7Imn9c vjk9snNlD9cqw== Date: Mon, 25 Jan 2021 20:45:41 +0200 From: Leon Romanovsky To: Robin Murphy Cc: xxm , devicetree@vger.kernel.org, Lorenzo Pieralisi , Heiko Stuebner , linux-pci@vger.kernel.org, Shawn Lin , linux-rockchip@lists.infradead.org, robh+dt@kernel.org, Bjorn Helgaas , Johan Jonker Subject: Re: [PATCH v3 2/2] PCI: rockchip: add DesignWare based PCIe controller Message-ID: <20210125184541.GJ579511@unreal> References: <20210125024824.634583-1-xxm@rock-chips.com> <20210125024927.634634-1-xxm@rock-chips.com> <20210125054836.GB579511@unreal> <0b65ca38-ff7a-f9cd-5406-1f275fbbecd1@rock-chips.com> <20210125090129.GF579511@unreal> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org On Mon, Jan 25, 2021 at 03:53:38PM +0000, Robin Murphy wrote: > On 2021-01-25 09:01, Leon Romanovsky wrote: > > On Mon, Jan 25, 2021 at 02:40:10PM +0800, xxm wrote: > > > Hi Leon, > > > > > > Thanks for your reply. > > > > > > 在 2021/1/25 13:48, Leon Romanovsky 写道: > > > > On Mon, Jan 25, 2021 at 10:49:27AM +0800, Simon Xue wrote: > > > > > pcie-dw-rockchip is based on DWC IP. But pcie-rockchip-host > > > > > is Rockchip designed IP which is only used for RK3399. So all the following > > > > > non-RK3399 SoCs should use this driver. > > > > > > > > > > Signed-off-by: Simon Xue > > > > > Signed-off-by: Shawn Lin > > > > > --- > > > > > drivers/pci/controller/dwc/Kconfig | 9 + > > > > > drivers/pci/controller/dwc/Makefile | 1 + > > > > > drivers/pci/controller/dwc/pcie-dw-rockchip.c | 286 ++++++++++++++++++ > > > > > 3 files changed, 296 insertions(+) > > > > > create mode 100644 drivers/pci/controller/dwc/pcie-dw-rockchip.c > > > > > > > > > > diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dwc/Kconfig > > > > > index 22c5529e9a65..aee408fe9283 100644 > > > > > --- a/drivers/pci/controller/dwc/Kconfig > > > > > +++ b/drivers/pci/controller/dwc/Kconfig > > > > > @@ -214,6 +214,15 @@ config PCIE_ARTPEC6_EP > > > > > Enables support for the PCIe controller in the ARTPEC-6 SoC to work in > > > > > endpoint mode. This uses the DesignWare core. > > > > > > > > > > +config PCIE_ROCKCHIP_DW_HOST > > > > > + bool "Rockchip DesignWare PCIe controller" > > > > > + select PCIE_DW > > > > > + select PCIE_DW_HOST > > > > > + depends on ARCH_ROCKCHIP || COMPILE_TEST > > > > > + depends on OF > > > > > + help > > > > > + Enables support for the DW PCIe controller in the Rockchip SoC. > > > > > + > > > > > config PCIE_INTEL_GW > > > > > bool "Intel Gateway PCIe host controller support" > > > > > depends on OF && (X86 || COMPILE_TEST) > > > > > diff --git a/drivers/pci/controller/dwc/Makefile b/drivers/pci/controller/dwc/Makefile > > > > > index a751553fa0db..30eef8e9ee8a 100644 > > > > > --- a/drivers/pci/controller/dwc/Makefile > > > > > +++ b/drivers/pci/controller/dwc/Makefile > > > > > @@ -13,6 +13,7 @@ obj-$(CONFIG_PCI_LAYERSCAPE_EP) += pci-layerscape-ep.o > > > > > obj-$(CONFIG_PCIE_QCOM) += pcie-qcom.o > > > > > obj-$(CONFIG_PCIE_ARMADA_8K) += pcie-armada8k.o > > > > > obj-$(CONFIG_PCIE_ARTPEC6) += pcie-artpec6.o > > > > > +obj-$(CONFIG_PCIE_ROCKCHIP_DW_HOST) += pcie-dw-rockchip.o > > > > > obj-$(CONFIG_PCIE_INTEL_GW) += pcie-intel-gw.o > > > > > obj-$(CONFIG_PCIE_KIRIN) += pcie-kirin.o > > > > > obj-$(CONFIG_PCIE_HISI_STB) += pcie-histb.o > > > > > diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/controller/dwc/pcie-dw-rockchip.c > > > > > new file mode 100644 > > > > > index 000000000000..07f6d1cd5853 > > > > > --- /dev/null > > > > > +++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c > > > > > @@ -0,0 +1,286 @@ > > > > > +// SPDX-License-Identifier: GPL-2.0 > > > > > +/* > > > > > + * PCIe host controller driver for Rockchip SoCs > > > > > + * > > > > > + * Copyright (C) 2021 Rockchip Electronics Co., Ltd. > > > > > + * http://www.rock-chips.com > > > > > + * > > > > > + * Author: Simon Xue > > > > > + */ > > > > > + > > > > > +#include > > > > > +#include > > > > > +#include > > > > > +#include > > > > > +#include > > > > > +#include > > > > > +#include > > > > > +#include > > > > > +#include > > > > > + > > > > > +#include "pcie-designware.h" > > > > > + > > > > > +/* > > > > > + * The upper 16 bits of PCIE_CLIENT_CONFIG are a write > > > > > + * mask for the lower 16 bits. This allows atomic updates > > > > > + * of the register without locking. > > > > > + */ > > > > This is correct only for the variables that naturally aligned, I imagine > > > > that this is the case here and in the Linux, but better do not write comments > > > > in the code that are not accurate. > > > > > > Ok, will remove. > > > I wonder what it would be when outside the Linux? Could you share some information? > > > > The C standard says nothing about atomicity, integer assignment maybe atomic, > > maybe it isn’t. There is no guarantee, plain integer assignment in C is non-atomic > > by definition. > > > > The atomicity of u32 is very dependent on hardware vendor, memory model and compiler, > > for example x86 and ARMs guarantee atomicity for u32. This is why I said that probably > > here (Linux) it is ok and you are not alone in expecting lockless write. > > Huh? What do variables and the abstract machine of the C language > environment have to do with the definition of *hardware MMIO registers*? We > don't write to registers with plain integer assignment of u32, we use > writel() (precisely in order to bypass that abstract C environment). > > I appreciate that the comment is not universally true if taken completely > out of context, but I that's true of pretty much all comments ever. If > someone really were trying to learn basic programming principles from random > comments in Linux drivers, then it's already a bit late for us to try and > save them from themselves. So what? Does it mean that new code should have comments that are not correct? As you can see from this conversation, even the author didn't know what u32 isn’t guaranteed to be atomic, so yes, the comments should be correct. Thanks From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.3 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A0D65C433DB for ; Mon, 25 Jan 2021 18:45:55 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 48F2620758 for ; Mon, 25 Jan 2021 18:45:55 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 48F2620758 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) 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uSXarDER2z+3KIBFVz97OL9klmlWeb83MNwemtU3yDkOvTZrxKLgcCwpafRE7Imn9c vjk9snNlD9cqw== Date: Mon, 25 Jan 2021 20:45:41 +0200 From: Leon Romanovsky To: Robin Murphy Subject: Re: [PATCH v3 2/2] PCI: rockchip: add DesignWare based PCIe controller Message-ID: <20210125184541.GJ579511@unreal> References: <20210125024824.634583-1-xxm@rock-chips.com> <20210125024927.634634-1-xxm@rock-chips.com> <20210125054836.GB579511@unreal> <0b65ca38-ff7a-f9cd-5406-1f275fbbecd1@rock-chips.com> <20210125090129.GF579511@unreal> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210125_134546_169215_A26F05A2 X-CRM114-Status: GOOD ( 34.78 ) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Lorenzo Pieralisi , xxm , linux-pci@vger.kernel.org, Shawn Lin , linux-rockchip@lists.infradead.org, robh+dt@kernel.org, Bjorn Helgaas , Johan Jonker , Heiko Stuebner Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org T24gTW9uLCBKYW4gMjUsIDIwMjEgYXQgMDM6NTM6MzhQTSArMDAwMCwgUm9iaW4gTXVycGh5IHdy b3RlOgo+IE9uIDIwMjEtMDEtMjUgMDk6MDEsIExlb24gUm9tYW5vdnNreSB3cm90ZToKPiA+IE9u IE1vbiwgSmFuIDI1LCAyMDIxIGF0IDAyOjQwOjEwUE0gKzA4MDAsIHh4bSB3cm90ZToKPiA+ID4g SGkgTGVvbiwKPiA+ID4KPiA+ID4gVGhhbmtzIGZvciB5b3VyIHJlcGx5Lgo+ID4gPgo+ID4gPiDl nKggMjAyMS8xLzI1IDEzOjQ4LCBMZW9uIFJvbWFub3Zza3kg5YaZ6YGTOgo+ID4gPiA+IE9uIE1v biwgSmFuIDI1LCAyMDIxIGF0IDEwOjQ5OjI3QU0gKzA4MDAsIFNpbW9uIFh1ZSB3cm90ZToKPiA+ ID4gPiA+IHBjaWUtZHctcm9ja2NoaXAgaXMgYmFzZWQgb24gRFdDIElQLiBCdXQgcGNpZS1yb2Nr Y2hpcC1ob3N0Cj4gPiA+ID4gPiBpcyBSb2NrY2hpcCBkZXNpZ25lZCBJUCB3aGljaCBpcyBvbmx5 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