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Tue, 26 Jan 2021 03:16:10 -0800 Date: Tue, 26 Jan 2021 12:16:16 +0100 From: "Edgar E. Iglesias" To: Joe Komlodi Subject: Re: [PATCH v1 1/3] target/microblaze: Add use-non-secure property Message-ID: <20210126111616.GF10562@toto> References: <1611274735-303873-1-git-send-email-komlodi@xilinx.com> <1611274735-303873-2-git-send-email-komlodi@xilinx.com> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <1611274735-303873-2-git-send-email-komlodi@xilinx.com> User-Agent: Mutt/1.10.1 (2018-07-13) X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 71781de2-1535-4376-7d69-08d8c1ebc9a2 X-MS-TrafficTypeDiagnostic: MWHPR02MB2589: X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Oob-TLC-OOBClassifiers: OLM:9508; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: nQKSUkJ7OevmyCkJa3f2R9eSz2siSwJ3wkH4GqotKhxsb66FFbtt/M3V2FY1ZtS7YsCnIn54VP/TYCc+qWeVrd56VfZgLHbi3amapIPMbEGLIFMofh2bcyMJLtArP2VxQ33qKAix0kvwO7Uw4IOkERIqQq3Qwj2m+UPiWQlvp0q0NT5Xt4utmL7rtcPjD122u5f9uSfzm0QjpAUDitV1P5YTDn5b8ICR6q7n0PMCsd1mxFUDmuWF8FpUfGyQ76G7uT7h6D/342I1njGBfs0lC0M47AomTOseiFfxZdBmc+h0tNCUx6FK5WMeaXf+n5cpdXyZ+kdehAkJnXWDzqDGP6rhjEa95r9l1DAdzR8OVrpkvMF/84zNTYcUfI0OfKxST9fzA1LhVHEe1jwDSq+NYDw/lXXXhLlr8fN/EC+hl2uwBy2+M9wRXSY28A5mYMG5cbiAaJlC/vVzZKbbYwD3j7gdKDozVlzUZD9L3yjwYoL8CA24niRyZ/xJ63WhvK3fFl3N0eoHsS2C2/+e4+JOTf8D6pkrVSrqBqjnK+GzhDg= X-Forefront-Antispam-Report: CIP:149.199.62.198; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:xsj-pvapexch02.xlnx.xilinx.com; PTR:unknown-62-198.xilinx.com; CAT:NONE; SFS:(7916004)(4636009)(396003)(136003)(376002)(346002)(39860400002)(46966006)(82310400003)(9686003)(70586007)(4326008)(356005)(8676002)(5660300002)(70206006)(107886003)(1076003)(54906003)(2906002)(478600001)(47076005)(426003)(83380400001)(33716001)(6862004)(186003)(82740400003)(316002)(966005)(336012)(9786002)(8936002)(6636002)(33656002)(26005)(7636003)(36906005); DIR:OUT; SFP:1101; X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Jan 2021 11:16:11.6470 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 71781de2-1535-4376-7d69-08d8c1ebc9a2 X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c; Ip=[149.199.62.198]; Helo=[xsj-pvapexch02.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-AuthSource: SN1NAM02FT018.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MWHPR02MB2589 Received-SPF: pass client-ip=40.107.237.66; envelope-from=edgar@xilinx.com; helo=NAM12-BN8-obe.outbound.protection.outlook.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgari@xilinx.com, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Thu, Jan 21, 2021 at 04:18:53PM -0800, Joe Komlodi wrote: > This property is used to control the security of the following interfaces > on MicroBlaze: > M_AXI_DP - data interface > M_AXI_IP - instruction interface > M_AXI_DC - dcache interface > M_AXI_IC - icache interface > > It works by enabling or disabling the use of the non_secure[3:0] signals. > > Interfaces and their corresponding values are taken from: > https://www.xilinx.com/support/documentation/sw_manuals/xilinx2020_2/ug984-vivado-microblaze-ref.pdf > page 153. Thanks Joe! Reviewed-by: Edgar E. Iglesias Tested-by: Edgar E. Iglesias > > Signed-off-by: Joe Komlodi > --- > target/microblaze/cpu.c | 46 ++++++++++++++++++++++++++++++++++++++++++++++ > target/microblaze/cpu.h | 11 +++++++++++ > 2 files changed, 57 insertions(+) > > diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c > index c8e754c..accfb23 100644 > --- a/target/microblaze/cpu.c > +++ b/target/microblaze/cpu.c > @@ -98,6 +98,38 @@ static bool mb_cpu_has_work(CPUState *cs) > } > > #ifndef CONFIG_USER_ONLY > +static void mb_cpu_ns_axi_dp(void *opaque, int irq, int level) > +{ > + MicroBlazeCPU *cpu = opaque; > + bool en = cpu->cfg.use_non_secure & USE_NON_SECURE_M_AXI_DP_MASK; > + > + cpu->ns_axi_dp = level & en; > +} > + > +static void mb_cpu_ns_axi_ip(void *opaque, int irq, int level) > +{ > + MicroBlazeCPU *cpu = opaque; > + bool en = cpu->cfg.use_non_secure & USE_NON_SECURE_M_AXI_IP_MASK; > + > + cpu->ns_axi_ip = level & en; > +} > + > +static void mb_cpu_ns_axi_dc(void *opaque, int irq, int level) > +{ > + MicroBlazeCPU *cpu = opaque; > + bool en = cpu->cfg.use_non_secure & USE_NON_SECURE_M_AXI_DC_MASK; > + > + cpu->ns_axi_dc = level & en; > +} > + > +static void mb_cpu_ns_axi_ic(void *opaque, int irq, int level) > +{ > + MicroBlazeCPU *cpu = opaque; > + bool en = cpu->cfg.use_non_secure & USE_NON_SECURE_M_AXI_IC_MASK; > + > + cpu->ns_axi_ic = level & en; > +} > + > static void microblaze_cpu_set_irq(void *opaque, int irq, int level) > { > MicroBlazeCPU *cpu = opaque; > @@ -248,6 +280,10 @@ static void mb_cpu_initfn(Object *obj) > #ifndef CONFIG_USER_ONLY > /* Inbound IRQ and FIR lines */ > qdev_init_gpio_in(DEVICE(cpu), microblaze_cpu_set_irq, 2); > + qdev_init_gpio_in_named(DEVICE(cpu), mb_cpu_ns_axi_dp, "ns_axi_dp", 1); > + qdev_init_gpio_in_named(DEVICE(cpu), mb_cpu_ns_axi_ip, "ns_axi_ip", 1); > + qdev_init_gpio_in_named(DEVICE(cpu), mb_cpu_ns_axi_dc, "ns_axi_dc", 1); > + qdev_init_gpio_in_named(DEVICE(cpu), mb_cpu_ns_axi_ic, "ns_axi_ic", 1); > #endif > } > > @@ -277,6 +313,16 @@ static Property mb_properties[] = { > DEFINE_PROP_BOOL("use-msr-instr", MicroBlazeCPU, cfg.use_msr_instr, true), > DEFINE_PROP_BOOL("use-pcmp-instr", MicroBlazeCPU, cfg.use_pcmp_instr, true), > DEFINE_PROP_BOOL("use-mmu", MicroBlazeCPU, cfg.use_mmu, true), > + /* > + * use-non-secure enables/disables the use of the non_secure[3:0] signals. > + * It is a bitfield where 1 = non-secure for the following bits and their > + * corresponding interfaces: > + * 0x1 - M_AXI_DP > + * 0x2 - M_AXI_IP > + * 0x4 - M_AXI_DC > + * 0x8 - M_AXI_IC > + */ > + DEFINE_PROP_UINT8("use-non-secure", MicroBlazeCPU, cfg.use_non_secure, 0), > DEFINE_PROP_BOOL("dcache-writeback", MicroBlazeCPU, cfg.dcache_writeback, > false), > DEFINE_PROP_BOOL("endianness", MicroBlazeCPU, cfg.endi, false), > diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h > index c1c2641..199cfb0 100644 > --- a/target/microblaze/cpu.h > +++ b/target/microblaze/cpu.h > @@ -233,6 +233,12 @@ typedef struct CPUMBState CPUMBState; > > #define TARGET_INSN_START_EXTRA_WORDS 1 > > +/* use-non-secure property masks */ > +#define USE_NON_SECURE_M_AXI_DP_MASK 0x1 > +#define USE_NON_SECURE_M_AXI_IP_MASK 0x2 > +#define USE_NON_SECURE_M_AXI_DC_MASK 0x4 > +#define USE_NON_SECURE_M_AXI_IC_MASK 0x8 > + > struct CPUMBState { > uint32_t bvalue; /* TCG temporary, only valid during a TB */ > uint32_t btarget; /* Full resolved branch destination */ > @@ -316,6 +322,7 @@ typedef struct { > bool use_msr_instr; > bool use_pcmp_instr; > bool use_mmu; > + uint8_t use_non_secure; > bool dcache_writeback; > bool endi; > bool dopb_bus_exception; > @@ -337,6 +344,10 @@ struct MicroBlazeCPU { > CPUState parent_obj; > > /*< public >*/ > + bool ns_axi_dp; > + bool ns_axi_ip; > + bool ns_axi_dc; > + bool ns_axi_ic; > > CPUNegativeOffsetState neg; > CPUMBState env; > -- > 2.7.4 >