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X-OriginatorOrg: nokia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Jan 2021 20:36:34.6757 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 869a0cb6-4be5-42cd-3a58-08d8c3033cf3 X-MS-Exchange-CrossTenant-Id: 5d471751-9675-428d-917b-70f44f9630b0 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=5d471751-9675-428d-917b-70f44f9630b0;Ip=[131.228.2.8];Helo=[fihe3nok0734.emea.nsn-net.net] X-MS-Exchange-CrossTenant-AuthSource: DB5EUR03FT043.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB7PR07MB3947 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org From: Alexander Sverdlin On Octeon smp_mb() translates to SYNC while wmb+rmb translates to SYNCW only. This brings around 10% performance on tight uncontended spinlock loops. Refer to commit 500c2e1fdbcc ("MIPS: Optimize spinlocks.") and the link below. On 6-core Octeon machine: sysbench --test=mutex --num-threads=64 --memory-scope=local run w/o patch: 1.60s with patch: 1.51s Link: https://lore.kernel.org/lkml/5644D08D.4080206@caviumnetworks.com/ Signed-off-by: Alexander Sverdlin --- arch/mips/include/asm/barrier.h | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/mips/include/asm/barrier.h b/arch/mips/include/asm/barrier.h index 49ff172..24c3f2c 100644 --- a/arch/mips/include/asm/barrier.h +++ b/arch/mips/include/asm/barrier.h @@ -113,6 +113,15 @@ static inline void wmb(void) ".set arch=octeon\n\t" \ "syncw\n\t" \ ".set pop" : : : "memory") + +#define __smp_store_release(p, v) \ +do { \ + compiletime_assert_atomic_type(*p); \ + __smp_wmb(); \ + __smp_rmb(); \ + WRITE_ONCE(*p, v); \ +} while (0) + #else #define smp_mb__before_llsc() smp_llsc_mb() #define __smp_mb__before_llsc() smp_llsc_mb() -- 2.10.2