From: kernel test robot <lkp@intel.com>
To: kbuild@lists.01.org
Subject: [agd5f:drm-next 50/60] drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c:999 amdgpu_info_ioctl() warn: possible memory leak of 'caps'
Date: Fri, 29 Jan 2021 10:52:11 +0800 [thread overview]
Message-ID: <202101291053.Bimdgb2e-lkp@intel.com> (raw)
[-- Attachment #1: Type: text/plain, Size: 54431 bytes --]
CC: kbuild-all(a)lists.01.org
TO: Alex Deucher <alexander.deucher@amd.com>
CC: Leo Liu <leo.liu@amd.com>
tree: https://gitlab.freedesktop.org/agd5f/linux.git drm-next
head: 92d7537f76bdb5485d663b49d79297769a0e0aa9
commit: 555fc7fbb2a2b2a13c8d59946ede06c8fe6b85bd [50/60] drm/amdgpu: add INFO ioctl support for querying video caps
:::::: branch date: 7 hours ago
:::::: commit date: 7 hours ago
config: x86_64-randconfig-m001-20210128 (attached as .config)
compiler: gcc-9 (Debian 9.3.0-15) 9.3.0
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
Reported-by: Dan Carpenter <dan.carpenter@oracle.com>
New smatch warnings:
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c:999 amdgpu_info_ioctl() warn: possible memory leak of 'caps'
Old smatch warnings:
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c:1004 amdgpu_info_ioctl() warn: possible memory leak of 'caps'
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c:1010 amdgpu_info_ioctl() warn: possible memory leak of 'caps'
vim +/caps +999 drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
a245daf3d7a143 Christian König 2018-08-01 477
a245daf3d7a143 Christian König 2018-08-01 478 /*
a245daf3d7a143 Christian König 2018-08-01 479 * Userspace get information ioctl
a245daf3d7a143 Christian König 2018-08-01 480 */
a245daf3d7a143 Christian König 2018-08-01 481 /**
a245daf3d7a143 Christian König 2018-08-01 482 * amdgpu_info_ioctl - answer a device specific request.
a245daf3d7a143 Christian König 2018-08-01 483 *
8970b698b0cee4 Lee Jones 2020-11-12 484 * @dev: drm device pointer
a245daf3d7a143 Christian König 2018-08-01 485 * @data: request object
a245daf3d7a143 Christian König 2018-08-01 486 * @filp: drm filp
a245daf3d7a143 Christian König 2018-08-01 487 *
a245daf3d7a143 Christian König 2018-08-01 488 * This function is used to pass device specific parameters to the userspace
a245daf3d7a143 Christian König 2018-08-01 489 * drivers. Examples include: pci device id, pipeline parms, tiling params,
a245daf3d7a143 Christian König 2018-08-01 490 * etc. (all asics).
a245daf3d7a143 Christian König 2018-08-01 491 * Returns 0 on success, -EINVAL on failure.
a245daf3d7a143 Christian König 2018-08-01 492 */
5088d6572e8ff6 Luben Tuikov 2020-11-04 493 int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
a245daf3d7a143 Christian König 2018-08-01 494 {
1348969ab68cb8 Luben Tuikov 2020-08-24 495 struct amdgpu_device *adev = drm_to_adev(dev);
a245daf3d7a143 Christian König 2018-08-01 496 struct drm_amdgpu_info *info = data;
a245daf3d7a143 Christian König 2018-08-01 497 struct amdgpu_mode_info *minfo = &adev->mode_info;
a245daf3d7a143 Christian König 2018-08-01 498 void __user *out = (void __user *)(uintptr_t)info->return_pointer;
a245daf3d7a143 Christian König 2018-08-01 499 uint32_t size = info->return_size;
a245daf3d7a143 Christian König 2018-08-01 500 struct drm_crtc *crtc;
a245daf3d7a143 Christian König 2018-08-01 501 uint32_t ui32 = 0;
a245daf3d7a143 Christian König 2018-08-01 502 uint64_t ui64 = 0;
a245daf3d7a143 Christian König 2018-08-01 503 int i, found;
a245daf3d7a143 Christian König 2018-08-01 504 int ui32_size = sizeof(ui32);
a245daf3d7a143 Christian König 2018-08-01 505
a245daf3d7a143 Christian König 2018-08-01 506 if (!info->return_size || !info->return_pointer)
a245daf3d7a143 Christian König 2018-08-01 507 return -EINVAL;
a245daf3d7a143 Christian König 2018-08-01 508
a245daf3d7a143 Christian König 2018-08-01 509 switch (info->query) {
a245daf3d7a143 Christian König 2018-08-01 510 case AMDGPU_INFO_ACCEL_WORKING:
a245daf3d7a143 Christian König 2018-08-01 511 ui32 = adev->accel_working;
a245daf3d7a143 Christian König 2018-08-01 512 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
a245daf3d7a143 Christian König 2018-08-01 513 case AMDGPU_INFO_CRTC_FROM_ID:
a245daf3d7a143 Christian König 2018-08-01 514 for (i = 0, found = 0; i < adev->mode_info.num_crtc; i++) {
a245daf3d7a143 Christian König 2018-08-01 515 crtc = (struct drm_crtc *)minfo->crtcs[i];
a245daf3d7a143 Christian König 2018-08-01 516 if (crtc && crtc->base.id == info->mode_crtc.id) {
a245daf3d7a143 Christian König 2018-08-01 517 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
a245daf3d7a143 Christian König 2018-08-01 518 ui32 = amdgpu_crtc->crtc_id;
a245daf3d7a143 Christian König 2018-08-01 519 found = 1;
a245daf3d7a143 Christian König 2018-08-01 520 break;
a245daf3d7a143 Christian König 2018-08-01 521 }
d38ceaf99ed015 Alex Deucher 2015-04-20 522 }
a245daf3d7a143 Christian König 2018-08-01 523 if (!found) {
a245daf3d7a143 Christian König 2018-08-01 524 DRM_DEBUG_KMS("unknown crtc id %d\n", info->mode_crtc.id);
a245daf3d7a143 Christian König 2018-08-01 525 return -EINVAL;
d38ceaf99ed015 Alex Deucher 2015-04-20 526 }
a245daf3d7a143 Christian König 2018-08-01 527 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
a245daf3d7a143 Christian König 2018-08-01 528 case AMDGPU_INFO_HW_IP_INFO: {
a245daf3d7a143 Christian König 2018-08-01 529 struct drm_amdgpu_info_hw_ip ip = {};
a245daf3d7a143 Christian König 2018-08-01 530 int ret;
a245daf3d7a143 Christian König 2018-08-01 531
a245daf3d7a143 Christian König 2018-08-01 532 ret = amdgpu_hw_ip_info(adev, info, &ip);
a245daf3d7a143 Christian König 2018-08-01 533 if (ret)
a245daf3d7a143 Christian König 2018-08-01 534 return ret;
a245daf3d7a143 Christian König 2018-08-01 535
a245daf3d7a143 Christian König 2018-08-01 536 ret = copy_to_user(out, &ip, min((size_t)size, sizeof(ip)));
a245daf3d7a143 Christian König 2018-08-01 537 return ret ? -EFAULT : 0;
d38ceaf99ed015 Alex Deucher 2015-04-20 538 }
d38ceaf99ed015 Alex Deucher 2015-04-20 539 case AMDGPU_INFO_HW_IP_COUNT: {
5fc3aeeb9e553a yanyang1 2015-05-22 540 enum amd_ip_block_type type;
d38ceaf99ed015 Alex Deucher 2015-04-20 541 uint32_t count = 0;
d38ceaf99ed015 Alex Deucher 2015-04-20 542
d38ceaf99ed015 Alex Deucher 2015-04-20 543 switch (info->query_hw_ip.type) {
d38ceaf99ed015 Alex Deucher 2015-04-20 544 case AMDGPU_HW_IP_GFX:
5fc3aeeb9e553a yanyang1 2015-05-22 545 type = AMD_IP_BLOCK_TYPE_GFX;
d38ceaf99ed015 Alex Deucher 2015-04-20 546 break;
d38ceaf99ed015 Alex Deucher 2015-04-20 547 case AMDGPU_HW_IP_COMPUTE:
5fc3aeeb9e553a yanyang1 2015-05-22 548 type = AMD_IP_BLOCK_TYPE_GFX;
d38ceaf99ed015 Alex Deucher 2015-04-20 549 break;
d38ceaf99ed015 Alex Deucher 2015-04-20 550 case AMDGPU_HW_IP_DMA:
5fc3aeeb9e553a yanyang1 2015-05-22 551 type = AMD_IP_BLOCK_TYPE_SDMA;
d38ceaf99ed015 Alex Deucher 2015-04-20 552 break;
d38ceaf99ed015 Alex Deucher 2015-04-20 553 case AMDGPU_HW_IP_UVD:
5fc3aeeb9e553a yanyang1 2015-05-22 554 type = AMD_IP_BLOCK_TYPE_UVD;
d38ceaf99ed015 Alex Deucher 2015-04-20 555 break;
d38ceaf99ed015 Alex Deucher 2015-04-20 556 case AMDGPU_HW_IP_VCE:
5fc3aeeb9e553a yanyang1 2015-05-22 557 type = AMD_IP_BLOCK_TYPE_VCE;
d38ceaf99ed015 Alex Deucher 2015-04-20 558 break;
63defd3f677ef4 Leo Liu 2017-01-10 559 case AMDGPU_HW_IP_UVD_ENC:
63defd3f677ef4 Leo Liu 2017-01-10 560 type = AMD_IP_BLOCK_TYPE_UVD;
63defd3f677ef4 Leo Liu 2017-01-10 561 break;
bdc799e5eee551 Leo Liu 2017-01-25 562 case AMDGPU_HW_IP_VCN_DEC:
cefbc5989f63d3 Leo Liu 2017-02-21 563 case AMDGPU_HW_IP_VCN_ENC:
bdc799e5eee551 Leo Liu 2017-01-25 564 type = AMD_IP_BLOCK_TYPE_VCN;
bdc799e5eee551 Leo Liu 2017-01-25 565 break;
52f2e779ad86da Leo Liu 2019-11-08 566 case AMDGPU_HW_IP_VCN_JPEG:
52f2e779ad86da Leo Liu 2019-11-08 567 type = (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_JPEG)) ?
52f2e779ad86da Leo Liu 2019-11-08 568 AMD_IP_BLOCK_TYPE_JPEG : AMD_IP_BLOCK_TYPE_VCN;
52f2e779ad86da Leo Liu 2019-11-08 569 break;
d38ceaf99ed015 Alex Deucher 2015-04-20 570 default:
d38ceaf99ed015 Alex Deucher 2015-04-20 571 return -EINVAL;
d38ceaf99ed015 Alex Deucher 2015-04-20 572 }
d38ceaf99ed015 Alex Deucher 2015-04-20 573
d38ceaf99ed015 Alex Deucher 2015-04-20 574 for (i = 0; i < adev->num_ip_blocks; i++)
a1255107212675 Alex Deucher 2016-10-13 575 if (adev->ip_blocks[i].version->type == type &&
a1255107212675 Alex Deucher 2016-10-13 576 adev->ip_blocks[i].status.valid &&
d38ceaf99ed015 Alex Deucher 2015-04-20 577 count < AMDGPU_HW_IP_INSTANCE_MAX_COUNT)
d38ceaf99ed015 Alex Deucher 2015-04-20 578 count++;
d38ceaf99ed015 Alex Deucher 2015-04-20 579
d38ceaf99ed015 Alex Deucher 2015-04-20 580 return copy_to_user(out, &count, min(size, 4u)) ? -EFAULT : 0;
d38ceaf99ed015 Alex Deucher 2015-04-20 581 }
d38ceaf99ed015 Alex Deucher 2015-04-20 582 case AMDGPU_INFO_TIMESTAMP:
b95e31fddabbc3 Alex Deucher 2016-07-07 583 ui64 = amdgpu_gfx_get_gpu_clock_counter(adev);
d38ceaf99ed015 Alex Deucher 2015-04-20 584 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
d38ceaf99ed015 Alex Deucher 2015-04-20 585 case AMDGPU_INFO_FW_VERSION: {
d38ceaf99ed015 Alex Deucher 2015-04-20 586 struct drm_amdgpu_info_firmware fw_info;
000cab9a61ea9e Huang Rui 2016-06-12 587 int ret;
d38ceaf99ed015 Alex Deucher 2015-04-20 588
d38ceaf99ed015 Alex Deucher 2015-04-20 589 /* We only support one instance of each IP block right now. */
d38ceaf99ed015 Alex Deucher 2015-04-20 590 if (info->query_fw.ip_instance != 0)
d38ceaf99ed015 Alex Deucher 2015-04-20 591 return -EINVAL;
d38ceaf99ed015 Alex Deucher 2015-04-20 592
000cab9a61ea9e Huang Rui 2016-06-12 593 ret = amdgpu_firmware_info(&fw_info, &info->query_fw, adev);
000cab9a61ea9e Huang Rui 2016-06-12 594 if (ret)
000cab9a61ea9e Huang Rui 2016-06-12 595 return ret;
000cab9a61ea9e Huang Rui 2016-06-12 596
d38ceaf99ed015 Alex Deucher 2015-04-20 597 return copy_to_user(out, &fw_info,
d38ceaf99ed015 Alex Deucher 2015-04-20 598 min((size_t)size, sizeof(fw_info))) ? -EFAULT : 0;
d38ceaf99ed015 Alex Deucher 2015-04-20 599 }
d38ceaf99ed015 Alex Deucher 2015-04-20 600 case AMDGPU_INFO_NUM_BYTES_MOVED:
d38ceaf99ed015 Alex Deucher 2015-04-20 601 ui64 = atomic64_read(&adev->num_bytes_moved);
d38ceaf99ed015 Alex Deucher 2015-04-20 602 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
83a59b6338c714 Marek Olšák 2016-08-17 603 case AMDGPU_INFO_NUM_EVICTIONS:
83a59b6338c714 Marek Olšák 2016-08-17 604 ui64 = atomic64_read(&adev->num_evictions);
83a59b6338c714 Marek Olšák 2016-08-17 605 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
68e2c5ffeb164f Marek Olšák 2017-05-17 606 case AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS:
68e2c5ffeb164f Marek Olšák 2017-05-17 607 ui64 = atomic64_read(&adev->num_vram_cpu_page_faults);
68e2c5ffeb164f Marek Olšák 2017-05-17 608 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
d38ceaf99ed015 Alex Deucher 2015-04-20 609 case AMDGPU_INFO_VRAM_USAGE:
6c28aed6e5b7fa Dave Airlie 2020-08-04 610 ui64 = amdgpu_vram_mgr_usage(ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM));
d38ceaf99ed015 Alex Deucher 2015-04-20 611 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
d38ceaf99ed015 Alex Deucher 2015-04-20 612 case AMDGPU_INFO_VIS_VRAM_USAGE:
6c28aed6e5b7fa Dave Airlie 2020-08-04 613 ui64 = amdgpu_vram_mgr_vis_usage(ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM));
d38ceaf99ed015 Alex Deucher 2015-04-20 614 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
d38ceaf99ed015 Alex Deucher 2015-04-20 615 case AMDGPU_INFO_GTT_USAGE:
6c28aed6e5b7fa Dave Airlie 2020-08-04 616 ui64 = amdgpu_gtt_mgr_usage(ttm_manager_type(&adev->mman.bdev, TTM_PL_TT));
d38ceaf99ed015 Alex Deucher 2015-04-20 617 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
d38ceaf99ed015 Alex Deucher 2015-04-20 618 case AMDGPU_INFO_GDS_CONFIG: {
d38ceaf99ed015 Alex Deucher 2015-04-20 619 struct drm_amdgpu_info_gds gds_info;
d38ceaf99ed015 Alex Deucher 2015-04-20 620
c92b90ccc20bb5 Alex Deucher 2015-04-30 621 memset(&gds_info, 0, sizeof(gds_info));
dca29491c37fd9 Christian König 2019-05-10 622 gds_info.compute_partition_size = adev->gds.gds_size;
dca29491c37fd9 Christian König 2019-05-10 623 gds_info.gds_total_size = adev->gds.gds_size;
dca29491c37fd9 Christian König 2019-05-10 624 gds_info.gws_per_compute_partition = adev->gds.gws_size;
dca29491c37fd9 Christian König 2019-05-10 625 gds_info.oa_per_compute_partition = adev->gds.oa_size;
d38ceaf99ed015 Alex Deucher 2015-04-20 626 return copy_to_user(out, &gds_info,
d38ceaf99ed015 Alex Deucher 2015-04-20 627 min((size_t)size, sizeof(gds_info))) ? -EFAULT : 0;
d38ceaf99ed015 Alex Deucher 2015-04-20 628 }
d38ceaf99ed015 Alex Deucher 2015-04-20 629 case AMDGPU_INFO_VRAM_GTT: {
d38ceaf99ed015 Alex Deucher 2015-04-20 630 struct drm_amdgpu_info_vram_gtt vram_gtt;
d38ceaf99ed015 Alex Deucher 2015-04-20 631
a5ccfe5c20740f Michel Dänzer 2018-07-11 632 vram_gtt.vram_size = adev->gmc.real_vram_size -
9d1b3c78052e87 Christian König 2019-08-30 633 atomic64_read(&adev->vram_pin_size) -
9d1b3c78052e87 Christian König 2019-08-30 634 AMDGPU_VM_RESERVED_VRAM;
9d1b3c78052e87 Christian König 2019-08-30 635 vram_gtt.vram_cpu_accessible_size =
9d1b3c78052e87 Christian König 2019-08-30 636 min(adev->gmc.visible_vram_size -
9d1b3c78052e87 Christian König 2019-08-30 637 atomic64_read(&adev->visible_pin_size),
9d1b3c78052e87 Christian König 2019-08-30 638 vram_gtt.vram_size);
6c28aed6e5b7fa Dave Airlie 2020-08-04 639 vram_gtt.gtt_size = ttm_manager_type(&adev->mman.bdev, TTM_PL_TT)->size;
09628c3f68c6ec Christian König 2017-06-30 640 vram_gtt.gtt_size *= PAGE_SIZE;
a5ccfe5c20740f Michel Dänzer 2018-07-11 641 vram_gtt.gtt_size -= atomic64_read(&adev->gart_pin_size);
d38ceaf99ed015 Alex Deucher 2015-04-20 642 return copy_to_user(out, &vram_gtt,
d38ceaf99ed015 Alex Deucher 2015-04-20 643 min((size_t)size, sizeof(vram_gtt))) ? -EFAULT : 0;
d38ceaf99ed015 Alex Deucher 2015-04-20 644 }
e0adf6c86ceb71 Junwei Zhang 2016-09-29 645 case AMDGPU_INFO_MEMORY: {
e0adf6c86ceb71 Junwei Zhang 2016-09-29 646 struct drm_amdgpu_memory_info mem;
9de59bc201496f Dave Airlie 2020-08-04 647 struct ttm_resource_manager *vram_man =
6c28aed6e5b7fa Dave Airlie 2020-08-04 648 ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM);
9de59bc201496f Dave Airlie 2020-08-04 649 struct ttm_resource_manager *gtt_man =
6c28aed6e5b7fa Dave Airlie 2020-08-04 650 ttm_manager_type(&adev->mman.bdev, TTM_PL_TT);
e0adf6c86ceb71 Junwei Zhang 2016-09-29 651 memset(&mem, 0, sizeof(mem));
770d13b19fdf36 Christian König 2018-01-12 652 mem.vram.total_heap_size = adev->gmc.real_vram_size;
a5ccfe5c20740f Michel Dänzer 2018-07-11 653 mem.vram.usable_heap_size = adev->gmc.real_vram_size -
9d1b3c78052e87 Christian König 2019-08-30 654 atomic64_read(&adev->vram_pin_size) -
9d1b3c78052e87 Christian König 2019-08-30 655 AMDGPU_VM_RESERVED_VRAM;
3c848bb38aca1f Christian König 2017-08-07 656 mem.vram.heap_usage =
6c28aed6e5b7fa Dave Airlie 2020-08-04 657 amdgpu_vram_mgr_usage(vram_man);
e0adf6c86ceb71 Junwei Zhang 2016-09-29 658 mem.vram.max_allocation = mem.vram.usable_heap_size * 3 / 4;
e0adf6c86ceb71 Junwei Zhang 2016-09-29 659
e0adf6c86ceb71 Junwei Zhang 2016-09-29 660 mem.cpu_accessible_vram.total_heap_size =
770d13b19fdf36 Christian König 2018-01-12 661 adev->gmc.visible_vram_size;
9d1b3c78052e87 Christian König 2019-08-30 662 mem.cpu_accessible_vram.usable_heap_size =
9d1b3c78052e87 Christian König 2019-08-30 663 min(adev->gmc.visible_vram_size -
9d1b3c78052e87 Christian König 2019-08-30 664 atomic64_read(&adev->visible_pin_size),
9d1b3c78052e87 Christian König 2019-08-30 665 mem.vram.usable_heap_size);
e0adf6c86ceb71 Junwei Zhang 2016-09-29 666 mem.cpu_accessible_vram.heap_usage =
6c28aed6e5b7fa Dave Airlie 2020-08-04 667 amdgpu_vram_mgr_vis_usage(vram_man);
e0adf6c86ceb71 Junwei Zhang 2016-09-29 668 mem.cpu_accessible_vram.max_allocation =
e0adf6c86ceb71 Junwei Zhang 2016-09-29 669 mem.cpu_accessible_vram.usable_heap_size * 3 / 4;
e0adf6c86ceb71 Junwei Zhang 2016-09-29 670
6c28aed6e5b7fa Dave Airlie 2020-08-04 671 mem.gtt.total_heap_size = gtt_man->size;
09628c3f68c6ec Christian König 2017-06-30 672 mem.gtt.total_heap_size *= PAGE_SIZE;
a5ccfe5c20740f Michel Dänzer 2018-07-11 673 mem.gtt.usable_heap_size = mem.gtt.total_heap_size -
a5ccfe5c20740f Michel Dänzer 2018-07-11 674 atomic64_read(&adev->gart_pin_size);
9255d77d8cfd71 Christian König 2017-08-07 675 mem.gtt.heap_usage =
6c28aed6e5b7fa Dave Airlie 2020-08-04 676 amdgpu_gtt_mgr_usage(gtt_man);
e0adf6c86ceb71 Junwei Zhang 2016-09-29 677 mem.gtt.max_allocation = mem.gtt.usable_heap_size * 3 / 4;
e0adf6c86ceb71 Junwei Zhang 2016-09-29 678
e0adf6c86ceb71 Junwei Zhang 2016-09-29 679 return copy_to_user(out, &mem,
e0adf6c86ceb71 Junwei Zhang 2016-09-29 680 min((size_t)size, sizeof(mem)))
cfa32556e58d8a Junwei Zhang 2016-09-21 681 ? -EFAULT : 0;
cfa32556e58d8a Junwei Zhang 2016-09-21 682 }
d38ceaf99ed015 Alex Deucher 2015-04-20 683 case AMDGPU_INFO_READ_MMR_REG: {
0d2edd3791bb17 Dan Carpenter 2015-09-23 684 unsigned n, alloc_size;
d38ceaf99ed015 Alex Deucher 2015-04-20 685 uint32_t *regs;
d38ceaf99ed015 Alex Deucher 2015-04-20 686 unsigned se_num = (info->read_mmr_reg.instance >>
d38ceaf99ed015 Alex Deucher 2015-04-20 687 AMDGPU_INFO_MMR_SE_INDEX_SHIFT) &
d38ceaf99ed015 Alex Deucher 2015-04-20 688 AMDGPU_INFO_MMR_SE_INDEX_MASK;
d38ceaf99ed015 Alex Deucher 2015-04-20 689 unsigned sh_num = (info->read_mmr_reg.instance >>
d38ceaf99ed015 Alex Deucher 2015-04-20 690 AMDGPU_INFO_MMR_SH_INDEX_SHIFT) &
d38ceaf99ed015 Alex Deucher 2015-04-20 691 AMDGPU_INFO_MMR_SH_INDEX_MASK;
d38ceaf99ed015 Alex Deucher 2015-04-20 692
d38ceaf99ed015 Alex Deucher 2015-04-20 693 /* set full masks if the userspace set all bits
d38ceaf99ed015 Alex Deucher 2015-04-20 694 * in the bitfields */
d38ceaf99ed015 Alex Deucher 2015-04-20 695 if (se_num == AMDGPU_INFO_MMR_SE_INDEX_MASK)
d38ceaf99ed015 Alex Deucher 2015-04-20 696 se_num = 0xffffffff;
b5b97cab55eb71 Alex Deucher 2020-08-25 697 else if (se_num >= AMDGPU_GFX_MAX_SE)
b5b97cab55eb71 Alex Deucher 2020-08-25 698 return -EINVAL;
d38ceaf99ed015 Alex Deucher 2015-04-20 699 if (sh_num == AMDGPU_INFO_MMR_SH_INDEX_MASK)
d38ceaf99ed015 Alex Deucher 2015-04-20 700 sh_num = 0xffffffff;
b5b97cab55eb71 Alex Deucher 2020-08-25 701 else if (sh_num >= AMDGPU_GFX_MAX_SH_PER_SE)
b5b97cab55eb71 Alex Deucher 2020-08-25 702 return -EINVAL;
d38ceaf99ed015 Alex Deucher 2015-04-20 703
73d8e6c7b841d9 Trek 2019-08-31 704 if (info->read_mmr_reg.count > 128)
73d8e6c7b841d9 Trek 2019-08-31 705 return -EINVAL;
73d8e6c7b841d9 Trek 2019-08-31 706
0d2edd3791bb17 Dan Carpenter 2015-09-23 707 regs = kmalloc_array(info->read_mmr_reg.count, sizeof(*regs), GFP_KERNEL);
d38ceaf99ed015 Alex Deucher 2015-04-20 708 if (!regs)
d38ceaf99ed015 Alex Deucher 2015-04-20 709 return -ENOMEM;
0d2edd3791bb17 Dan Carpenter 2015-09-23 710 alloc_size = info->read_mmr_reg.count * sizeof(*regs);
d38ceaf99ed015 Alex Deucher 2015-04-20 711
ca9317b9183b93 Alex Deucher 2019-11-14 712 amdgpu_gfx_off_ctrl(adev, false);
ca9317b9183b93 Alex Deucher 2019-11-14 713 for (i = 0; i < info->read_mmr_reg.count; i++) {
d38ceaf99ed015 Alex Deucher 2015-04-20 714 if (amdgpu_asic_read_register(adev, se_num, sh_num,
d38ceaf99ed015 Alex Deucher 2015-04-20 715 info->read_mmr_reg.dword_offset + i,
d38ceaf99ed015 Alex Deucher 2015-04-20 716 ®s[i])) {
d38ceaf99ed015 Alex Deucher 2015-04-20 717 DRM_DEBUG_KMS("unallowed offset %#x\n",
d38ceaf99ed015 Alex Deucher 2015-04-20 718 info->read_mmr_reg.dword_offset + i);
d38ceaf99ed015 Alex Deucher 2015-04-20 719 kfree(regs);
ca9317b9183b93 Alex Deucher 2019-11-14 720 amdgpu_gfx_off_ctrl(adev, true);
d38ceaf99ed015 Alex Deucher 2015-04-20 721 return -EFAULT;
d38ceaf99ed015 Alex Deucher 2015-04-20 722 }
ca9317b9183b93 Alex Deucher 2019-11-14 723 }
ca9317b9183b93 Alex Deucher 2019-11-14 724 amdgpu_gfx_off_ctrl(adev, true);
d38ceaf99ed015 Alex Deucher 2015-04-20 725 n = copy_to_user(out, regs, min(size, alloc_size));
d38ceaf99ed015 Alex Deucher 2015-04-20 726 kfree(regs);
d38ceaf99ed015 Alex Deucher 2015-04-20 727 return n ? -EFAULT : 0;
d38ceaf99ed015 Alex Deucher 2015-04-20 728 }
d38ceaf99ed015 Alex Deucher 2015-04-20 729 case AMDGPU_INFO_DEV_INFO: {
a5a52a43eac068 Lee Jones 2020-11-06 730 struct drm_amdgpu_info_device *dev_info;
5b565e0e5a9872 Christian König 2017-11-07 731 uint64_t vm_size;
a5a52a43eac068 Lee Jones 2020-11-06 732 int ret;
a5a52a43eac068 Lee Jones 2020-11-06 733
a5a52a43eac068 Lee Jones 2020-11-06 734 dev_info = kzalloc(sizeof(*dev_info), GFP_KERNEL);
a5a52a43eac068 Lee Jones 2020-11-06 735 if (!dev_info)
a5a52a43eac068 Lee Jones 2020-11-06 736 return -ENOMEM;
d38ceaf99ed015 Alex Deucher 2015-04-20 737
8f66090b7bb7f2 Thomas Zimmermann 2021-01-07 738 dev_info->device_id = adev->pdev->device;
a5a52a43eac068 Lee Jones 2020-11-06 739 dev_info->chip_rev = adev->rev_id;
a5a52a43eac068 Lee Jones 2020-11-06 740 dev_info->external_rev = adev->external_rev_id;
8f66090b7bb7f2 Thomas Zimmermann 2021-01-07 741 dev_info->pci_rev = adev->pdev->revision;
a5a52a43eac068 Lee Jones 2020-11-06 742 dev_info->family = adev->family;
a5a52a43eac068 Lee Jones 2020-11-06 743 dev_info->num_shader_engines = adev->gfx.config.max_shader_engines;
a5a52a43eac068 Lee Jones 2020-11-06 744 dev_info->num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se;
d38ceaf99ed015 Alex Deucher 2015-04-20 745 /* return all clocks in KHz */
a5a52a43eac068 Lee Jones 2020-11-06 746 dev_info->gpu_counter_freq = amdgpu_asic_get_xclk(adev) * 10;
32bf7106e072b5 Ken Wang 2015-06-03 747 if (adev->pm.dpm_enabled) {
a5a52a43eac068 Lee Jones 2020-11-06 748 dev_info->max_engine_clock = amdgpu_dpm_get_sclk(adev, false) * 10;
a5a52a43eac068 Lee Jones 2020-11-06 749 dev_info->max_memory_clock = amdgpu_dpm_get_mclk(adev, false) * 10;
32bf7106e072b5 Ken Wang 2015-06-03 750 } else {
a5a52a43eac068 Lee Jones 2020-11-06 751 dev_info->max_engine_clock = adev->clock.default_sclk * 10;
a5a52a43eac068 Lee Jones 2020-11-06 752 dev_info->max_memory_clock = adev->clock.default_mclk * 10;
32bf7106e072b5 Ken Wang 2015-06-03 753 }
a5a52a43eac068 Lee Jones 2020-11-06 754 dev_info->enabled_rb_pipes_mask = adev->gfx.config.backend_enable_mask;
a5a52a43eac068 Lee Jones 2020-11-06 755 dev_info->num_rb_pipes = adev->gfx.config.max_backends_per_se *
0b10029d826ed8 Alex Deucher 2016-06-17 756 adev->gfx.config.max_shader_engines;
a5a52a43eac068 Lee Jones 2020-11-06 757 dev_info->num_hw_gfx_contexts = adev->gfx.config.max_hw_contexts;
a5a52a43eac068 Lee Jones 2020-11-06 758 dev_info->_pad = 0;
a5a52a43eac068 Lee Jones 2020-11-06 759 dev_info->ids_flags = 0;
2f7d10b393c83a Jammy Zhou 2015-07-22 760 if (adev->flags & AMD_IS_APU)
a5a52a43eac068 Lee Jones 2020-11-06 761 dev_info->ids_flags |= AMDGPU_IDS_FLAGS_FUSION;
f92d5c6123f4f0 Jack Xiao 2019-01-10 762 if (amdgpu_mcbp || amdgpu_sriov_vf(adev))
a5a52a43eac068 Lee Jones 2020-11-06 763 dev_info->ids_flags |= AMDGPU_IDS_FLAGS_PREEMPTION;
16c642ec3fe9a1 Pierre-Eric Pelloux-Prayer 2020-07-30 764 if (amdgpu_is_tmz(adev))
a5a52a43eac068 Lee Jones 2020-11-06 765 dev_info->ids_flags |= AMDGPU_IDS_FLAGS_TMZ;
5b565e0e5a9872 Christian König 2017-11-07 766
5b565e0e5a9872 Christian König 2017-11-07 767 vm_size = adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE;
a3e9a15a25d5df Christian König 2018-01-22 768 vm_size -= AMDGPU_VA_RESERVED_SIZE;
6b034e25c86805 Christian König 2018-01-29 769
6b034e25c86805 Christian König 2018-01-29 770 /* Older VCE FW versions are buggy and can handle only 40bits */
09b6f25b55d9c6 Christian König 2018-08-15 771 if (adev->vce.fw_version &&
09b6f25b55d9c6 Christian König 2018-08-15 772 adev->vce.fw_version < AMDGPU_VCE_FW_53_45)
6b034e25c86805 Christian König 2018-01-29 773 vm_size = min(vm_size, 1ULL << 40);
6b034e25c86805 Christian König 2018-01-29 774
a5a52a43eac068 Lee Jones 2020-11-06 775 dev_info->virtual_address_offset = AMDGPU_VA_RESERVED_SIZE;
a5a52a43eac068 Lee Jones 2020-11-06 776 dev_info->virtual_address_max =
ad9a5b78f585e9 Christian König 2018-08-27 777 min(vm_size, AMDGPU_GMC_HOLE_START);
5b565e0e5a9872 Christian König 2017-11-07 778
ad9a5b78f585e9 Christian König 2018-08-27 779 if (vm_size > AMDGPU_GMC_HOLE_START) {
a5a52a43eac068 Lee Jones 2020-11-06 780 dev_info->high_va_offset = AMDGPU_GMC_HOLE_END;
a5a52a43eac068 Lee Jones 2020-11-06 781 dev_info->high_va_max = AMDGPU_GMC_HOLE_END | vm_size;
a5a52a43eac068 Lee Jones 2020-11-06 782 }
a5a52a43eac068 Lee Jones 2020-11-06 783 dev_info->virtual_address_alignment = max((int)PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE);
a5a52a43eac068 Lee Jones 2020-11-06 784 dev_info->pte_fragment_size = (1 << adev->vm_manager.fragment_size) * AMDGPU_GPU_PAGE_SIZE;
a5a52a43eac068 Lee Jones 2020-11-06 785 dev_info->gart_page_size = AMDGPU_GPU_PAGE_SIZE;
a5a52a43eac068 Lee Jones 2020-11-06 786 dev_info->cu_active_number = adev->gfx.cu_info.number;
a5a52a43eac068 Lee Jones 2020-11-06 787 dev_info->cu_ao_mask = adev->gfx.cu_info.ao_cu_mask;
a5a52a43eac068 Lee Jones 2020-11-06 788 dev_info->ce_ram_size = adev->gfx.ce_ram_size;
a5a52a43eac068 Lee Jones 2020-11-06 789 memcpy(&dev_info->cu_ao_bitmap[0], &adev->gfx.cu_info.ao_cu_bitmap[0],
dbfe85ea496728 Flora Cui 2017-06-20 790 sizeof(adev->gfx.cu_info.ao_cu_bitmap));
a5a52a43eac068 Lee Jones 2020-11-06 791 memcpy(&dev_info->cu_bitmap[0], &adev->gfx.cu_info.bitmap[0],
7dae69a2905c34 Alex Deucher 2016-05-03 792 sizeof(adev->gfx.cu_info.bitmap));
a5a52a43eac068 Lee Jones 2020-11-06 793 dev_info->vram_type = adev->gmc.vram_type;
a5a52a43eac068 Lee Jones 2020-11-06 794 dev_info->vram_bit_width = adev->gmc.vram_width;
a5a52a43eac068 Lee Jones 2020-11-06 795 dev_info->vce_harvest_config = adev->vce.harvest_config;
a5a52a43eac068 Lee Jones 2020-11-06 796 dev_info->gc_double_offchip_lds_buf =
df6e2c4aeb263f Junwei Zhang 2017-02-17 797 adev->gfx.config.double_offchip_lds_buf;
a5a52a43eac068 Lee Jones 2020-11-06 798 dev_info->wave_front_size = adev->gfx.cu_info.wave_front_size;
a5a52a43eac068 Lee Jones 2020-11-06 799 dev_info->num_shader_visible_vgprs = adev->gfx.config.max_gprs;
a5a52a43eac068 Lee Jones 2020-11-06 800 dev_info->num_cu_per_sh = adev->gfx.config.max_cu_per_sh;
a5a52a43eac068 Lee Jones 2020-11-06 801 dev_info->num_tcc_blocks = adev->gfx.config.max_texture_channel_caches;
a5a52a43eac068 Lee Jones 2020-11-06 802 dev_info->gs_vgt_table_depth = adev->gfx.config.gs_vgt_table_depth;
a5a52a43eac068 Lee Jones 2020-11-06 803 dev_info->gs_prim_buffer_depth = adev->gfx.config.gs_prim_buffer_depth;
a5a52a43eac068 Lee Jones 2020-11-06 804 dev_info->max_gs_waves_per_vgt = adev->gfx.config.max_gs_threads;
bce23e00f3369c Alex Deucher 2017-03-28 805
be9250fb962d36 Hawking Zhang 2018-06-12 806 if (adev->family >= AMDGPU_FAMILY_NV)
a5a52a43eac068 Lee Jones 2020-11-06 807 dev_info->pa_sc_tile_steering_override =
be9250fb962d36 Hawking Zhang 2018-06-12 808 adev->gfx.config.pa_sc_tile_steering_override;
be9250fb962d36 Hawking Zhang 2018-06-12 809
a5a52a43eac068 Lee Jones 2020-11-06 810 dev_info->tcc_disabled_mask = adev->gfx.config.tcc_disabled_mask;
815fb4c9d7da86 Marek Olšák 2019-09-24 811
a5a52a43eac068 Lee Jones 2020-11-06 812 ret = copy_to_user(out, dev_info,
a5a52a43eac068 Lee Jones 2020-11-06 813 min((size_t)size, sizeof(*dev_info))) ? -EFAULT : 0;
a5a52a43eac068 Lee Jones 2020-11-06 814 kfree(dev_info);
a5a52a43eac068 Lee Jones 2020-11-06 815 return ret;
d38ceaf99ed015 Alex Deucher 2015-04-20 816 }
07fecde5d3ece7 Alex Deucher 2016-10-07 817 case AMDGPU_INFO_VCE_CLOCK_TABLE: {
07fecde5d3ece7 Alex Deucher 2016-10-07 818 unsigned i;
07fecde5d3ece7 Alex Deucher 2016-10-07 819 struct drm_amdgpu_info_vce_clock_table vce_clk_table = {};
07fecde5d3ece7 Alex Deucher 2016-10-07 820 struct amd_vce_state *vce_state;
07fecde5d3ece7 Alex Deucher 2016-10-07 821
07fecde5d3ece7 Alex Deucher 2016-10-07 822 for (i = 0; i < AMDGPU_VCE_CLOCK_TABLE_ENTRIES; i++) {
07fecde5d3ece7 Alex Deucher 2016-10-07 823 vce_state = amdgpu_dpm_get_vce_clock_state(adev, i);
07fecde5d3ece7 Alex Deucher 2016-10-07 824 if (vce_state) {
07fecde5d3ece7 Alex Deucher 2016-10-07 825 vce_clk_table.entries[i].sclk = vce_state->sclk;
07fecde5d3ece7 Alex Deucher 2016-10-07 826 vce_clk_table.entries[i].mclk = vce_state->mclk;
07fecde5d3ece7 Alex Deucher 2016-10-07 827 vce_clk_table.entries[i].eclk = vce_state->evclk;
07fecde5d3ece7 Alex Deucher 2016-10-07 828 vce_clk_table.num_valid_entries++;
07fecde5d3ece7 Alex Deucher 2016-10-07 829 }
07fecde5d3ece7 Alex Deucher 2016-10-07 830 }
07fecde5d3ece7 Alex Deucher 2016-10-07 831
07fecde5d3ece7 Alex Deucher 2016-10-07 832 return copy_to_user(out, &vce_clk_table,
07fecde5d3ece7 Alex Deucher 2016-10-07 833 min((size_t)size, sizeof(vce_clk_table))) ? -EFAULT : 0;
07fecde5d3ece7 Alex Deucher 2016-10-07 834 }
40ee5888faecf4 Evan Quan 2016-12-07 835 case AMDGPU_INFO_VBIOS: {
40ee5888faecf4 Evan Quan 2016-12-07 836 uint32_t bios_size = adev->bios_size;
40ee5888faecf4 Evan Quan 2016-12-07 837
40ee5888faecf4 Evan Quan 2016-12-07 838 switch (info->vbios_info.type) {
40ee5888faecf4 Evan Quan 2016-12-07 839 case AMDGPU_INFO_VBIOS_SIZE:
40ee5888faecf4 Evan Quan 2016-12-07 840 return copy_to_user(out, &bios_size,
40ee5888faecf4 Evan Quan 2016-12-07 841 min((size_t)size, sizeof(bios_size)))
40ee5888faecf4 Evan Quan 2016-12-07 842 ? -EFAULT : 0;
40ee5888faecf4 Evan Quan 2016-12-07 843 case AMDGPU_INFO_VBIOS_IMAGE: {
40ee5888faecf4 Evan Quan 2016-12-07 844 uint8_t *bios;
40ee5888faecf4 Evan Quan 2016-12-07 845 uint32_t bios_offset = info->vbios_info.offset;
40ee5888faecf4 Evan Quan 2016-12-07 846
40ee5888faecf4 Evan Quan 2016-12-07 847 if (bios_offset >= bios_size)
40ee5888faecf4 Evan Quan 2016-12-07 848 return -EINVAL;
40ee5888faecf4 Evan Quan 2016-12-07 849
40ee5888faecf4 Evan Quan 2016-12-07 850 bios = adev->bios + bios_offset;
40ee5888faecf4 Evan Quan 2016-12-07 851 return copy_to_user(out, bios,
40ee5888faecf4 Evan Quan 2016-12-07 852 min((size_t)size, (size_t)(bios_size - bios_offset)))
40ee5888faecf4 Evan Quan 2016-12-07 853 ? -EFAULT : 0;
40ee5888faecf4 Evan Quan 2016-12-07 854 }
40ee5888faecf4 Evan Quan 2016-12-07 855 default:
40ee5888faecf4 Evan Quan 2016-12-07 856 DRM_DEBUG_KMS("Invalid request %d\n",
40ee5888faecf4 Evan Quan 2016-12-07 857 info->vbios_info.type);
40ee5888faecf4 Evan Quan 2016-12-07 858 return -EINVAL;
40ee5888faecf4 Evan Quan 2016-12-07 859 }
40ee5888faecf4 Evan Quan 2016-12-07 860 }
44879b6261530b Arindam Nath 2016-12-12 861 case AMDGPU_INFO_NUM_HANDLES: {
44879b6261530b Arindam Nath 2016-12-12 862 struct drm_amdgpu_info_num_handles handle;
44879b6261530b Arindam Nath 2016-12-12 863
44879b6261530b Arindam Nath 2016-12-12 864 switch (info->query_hw_ip.type) {
44879b6261530b Arindam Nath 2016-12-12 865 case AMDGPU_HW_IP_UVD:
44879b6261530b Arindam Nath 2016-12-12 866 /* Starting Polaris, we support unlimited UVD handles */
44879b6261530b Arindam Nath 2016-12-12 867 if (adev->asic_type < CHIP_POLARIS10) {
44879b6261530b Arindam Nath 2016-12-12 868 handle.uvd_max_handles = adev->uvd.max_handles;
44879b6261530b Arindam Nath 2016-12-12 869 handle.uvd_used_handles = amdgpu_uvd_used_handles(adev);
44879b6261530b Arindam Nath 2016-12-12 870
44879b6261530b Arindam Nath 2016-12-12 871 return copy_to_user(out, &handle,
44879b6261530b Arindam Nath 2016-12-12 872 min((size_t)size, sizeof(handle))) ? -EFAULT : 0;
44879b6261530b Arindam Nath 2016-12-12 873 } else {
44879b6261530b Arindam Nath 2016-12-12 874 return -ENODATA;
44879b6261530b Arindam Nath 2016-12-12 875 }
44879b6261530b Arindam Nath 2016-12-12 876
44879b6261530b Arindam Nath 2016-12-12 877 break;
44879b6261530b Arindam Nath 2016-12-12 878 default:
44879b6261530b Arindam Nath 2016-12-12 879 return -EINVAL;
44879b6261530b Arindam Nath 2016-12-12 880 }
44879b6261530b Arindam Nath 2016-12-12 881 }
5ebbac4b5c9159 Alex Deucher 2017-03-08 882 case AMDGPU_INFO_SENSOR: {
b13aa1091fb200 Rex Zhu 2018-03-26 883 if (!adev->pm.dpm_enabled)
5ebbac4b5c9159 Alex Deucher 2017-03-08 884 return -ENOENT;
5ebbac4b5c9159 Alex Deucher 2017-03-08 885
5ebbac4b5c9159 Alex Deucher 2017-03-08 886 switch (info->sensor_info.type) {
5ebbac4b5c9159 Alex Deucher 2017-03-08 887 case AMDGPU_INFO_SENSOR_GFX_SCLK:
5ebbac4b5c9159 Alex Deucher 2017-03-08 888 /* get sclk in Mhz */
5ebbac4b5c9159 Alex Deucher 2017-03-08 889 if (amdgpu_dpm_read_sensor(adev,
5ebbac4b5c9159 Alex Deucher 2017-03-08 890 AMDGPU_PP_SENSOR_GFX_SCLK,
5ebbac4b5c9159 Alex Deucher 2017-03-08 891 (void *)&ui32, &ui32_size)) {
5ebbac4b5c9159 Alex Deucher 2017-03-08 892 return -EINVAL;
5ebbac4b5c9159 Alex Deucher 2017-03-08 893 }
5ebbac4b5c9159 Alex Deucher 2017-03-08 894 ui32 /= 100;
5ebbac4b5c9159 Alex Deucher 2017-03-08 895 break;
5ebbac4b5c9159 Alex Deucher 2017-03-08 896 case AMDGPU_INFO_SENSOR_GFX_MCLK:
5ebbac4b5c9159 Alex Deucher 2017-03-08 897 /* get mclk in Mhz */
5ebbac4b5c9159 Alex Deucher 2017-03-08 898 if (amdgpu_dpm_read_sensor(adev,
5ebbac4b5c9159 Alex Deucher 2017-03-08 899 AMDGPU_PP_SENSOR_GFX_MCLK,
5ebbac4b5c9159 Alex Deucher 2017-03-08 900 (void *)&ui32, &ui32_size)) {
5ebbac4b5c9159 Alex Deucher 2017-03-08 901 return -EINVAL;
5ebbac4b5c9159 Alex Deucher 2017-03-08 902 }
5ebbac4b5c9159 Alex Deucher 2017-03-08 903 ui32 /= 100;
5ebbac4b5c9159 Alex Deucher 2017-03-08 904 break;
5ebbac4b5c9159 Alex Deucher 2017-03-08 905 case AMDGPU_INFO_SENSOR_GPU_TEMP:
5ebbac4b5c9159 Alex Deucher 2017-03-08 906 /* get temperature in millidegrees C */
5ebbac4b5c9159 Alex Deucher 2017-03-08 907 if (amdgpu_dpm_read_sensor(adev,
5ebbac4b5c9159 Alex Deucher 2017-03-08 908 AMDGPU_PP_SENSOR_GPU_TEMP,
5ebbac4b5c9159 Alex Deucher 2017-03-08 909 (void *)&ui32, &ui32_size)) {
5ebbac4b5c9159 Alex Deucher 2017-03-08 910 return -EINVAL;
5ebbac4b5c9159 Alex Deucher 2017-03-08 911 }
5ebbac4b5c9159 Alex Deucher 2017-03-08 912 break;
5ebbac4b5c9159 Alex Deucher 2017-03-08 913 case AMDGPU_INFO_SENSOR_GPU_LOAD:
5ebbac4b5c9159 Alex Deucher 2017-03-08 914 /* get GPU load */
5ebbac4b5c9159 Alex Deucher 2017-03-08 915 if (amdgpu_dpm_read_sensor(adev,
5ebbac4b5c9159 Alex Deucher 2017-03-08 916 AMDGPU_PP_SENSOR_GPU_LOAD,
5ebbac4b5c9159 Alex Deucher 2017-03-08 917 (void *)&ui32, &ui32_size)) {
5ebbac4b5c9159 Alex Deucher 2017-03-08 918 return -EINVAL;
5ebbac4b5c9159 Alex Deucher 2017-03-08 919 }
5ebbac4b5c9159 Alex Deucher 2017-03-08 920 break;
5ebbac4b5c9159 Alex Deucher 2017-03-08 921 case AMDGPU_INFO_SENSOR_GPU_AVG_POWER:
5ebbac4b5c9159 Alex Deucher 2017-03-08 922 /* get average GPU power */
5ebbac4b5c9159 Alex Deucher 2017-03-08 923 if (amdgpu_dpm_read_sensor(adev,
5ebbac4b5c9159 Alex Deucher 2017-03-08 924 AMDGPU_PP_SENSOR_GPU_POWER,
5b79d0482f3c1e Rex Zhu 2018-04-04 925 (void *)&ui32, &ui32_size)) {
5ebbac4b5c9159 Alex Deucher 2017-03-08 926 return -EINVAL;
5ebbac4b5c9159 Alex Deucher 2017-03-08 927 }
5b79d0482f3c1e Rex Zhu 2018-04-04 928 ui32 >>= 8;
5ebbac4b5c9159 Alex Deucher 2017-03-08 929 break;
5ebbac4b5c9159 Alex Deucher 2017-03-08 930 case AMDGPU_INFO_SENSOR_VDDNB:
5ebbac4b5c9159 Alex Deucher 2017-03-08 931 /* get VDDNB in millivolts */
5ebbac4b5c9159 Alex Deucher 2017-03-08 932 if (amdgpu_dpm_read_sensor(adev,
5ebbac4b5c9159 Alex Deucher 2017-03-08 933 AMDGPU_PP_SENSOR_VDDNB,
5ebbac4b5c9159 Alex Deucher 2017-03-08 934 (void *)&ui32, &ui32_size)) {
5ebbac4b5c9159 Alex Deucher 2017-03-08 935 return -EINVAL;
5ebbac4b5c9159 Alex Deucher 2017-03-08 936 }
5ebbac4b5c9159 Alex Deucher 2017-03-08 937 break;
5ebbac4b5c9159 Alex Deucher 2017-03-08 938 case AMDGPU_INFO_SENSOR_VDDGFX:
5ebbac4b5c9159 Alex Deucher 2017-03-08 939 /* get VDDGFX in millivolts */
5ebbac4b5c9159 Alex Deucher 2017-03-08 940 if (amdgpu_dpm_read_sensor(adev,
5ebbac4b5c9159 Alex Deucher 2017-03-08 941 AMDGPU_PP_SENSOR_VDDGFX,
5ebbac4b5c9159 Alex Deucher 2017-03-08 942 (void *)&ui32, &ui32_size)) {
5ebbac4b5c9159 Alex Deucher 2017-03-08 943 return -EINVAL;
5ebbac4b5c9159 Alex Deucher 2017-03-08 944 }
5ebbac4b5c9159 Alex Deucher 2017-03-08 945 break;
60bbade2a63de3 Rex Zhu 2018-01-17 946 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK:
60bbade2a63de3 Rex Zhu 2018-01-17 947 /* get stable pstate sclk in Mhz */
60bbade2a63de3 Rex Zhu 2018-01-17 948 if (amdgpu_dpm_read_sensor(adev,
60bbade2a63de3 Rex Zhu 2018-01-17 949 AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK,
60bbade2a63de3 Rex Zhu 2018-01-17 950 (void *)&ui32, &ui32_size)) {
60bbade2a63de3 Rex Zhu 2018-01-17 951 return -EINVAL;
60bbade2a63de3 Rex Zhu 2018-01-17 952 }
60bbade2a63de3 Rex Zhu 2018-01-17 953 ui32 /= 100;
60bbade2a63de3 Rex Zhu 2018-01-17 954 break;
60bbade2a63de3 Rex Zhu 2018-01-17 955 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK:
60bbade2a63de3 Rex Zhu 2018-01-17 956 /* get stable pstate mclk in Mhz */
60bbade2a63de3 Rex Zhu 2018-01-17 957 if (amdgpu_dpm_read_sensor(adev,
60bbade2a63de3 Rex Zhu 2018-01-17 958 AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK,
60bbade2a63de3 Rex Zhu 2018-01-17 959 (void *)&ui32, &ui32_size)) {
60bbade2a63de3 Rex Zhu 2018-01-17 960 return -EINVAL;
60bbade2a63de3 Rex Zhu 2018-01-17 961 }
60bbade2a63de3 Rex Zhu 2018-01-17 962 ui32 /= 100;
60bbade2a63de3 Rex Zhu 2018-01-17 963 break;
5ebbac4b5c9159 Alex Deucher 2017-03-08 964 default:
5ebbac4b5c9159 Alex Deucher 2017-03-08 965 DRM_DEBUG_KMS("Invalid request %d\n",
5ebbac4b5c9159 Alex Deucher 2017-03-08 966 info->sensor_info.type);
5ebbac4b5c9159 Alex Deucher 2017-03-08 967 return -EINVAL;
5ebbac4b5c9159 Alex Deucher 2017-03-08 968 }
5ebbac4b5c9159 Alex Deucher 2017-03-08 969 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
5ebbac4b5c9159 Alex Deucher 2017-03-08 970 }
1f7251b73e0839 Christian König 2017-10-09 971 case AMDGPU_INFO_VRAM_LOST_COUNTER:
1f7251b73e0839 Christian König 2017-10-09 972 ui32 = atomic_read(&adev->vram_lost_counter);
1f7251b73e0839 Christian König 2017-10-09 973 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
5cb771143ed955 xinhui pan 2018-12-17 974 case AMDGPU_INFO_RAS_ENABLED_FEATURES: {
5cb771143ed955 xinhui pan 2018-12-17 975 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
1febb00ecb1af5 xinhui pan 2019-03-07 976 uint64_t ras_mask;
5cb771143ed955 xinhui pan 2018-12-17 977
5cb771143ed955 xinhui pan 2018-12-17 978 if (!ras)
5cb771143ed955 xinhui pan 2018-12-17 979 return -EINVAL;
1febb00ecb1af5 xinhui pan 2019-03-07 980 ras_mask = (uint64_t)ras->supported << 32 | ras->features;
1febb00ecb1af5 xinhui pan 2019-03-07 981
1febb00ecb1af5 xinhui pan 2019-03-07 982 return copy_to_user(out, &ras_mask,
1febb00ecb1af5 xinhui pan 2019-03-07 983 min_t(u64, size, sizeof(ras_mask))) ?
5cb771143ed955 xinhui pan 2018-12-17 984 -EFAULT : 0;
5cb771143ed955 xinhui pan 2018-12-17 985 }
555fc7fbb2a2b2 Alex Deucher 2021-01-07 986 case AMDGPU_INFO_VIDEO_CAPS: {
555fc7fbb2a2b2 Alex Deucher 2021-01-07 987 const struct amdgpu_video_codecs *codecs;
555fc7fbb2a2b2 Alex Deucher 2021-01-07 988 struct drm_amdgpu_info_video_caps *caps;
555fc7fbb2a2b2 Alex Deucher 2021-01-07 989 int r;
555fc7fbb2a2b2 Alex Deucher 2021-01-07 990
555fc7fbb2a2b2 Alex Deucher 2021-01-07 991 caps = kzalloc(sizeof(*caps), GFP_KERNEL);
555fc7fbb2a2b2 Alex Deucher 2021-01-07 992 if (!caps)
555fc7fbb2a2b2 Alex Deucher 2021-01-07 993 return -ENOMEM;
555fc7fbb2a2b2 Alex Deucher 2021-01-07 994
555fc7fbb2a2b2 Alex Deucher 2021-01-07 995 switch (info->video_cap.type) {
555fc7fbb2a2b2 Alex Deucher 2021-01-07 996 case AMDGPU_INFO_VIDEO_CAPS_DECODE:
555fc7fbb2a2b2 Alex Deucher 2021-01-07 997 r = amdgpu_asic_query_video_codecs(adev, false, &codecs);
555fc7fbb2a2b2 Alex Deucher 2021-01-07 998 if (r)
555fc7fbb2a2b2 Alex Deucher 2021-01-07 @999 return -EINVAL;
555fc7fbb2a2b2 Alex Deucher 2021-01-07 1000 break;
555fc7fbb2a2b2 Alex Deucher 2021-01-07 1001 case AMDGPU_INFO_VIDEO_CAPS_ENCODE:
555fc7fbb2a2b2 Alex Deucher 2021-01-07 1002 r = amdgpu_asic_query_video_codecs(adev, true, &codecs);
555fc7fbb2a2b2 Alex Deucher 2021-01-07 1003 if (r)
555fc7fbb2a2b2 Alex Deucher 2021-01-07 1004 return -EINVAL;
555fc7fbb2a2b2 Alex Deucher 2021-01-07 1005 break;
555fc7fbb2a2b2 Alex Deucher 2021-01-07 1006 break;
555fc7fbb2a2b2 Alex Deucher 2021-01-07 1007 default:
555fc7fbb2a2b2 Alex Deucher 2021-01-07 1008 DRM_DEBUG_KMS("Invalid request %d\n",
555fc7fbb2a2b2 Alex Deucher 2021-01-07 1009 info->video_cap.type);
555fc7fbb2a2b2 Alex Deucher 2021-01-07 1010 return -EINVAL;
555fc7fbb2a2b2 Alex Deucher 2021-01-07 1011 }
555fc7fbb2a2b2 Alex Deucher 2021-01-07 1012 for (i = 0; i < codecs->codec_count; i++) {
555fc7fbb2a2b2 Alex Deucher 2021-01-07 1013 int idx = codecs->codec_array[i].codec_type;
555fc7fbb2a2b2 Alex Deucher 2021-01-07 1014
555fc7fbb2a2b2 Alex Deucher 2021-01-07 1015 switch (idx) {
555fc7fbb2a2b2 Alex Deucher 2021-01-07 1016 case AMDGPU_VIDEO_CODEC_TYPE_MPEG2:
555fc7fbb2a2b2 Alex Deucher 2021-01-07 1017 case AMDGPU_VIDEO_CODEC_TYPE_MPEG4:
555fc7fbb2a2b2 Alex Deucher 2021-01-07 1018 case AMDGPU_VIDEO_CODEC_TYPE_MPEG4_AVC:
555fc7fbb2a2b2 Alex Deucher 2021-01-07 1019 case AMDGPU_VIDEO_CODEC_TYPE_VC1:
555fc7fbb2a2b2 Alex Deucher 2021-01-07 1020 case AMDGPU_VIDEO_CODEC_TYPE_HEVC:
555fc7fbb2a2b2 Alex Deucher 2021-01-07 1021 case AMDGPU_VIDEO_CODEC_TYPE_JPEG:
555fc7fbb2a2b2 Alex Deucher 2021-01-07 1022 case AMDGPU_VIDEO_CODEC_TYPE_VP9:
555fc7fbb2a2b2 Alex Deucher 2021-01-07 1023 case AMDGPU_VIDEO_CODEC_TYPE_AV1:
555fc7fbb2a2b2 Alex Deucher 2021-01-07 1024 caps->codec_info[idx].valid = 1;
555fc7fbb2a2b2 Alex Deucher 2021-01-07 1025 caps->codec_info[idx].max_width =
555fc7fbb2a2b2 Alex Deucher 2021-01-07 1026 codecs->codec_array[i].max_width;
555fc7fbb2a2b2 Alex Deucher 2021-01-07 1027 caps->codec_info[idx].max_height =
555fc7fbb2a2b2 Alex Deucher 2021-01-07 1028 codecs->codec_array[i].max_height;
555fc7fbb2a2b2 Alex Deucher 2021-01-07 1029 caps->codec_info[idx].max_level =
555fc7fbb2a2b2 Alex Deucher 2021-01-07 1030 codecs->codec_array[i].max_level;
555fc7fbb2a2b2 Alex Deucher 2021-01-07 1031 break;
555fc7fbb2a2b2 Alex Deucher 2021-01-07 1032 default:
555fc7fbb2a2b2 Alex Deucher 2021-01-07 1033 break;
555fc7fbb2a2b2 Alex Deucher 2021-01-07 1034 }
555fc7fbb2a2b2 Alex Deucher 2021-01-07 1035 }
555fc7fbb2a2b2 Alex Deucher 2021-01-07 1036 r = copy_to_user(out, caps,
555fc7fbb2a2b2 Alex Deucher 2021-01-07 1037 min((size_t)size, sizeof(*caps))) ? -EFAULT : 0;
555fc7fbb2a2b2 Alex Deucher 2021-01-07 1038 kfree(caps);
555fc7fbb2a2b2 Alex Deucher 2021-01-07 1039 return r;
555fc7fbb2a2b2 Alex Deucher 2021-01-07 1040 }
d38ceaf99ed015 Alex Deucher 2015-04-20 1041 default:
d38ceaf99ed015 Alex Deucher 2015-04-20 1042 DRM_DEBUG_KMS("Invalid request %d\n", info->query);
d38ceaf99ed015 Alex Deucher 2015-04-20 1043 return -EINVAL;
d38ceaf99ed015 Alex Deucher 2015-04-20 1044 }
d38ceaf99ed015 Alex Deucher 2015-04-20 1045 return 0;
d38ceaf99ed015 Alex Deucher 2015-04-20 1046 }
d38ceaf99ed015 Alex Deucher 2015-04-20 1047
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org
[-- Attachment #2: config.gz --]
[-- Type: application/gzip, Size: 34032 bytes --]
next reply other threads:[~2021-01-29 2:52 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-01-29 2:52 kernel test robot [this message]
-- strict thread matches above, loose matches on Subject: below --
2021-01-29 7:34 [agd5f:drm-next 50/60] drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c:999 amdgpu_info_ioctl() warn: possible memory leak of 'caps' Dan Carpenter
2021-01-29 7:34 ` Dan Carpenter
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=202101291053.Bimdgb2e-lkp@intel.com \
--to=lkp@intel.com \
--cc=kbuild@lists.01.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.