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Received: from shell.armlinux.org.uk ([fd8f:7570:feb6:1:5054:ff:fe00:4ec]:54192) by pandora.armlinux.org.uk with esmtpsa (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1l5Rgk-0000wa-Ak; Fri, 29 Jan 2021 11:11:42 +0000 Received: from linux by shell.armlinux.org.uk with local (Exim 4.92) (envelope-from ) id 1l5Rgh-0006qo-EX; Fri, 29 Jan 2021 11:11:39 +0000 Date: Fri, 29 Jan 2021 11:11:39 +0000 From: Russell King - ARM Linux admin To: Arnd Bergmann Subject: Re: [PATCH v5 4/4] ARM: Add support for Hisilicon Kunpeng L3 cache controller Message-ID: <20210129111139.GX1551@shell.armlinux.org.uk> References: <20210116032740.873-1-thunder.leizhen@huawei.com> <20210116032740.873-5-thunder.leizhen@huawei.com> <20dac713-25b7-cddf-cc42-69a834487c71@huawei.com> <20210129103340.GW1551@shell.armlinux.org.uk> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.10.1 (2018-07-13) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210129_061152_608090_99E56117 X-CRM114-Status: GOOD ( 17.67 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree , Arnd Bergmann , Greg Kroah-Hartman , Will Deacon , linux-kernel , Haojian Zhuang , Rob Herring , Wei Xu , "Leizhen \(ThunderTown\)" , linux-arm-kernel Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Fri, Jan 29, 2021 at 11:53:20AM +0100, Arnd Bergmann wrote: > On Fri, Jan 29, 2021 at 11:33 AM Russell King - ARM Linux admin > wrote: > > It is safer to put explicit barriers where it is necessary. > > > > Also remember that the barrier in readl() etc is _after_ the read, not > > before, and the barrier in writel() is _before_ the write, not after. > > The point is to ensure that DMA memory accesses are properly ordered > > with the IO-accessing instructions. > > > > So, using readl_relaxed() with a read-modify-write is entirely sensible > > provided you do not access DMA memory inbetween. > > The part I was not sure about is what happens when you have > a store to memory immediately before flushing the cache, and there > are no barriers inbetween. If the caches are non-coherent, we have to flush L1 before we flush L2 to ensure writebacks get pushed out properly, and L1 will already have the necessary barriers. If we have the situation where L1 is coherent but L2 isn't, then I think we have an "interesting situation" that we haven't considered whether it be in DT or elsewhere. -- RMK's Patch system: https://www.armlinux.org.uk/developer/patches/ FTTP is here! 40Mbps down 10Mbps up. Decent connectivity at last! _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel