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[82.27.183.148]) by smtp.gmail.com with ESMTPSA id c18sm14955709wmk.0.2021.02.03.03.36.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Feb 2021 03:36:19 -0800 (PST) Date: Wed, 3 Feb 2021 11:36:17 +0000 From: Leif Lindholm To: Peter Maydell Subject: Re: [RFC PATCH 4/4] hw/intc: make gicv3_idreg() distinguish between gicv3/gicv4 Message-ID: <20210203113617.GV1664@vanye> References: <20210124025306.3949-1-leif@nuviainc.com> <20210124025306.3949-5-leif@nuviainc.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.10.1 (2018-07-13) Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=leif@nuviainc.com; helo=mail-wr1-x42b.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Shashi Mallela , qemu-arm , QEMU Developers Errors-To: qemu-arm-bounces+alex.bennee=linaro.org@nongnu.org Sender: "Qemu-arm" X-TUID: Neol2fgx0cfA On Tue, Feb 02, 2021 at 10:31:16 +0000, Peter Maydell wrote: > On Sun, 24 Jan 2021 at 02:53, Leif Lindholm wrote: > > > > Make gicv3_idreg() able to return either gicv3 or gicv4 data. > > Add a parameter to specify gic version. > > > > Signed-off-by: Leif Lindholm > > --- > > hw/intc/arm_gicv3_dist.c | 2 +- > > hw/intc/arm_gicv3_redist.c | 2 +- > > hw/intc/gicv3_internal.h | 12 ++++++++++-- > > 3 files changed, 12 insertions(+), 4 deletions(-) > > > -static inline uint32_t gicv3_idreg(int regoffset) > > +static inline uint32_t gicv3_idreg(int regoffset, int revision) > > I would prefer to pass in the GICv3State* and let the function > look at s->revision. Yeah, that'd be neater. > > { > > /* Return the value of the CoreSight ID register at the specified > > * offset from the first ID register (as found in the distributor > > @@ -331,7 +331,15 @@ static inline uint32_t gicv3_idreg(int regoffset) > > static const uint8_t gicd_ids[] = { > > 0x44, 0x00, 0x00, 0x00, 0x92, 0xB4, 0x3B, 0x00, 0x0D, 0xF0, 0x05, 0xB1 > > }; > > - return gicd_ids[regoffset / 4]; > > + static const uint8_t gicdv4_ids[] = { > > + 0x44, 0x00, 0x00, 0x00, 0x92, 0xB4, 0x4B, 0x00, 0x0D, 0xF0, 0x05, 0xB1 > > + }; > > + > > + if (revision == 3) { > > + return gicd_ids[regoffset / 4]; > > + } else { > > + return gicdv4_ids[regoffset / 4]; > > + } > > } > > Updating the comment "These values indicate an ARM implementation of a GICv3" > to add a note about what the new values are indicating would be nice. Will do. Regards, Leif